[deliverable/linux.git] / drivers / i2c / busses / i2c-octeon.c

/*
 * (C) Copyright 2009-2010
 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
 *
 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
 *
 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/of.h>

#include <asm/octeon/octeon.h>

#define DRV_NAME "i2c-octeon"

/* Register offsets */
#define SW_TWSI			0x00
#define TWSI_INT		0x10

/* Controller command patterns */
#define SW_TWSI_V		BIT_ULL(63)	/* Valid bit */
#define SW_TWSI_R		BIT_ULL(56)	/* Result or read bit */

/* Controller opcode word (bits 60:57) */
#define SW_TWSI_OP_SHIFT	57
#define SW_TWSI_OP_TWSI_CLK	(4ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_EOP		(6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */

/* Controller extended opcode word (bits 34:32) */
#define SW_TWSI_EOP_SHIFT	32
#define SW_TWSI_EOP_TWSI_DATA	(SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CTL	(SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CLKCTL	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_STAT	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_RST	(SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)

/* Controller command and status bits */
#define TWSI_CTL_CE		0x80
#define TWSI_CTL_ENAB		0x40	/* Bus enable */
#define TWSI_CTL_STA		0x20	/* Master-mode start, HW clears when done */
#define TWSI_CTL_STP		0x10	/* Master-mode stop, HW clears when done */
#define TWSI_CTL_IFLG		0x08	/* HW event, SW writes 0 to ACK */
#define TWSI_CTL_AAK		0x04	/* Assert ACK */

/* Some status values */
#define STAT_START		0x08
#define STAT_RSTART		0x10
#define STAT_TXADDR_ACK		0x18
#define STAT_TXDATA_ACK		0x28
#define STAT_RXADDR_ACK		0x40
#define STAT_RXDATA_ACK		0x50
#define STAT_IDLE		0xF8

/* TWSI_INT values */
#define TWSI_INT_CORE_EN	BIT_ULL(6)
#define TWSI_INT_SDA_OVR	BIT_ULL(8)
#define TWSI_INT_SCL_OVR	BIT_ULL(9)

struct octeon_i2c {
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	int irq;
	u32 twsi_freq;
	int sys_freq;
	resource_size_t twsi_phys;
	void __iomem *twsi_base;
	resource_size_t regsize;
	struct device *dev;
};

/**
 * octeon_i2c_write_sw - write an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 * @data: Value to be written
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
{
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	} while ((tmp & SW_TWSI_V) != 0);
}

/**
 * octeon_i2c_read_sw - read lower bits of an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 *
 * Returns the data.
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
{
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	} while ((tmp & SW_TWSI_V) != 0);

	return tmp & 0xFF;
}

/**
 * octeon_i2c_write_int - write the TWSI_INT register
 * @i2c: The struct octeon_i2c
 * @data: Value to be written
 */
static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
{
	__raw_writeq(data, i2c->twsi_base + TWSI_INT);
	__raw_readq(i2c->twsi_base + TWSI_INT);
}

/**
 * octeon_i2c_int_enable - enable the CORE interrupt
 * @i2c: The struct octeon_i2c
 *
 * The interrupt will be asserted when there is non-STAT_IDLE state in
 * the SW_TWSI_EOP_TWSI_STAT register.
 */
static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
{
	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
}

/* disable the CORE interrupt */
static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
{
	/* clear TS/ST/IFLG events */
	octeon_i2c_write_int(i2c, 0);
}

/**
 * octeon_i2c_unblock - unblock the bus
 * @i2c: The struct octeon_i2c
 *
 * If there was a reset while a device was driving 0 to bus, bus is blocked.
 * We toggle it free manually by some clock cycles and send a stop.
 */
static void octeon_i2c_unblock(struct octeon_i2c *i2c)
{
	int i;

	dev_dbg(i2c->dev, "%s\n", __func__);

	for (i = 0; i < 9; i++) {
		octeon_i2c_write_int(i2c, 0);
		udelay(5);
		octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
		udelay(5);
	}
	/* hand-crank a STOP */
	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
	udelay(5);
	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
	udelay(5);
	octeon_i2c_write_int(i2c, 0);
}

/* interrupt service routine */
static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
{
	struct octeon_i2c *i2c = dev_id;

	octeon_i2c_int_disable(i2c);
	wake_up(&i2c->queue);

	return IRQ_HANDLED;
}


static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
{
	return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
}

/**
 * octeon_i2c_wait - wait for the IFLG to be set
 * @i2c: The struct octeon_i2c
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_wait(struct octeon_i2c *i2c)
{
	long time_left;

	octeon_i2c_int_enable(i2c);
	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
				       i2c->adap.timeout);
	octeon_i2c_int_disable(i2c);
	if (!time_left) {
		dev_dbg(i2c->dev, "%s: timeout\n", __func__);
		return -ETIMEDOUT;
	}

	return 0;
}

/**
 * octeon_i2c_start - send START to the bus
 * @i2c: The struct octeon_i2c
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_start(struct octeon_i2c *i2c)
{
	int result;
	u8 data;

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
			    TWSI_CTL_ENAB | TWSI_CTL_STA);

	result = octeon_i2c_wait(i2c);
	if (result) {
		if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
			/*
			 * Controller refused to send start flag May
			 * be a client is holding SDA low - let's try
			 * to free it.
			 */
			octeon_i2c_unblock(i2c);
			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB | TWSI_CTL_STA);
			result = octeon_i2c_wait(i2c);
		}
		if (result)
			return result;
	}

	data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
	if ((data != STAT_START) && (data != STAT_RSTART)) {
		dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
		return -EIO;
	}

	return 0;
}

/* send STOP to the bus */
static void octeon_i2c_stop(struct octeon_i2c *i2c)
{
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
			    TWSI_CTL_ENAB | TWSI_CTL_STP);
}

/**
 * octeon_i2c_write - send data to the bus via low-level controller
 * @i2c: The struct octeon_i2c
 * @target: Target address
 * @data: Pointer to the data to be sent
 * @length: Length of the data
 *
 * The address is sent over the bus, then the data.
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
			    const u8 *data, int length)
{
	int i, result;
	u8 tmp;

	result = octeon_i2c_start(i2c);
	if (result)
		return result;

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	result = octeon_i2c_wait(i2c);
	if (result)
		return result;

	for (i = 0; i < length; i++) {
		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

		if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
			dev_err(i2c->dev,
				"%s: bad status before write (0x%x)\n",
				__func__, tmp);
			return -EIO;
		}

		octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
		octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

		result = octeon_i2c_wait(i2c);
		if (result)
			return result;
	}

	return 0;
}

/**
 * octeon_i2c_read - receive data from the bus via low-level controller
 * @i2c: The struct octeon_i2c
 * @target: Target address
 * @data: Pointer to the location to store the data
 * @length: Length of the data
 *
 * The address is sent over the bus, then the data is read.
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
			   u8 *data, int length)
{
	int i, result;
	u8 tmp;

	if (length < 1)
		return -EINVAL;

	result = octeon_i2c_start(i2c);
	if (result)
		return result;

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	result = octeon_i2c_wait(i2c);
	if (result)
		return result;

	for (i = 0; i < length; i++) {
		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

		if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
			dev_err(i2c->dev,
				"%s: bad status before read (0x%x)\n",
				__func__, tmp);
			return -EIO;
		}

		if (i + 1 < length)
			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB | TWSI_CTL_AAK);
		else
			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB);

		result = octeon_i2c_wait(i2c);
		if (result)
			return result;

		data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
	}
	return 0;
}

/**
 * octeon_i2c_xfer - The driver's master_xfer function
 * @adap: Pointer to the i2c_adapter structure
 * @msgs: Pointer to the messages to be processed
 * @num: Length of the MSGS array
 *
 * Returns the number of messages processed, or a negative errno on failure.
 */
static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
			   int num)
{
	struct octeon_i2c *i2c = i2c_get_adapdata(adap);
	int i, ret = 0;

	for (i = 0; ret == 0 && i < num; i++) {
		struct i2c_msg *pmsg = &msgs[i];

		dev_dbg(i2c->dev,
			"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
			 pmsg->flags & I2C_M_RD ? "read" : "write",
			 pmsg->len, pmsg->addr, i + 1, num);
		if (pmsg->flags & I2C_M_RD)
			ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
					      pmsg->len);
		else
			ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
					       pmsg->len);
	}
	octeon_i2c_stop(i2c);

	return (ret != 0) ? ret : num;
}

static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm octeon_i2c_algo = {
	.master_xfer = octeon_i2c_xfer,
	.functionality = octeon_i2c_functionality,
};

static struct i2c_adapter octeon_i2c_ops = {
	.owner = THIS_MODULE,
	.name = "OCTEON adapter",
	.algo = &octeon_i2c_algo,
	.timeout = HZ / 50,
};

/* calculate and set clock divisors */
static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
{
	int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;

	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
		/*
		 * An mdiv value of less than 2 seems to not work well
		 * with ds1337 RTCs, so we constrain it to larger values.
		 */
		for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
			/*
			 * For given ndiv and mdiv values check the
			 * two closest thp values.
			 */
			tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
			tclk *= (1 << ndiv_idx);
			thp_base = (i2c->sys_freq / (tclk * 2)) - 1;

			for (inc = 0; inc <= 1; inc++) {
				thp_idx = thp_base + inc;
				if (thp_idx < 5 || thp_idx > 0xff)
					continue;

				foscl = i2c->sys_freq / (2 * (thp_idx + 1));
				foscl = foscl / (1 << ndiv_idx);
				foscl = foscl / (mdiv_idx + 1) / 10;
				diff = abs(foscl - i2c->twsi_freq);
				if (diff < delta_hz) {
					delta_hz = diff;
					thp = thp_idx;
					mdiv = mdiv_idx;
					ndiv = ndiv_idx;
				}
			}
		}
	}
	octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
}

static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
{
	u8 status;
	int tries;

	/* disable high level controller, enable bus access */
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	/* reset controller */
	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);

	for (tries = 10; tries; tries--) {
		udelay(1);
		status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
		if (status == STAT_IDLE)
			return 0;
	}
	dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
	return -EIO;
}

static int octeon_i2c_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct resource *res_mem;
	struct octeon_i2c *i2c;
	int irq, result = 0;

	/* All adaptors have an irq.  */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c) {
		result = -ENOMEM;
		goto out;
	}
	i2c->dev = &pdev->dev;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (res_mem == NULL) {
		dev_err(i2c->dev, "found no memory resource\n");
		result = -ENXIO;
		goto out;
	}
	i2c->twsi_phys = res_mem->start;
	i2c->regsize = resource_size(res_mem);

	/*
	 * "clock-rate" is a legacy binding, the official binding is
	 * "clock-frequency".  Try the official one first and then
	 * fall back if it doesn't exist.
	 */
	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
	    of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
		dev_err(i2c->dev,
			"no I2C 'clock-rate' or 'clock-frequency' property\n");
		result = -ENXIO;
		goto out;
	}

	i2c->sys_freq = octeon_get_io_clock_rate();

	if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
				     res_mem->name)) {
		dev_err(i2c->dev, "request_mem_region failed\n");
		goto out;
	}
	i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);

	init_waitqueue_head(&i2c->queue);

	i2c->irq = irq;

	result = devm_request_irq(&pdev->dev, i2c->irq,
				  octeon_i2c_isr, 0, DRV_NAME, i2c);
	if (result < 0) {
		dev_err(i2c->dev, "failed to attach interrupt\n");
		goto out;
	}

	result = octeon_i2c_init_lowlevel(i2c);
	if (result) {
		dev_err(i2c->dev, "init low level failed\n");
		goto  out;
	}

	octeon_i2c_set_clock(i2c);

	i2c->adap = octeon_i2c_ops;
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = node;
	i2c_set_adapdata(&i2c->adap, i2c);
	platform_set_drvdata(pdev, i2c);

	result = i2c_add_adapter(&i2c->adap);
	if (result < 0) {
		dev_err(i2c->dev, "failed to add adapter\n");
		goto out;
	}
	dev_info(i2c->dev, "probed\n");
	return 0;

out:
	return result;
};

static int octeon_i2c_remove(struct platform_device *pdev)
{
	struct octeon_i2c *i2c = platform_get_drvdata(pdev);

	i2c_del_adapter(&i2c->adap);
	return 0;
};

static const struct of_device_id octeon_i2c_match[] = {
	{ .compatible = "cavium,octeon-3860-twsi", },
	{},
};
MODULE_DEVICE_TABLE(of, octeon_i2c_match);

static struct platform_driver octeon_i2c_driver = {
	.probe		= octeon_i2c_probe,
	.remove		= octeon_i2c_remove,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = octeon_i2c_match,
	},
};

module_platform_driver(octeon_i2c_driver);

MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
85660f43 RB	1	/*
	2	* (C) Copyright 2009-2010
	3	* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
	4	*
dfcd8212	5	* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
85660f43 RB	6	*
	7	* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
f353a218 DD	14	#include <linux/platform_device.h>
f353a218 DD	15	#include <linux/interrupt.h>
85660f43 RB	16	#include <linux/kernel.h>
85660f43 RB	17	#include <linux/module.h>
f353a218	18	#include <linux/delay.h>
85660f43	19	#include <linux/sched.h>
5a0e3ad6	20	#include <linux/slab.h>
85660f43	21	#include <linux/i2c.h>
f353a218 DD	22	#include <linux/io.h>
f353a218 DD	23	#include <linux/of.h>
85660f43 RB	24
	25	#include <asm/octeon/octeon.h>
	26
	27	#define DRV_NAME "i2c-octeon"
	28
dfcd8212 JG	29	/* Register offsets */
	30	#define SW_TWSI 0x00
	31	#define TWSI_INT 0x10
85660f43 RB	32
85660f43 RB	33	/* Controller command patterns */
dfcd8212 JG	34	#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
	35	#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
	36
	37	/* Controller opcode word (bits 60:57) */
	38	#define SW_TWSI_OP_SHIFT 57
	39	#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
	40	#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
	41
	42	/* Controller extended opcode word (bits 34:32) */
	43	#define SW_TWSI_EOP_SHIFT 32
	44	#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP \| 1ULL << SW_TWSI_EOP_SHIFT)
	45	#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP \| 2ULL << SW_TWSI_EOP_SHIFT)
	46	#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	47	#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	48	#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP \| 7ULL << SW_TWSI_EOP_SHIFT)
85660f43 RB	49
85660f43 RB	50	/* Controller command and status bits */
dfcd8212 JG	51	#define TWSI_CTL_CE 0x80
	52	#define TWSI_CTL_ENAB 0x40 /* Bus enable */
	53	#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
	54	#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
	55	#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
	56	#define TWSI_CTL_AAK 0x04 /* Assert ACK */
85660f43 RB	57
85660f43 RB	58	/* Some status values */
dfcd8212 JG	59	#define STAT_START 0x08
	60	#define STAT_RSTART 0x10
	61	#define STAT_TXADDR_ACK 0x18
	62	#define STAT_TXDATA_ACK 0x28
	63	#define STAT_RXADDR_ACK 0x40
	64	#define STAT_RXDATA_ACK 0x50
	65	#define STAT_IDLE 0xF8
	66
	67	/* TWSI_INT values */
	68	#define TWSI_INT_CORE_EN BIT_ULL(6)
	69	#define TWSI_INT_SDA_OVR BIT_ULL(8)
	70	#define TWSI_INT_SCL_OVR BIT_ULL(9)
85660f43 RB	71
	72	struct octeon_i2c {
	73	wait_queue_head_t queue;
	74	struct i2c_adapter adap;
	75	int irq;
f353a218	76	u32 twsi_freq;
85660f43 RB	77	int sys_freq;
	78	resource_size_t twsi_phys;
	79	void __iomem *twsi_base;
	80	resource_size_t regsize;
	81	struct device *dev;
	82	};
	83
	84	/**
bd7784c2 JG	85	* octeon_i2c_write_sw - write an I2C core register
	86	* @i2c: The struct octeon_i2c
	87	* @eop_reg: Register selector
	88	* @data: Value to be written
85660f43 RB	89	*
	90	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	91	*/
dfcd8212	92	static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
85660f43 RB	93	{
	94	u64 tmp;
	95
	96	__raw_writeq(SW_TWSI_V \| eop_reg \| data, i2c->twsi_base + SW_TWSI);
	97	do {
	98	tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	99	} while ((tmp & SW_TWSI_V) != 0);
	100	}
	101
	102	/**
dfcd8212	103	* octeon_i2c_read_sw - read lower bits of an I2C core register
bd7784c2 JG	104	* @i2c: The struct octeon_i2c
bd7784c2 JG	105	* @eop_reg: Register selector
85660f43 RB	106	*
	107	* Returns the data.
	108	*
	109	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	110	*/
	111	static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
	112	{
	113	u64 tmp;
	114
	115	__raw_writeq(SW_TWSI_V \| eop_reg \| SW_TWSI_R, i2c->twsi_base + SW_TWSI);
	116	do {
	117	tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	118	} while ((tmp & SW_TWSI_V) != 0);
	119
	120	return tmp & 0xFF;
	121	}
	122
	123	/**
	124	* octeon_i2c_write_int - write the TWSI_INT register
bd7784c2 JG	125	* @i2c: The struct octeon_i2c
bd7784c2 JG	126	* @data: Value to be written
85660f43 RB	127	*/
	128	static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
	129	{
85660f43	130	__raw_writeq(data, i2c->twsi_base + TWSI_INT);
f353a218	131	__raw_readq(i2c->twsi_base + TWSI_INT);
85660f43 RB	132	}
	133
	134	/**
bd7784c2 JG	135	* octeon_i2c_int_enable - enable the CORE interrupt
bd7784c2 JG	136	* @i2c: The struct octeon_i2c
85660f43 RB	137	*
	138	* The interrupt will be asserted when there is non-STAT_IDLE state in
	139	* the SW_TWSI_EOP_TWSI_STAT register.
	140	*/
	141	static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
	142	{
dfcd8212	143	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
85660f43 RB	144	}
85660f43 RB	145
bd7784c2	146	/* disable the CORE interrupt */
85660f43 RB	147	static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
85660f43 RB	148	{
dfcd8212	149	/* clear TS/ST/IFLG events */
85660f43 RB	150	octeon_i2c_write_int(i2c, 0);
	151	}
	152
	153	/**
bd7784c2 JG	154	* octeon_i2c_unblock - unblock the bus
bd7784c2 JG	155	* @i2c: The struct octeon_i2c
85660f43	156	*
bd7784c2 JG	157	* If there was a reset while a device was driving 0 to bus, bus is blocked.
bd7784c2 JG	158	* We toggle it free manually by some clock cycles and send a stop.
85660f43 RB	159	*/
	160	static void octeon_i2c_unblock(struct octeon_i2c *i2c)
	161	{
	162	int i;
	163
	164	dev_dbg(i2c->dev, "%s\n", __func__);
dfcd8212	165
85660f43	166	for (i = 0; i < 9; i++) {
dfcd8212	167	octeon_i2c_write_int(i2c, 0);
85660f43	168	udelay(5);
dfcd8212	169	octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
85660f43 RB	170	udelay(5);
85660f43 RB	171	}
dfcd8212 JG	172	/* hand-crank a STOP */
dfcd8212 JG	173	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR \| TWSI_INT_SCL_OVR);
85660f43	174	udelay(5);
dfcd8212	175	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
85660f43	176	udelay(5);
dfcd8212	177	octeon_i2c_write_int(i2c, 0);
85660f43 RB	178	}
85660f43 RB	179
bd7784c2	180	/* interrupt service routine */
85660f43 RB	181	static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
	182	{
	183	struct octeon_i2c *i2c = dev_id;
	184
	185	octeon_i2c_int_disable(i2c);
2637e5fd	186	wake_up(&i2c->queue);
85660f43 RB	187
	188	return IRQ_HANDLED;
	189	}
	190
	191
	192	static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
	193	{
	194	return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
	195	}
	196
	197	/**
bd7784c2 JG	198	* octeon_i2c_wait - wait for the IFLG to be set
bd7784c2 JG	199	* @i2c: The struct octeon_i2c
85660f43 RB	200	*
	201	* Returns 0 on success, otherwise a negative errno.
	202	*/
	203	static int octeon_i2c_wait(struct octeon_i2c *i2c)
	204	{
dfcd8212	205	long time_left;
85660f43 RB	206
85660f43 RB	207	octeon_i2c_int_enable(i2c);
dfcd8212 JG	208	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
dfcd8212 JG	209	i2c->adap.timeout);
85660f43	210	octeon_i2c_int_disable(i2c);
dfcd8212	211	if (!time_left) {
85660f43	212	dev_dbg(i2c->dev, "%s: timeout\n", __func__);
cc33e542	213	return -ETIMEDOUT;
85660f43 RB	214	}
	215
	216	return 0;
	217	}
	218
	219	/**
bd7784c2 JG	220	* octeon_i2c_start - send START to the bus
bd7784c2 JG	221	* @i2c: The struct octeon_i2c
85660f43 RB	222	*
	223	* Returns 0 on success, otherwise a negative errno.
	224	*/
	225	static int octeon_i2c_start(struct octeon_i2c *i2c)
	226	{
85660f43	227	int result;
dfcd8212	228	u8 data;
85660f43 RB	229
85660f43 RB	230	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	231	TWSI_CTL_ENAB \| TWSI_CTL_STA);
85660f43 RB	232
	233	result = octeon_i2c_wait(i2c);
	234	if (result) {
	235	if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
	236	/*
	237	* Controller refused to send start flag May
	238	* be a client is holding SDA low - let's try
	239	* to free it.
	240	*/
	241	octeon_i2c_unblock(i2c);
	242	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
	243	TWSI_CTL_ENAB \| TWSI_CTL_STA);
85660f43 RB	244	result = octeon_i2c_wait(i2c);
	245	}
	246	if (result)
	247	return result;
	248	}
	249
	250	data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
	251	if ((data != STAT_START) && (data != STAT_RSTART)) {
	252	dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
	253	return -EIO;
	254	}
	255
	256	return 0;
	257	}
	258
dfcd8212 JG	259	/* send STOP to the bus */
dfcd8212 JG	260	static void octeon_i2c_stop(struct octeon_i2c *i2c)
85660f43	261	{
85660f43 RB	262	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
85660f43 RB	263	TWSI_CTL_ENAB \| TWSI_CTL_STP);
85660f43 RB	264	}
	265
	266	/**
bd7784c2 JG	267	* octeon_i2c_write - send data to the bus via low-level controller
	268	* @i2c: The struct octeon_i2c
	269	* @target: Target address
	270	* @data: Pointer to the data to be sent
	271	* @length: Length of the data
85660f43 RB	272	*
	273	* The address is sent over the bus, then the data.
	274	*
	275	* Returns 0 on success, otherwise a negative errno.
	276	*/
	277	static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
	278	const u8 *data, int length)
	279	{
	280	int i, result;
	281	u8 tmp;
	282
	283	result = octeon_i2c_start(i2c);
	284	if (result)
	285	return result;
	286
	287	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
	288	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
	289
	290	result = octeon_i2c_wait(i2c);
	291	if (result)
	292	return result;
	293
	294	for (i = 0; i < length; i++) {
	295	tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
dfcd8212	296
85660f43 RB	297	if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
	298	dev_err(i2c->dev,
	299	"%s: bad status before write (0x%x)\n",
	300	__func__, tmp);
	301	return -EIO;
	302	}
	303
	304	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
	305	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
	306
	307	result = octeon_i2c_wait(i2c);
	308	if (result)
	309	return result;
	310	}
	311
	312	return 0;
	313	}
	314
	315	/**
bd7784c2 JG	316	* octeon_i2c_read - receive data from the bus via low-level controller
	317	* @i2c: The struct octeon_i2c
	318	* @target: Target address
	319	* @data: Pointer to the location to store the data
	320	* @length: Length of the data
85660f43 RB	321	*
	322	* The address is sent over the bus, then the data is read.
	323	*
	324	* Returns 0 on success, otherwise a negative errno.
	325	*/
	326	static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
	327	u8 *data, int length)
	328	{
	329	int i, result;
	330	u8 tmp;
	331
	332	if (length < 1)
	333	return -EINVAL;
	334
	335	result = octeon_i2c_start(i2c);
	336	if (result)
	337	return result;
	338
dfcd8212	339	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) \| 1);
85660f43 RB	340	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
	341
	342	result = octeon_i2c_wait(i2c);
	343	if (result)
	344	return result;
	345
	346	for (i = 0; i < length; i++) {
	347	tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
dfcd8212	348
85660f43 RB	349	if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
	350	dev_err(i2c->dev,
	351	"%s: bad status before read (0x%x)\n",
	352	__func__, tmp);
	353	return -EIO;
	354	}
	355
dfcd8212	356	if (i + 1 < length)
85660f43	357	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	358	TWSI_CTL_ENAB \| TWSI_CTL_AAK);
85660f43 RB	359	else
85660f43 RB	360	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	361	TWSI_CTL_ENAB);
85660f43 RB	362
	363	result = octeon_i2c_wait(i2c);
	364	if (result)
	365	return result;
	366
	367	data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
	368	}
	369	return 0;
	370	}
	371
	372	/**
bd7784c2 JG	373	* octeon_i2c_xfer - The driver's master_xfer function
	374	* @adap: Pointer to the i2c_adapter structure
	375	* @msgs: Pointer to the messages to be processed
	376	* @num: Length of the MSGS array
85660f43	377	*
bd7784c2	378	* Returns the number of messages processed, or a negative errno on failure.
85660f43	379	*/
dfcd8212	380	static int octeon_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
85660f43 RB	381	int num)
85660f43 RB	382	{
85660f43	383	struct octeon_i2c *i2c = i2c_get_adapdata(adap);
dfcd8212	384	int i, ret = 0;
85660f43 RB	385
85660f43 RB	386	for (i = 0; ret == 0 && i < num; i++) {
dfcd8212 JG	387	struct i2c_msg *pmsg = &msgs[i];
dfcd8212 JG	388
85660f43 RB	389	dev_dbg(i2c->dev,
	390	"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
	391	pmsg->flags & I2C_M_RD ? "read" : "write",
	392	pmsg->len, pmsg->addr, i + 1, num);
	393	if (pmsg->flags & I2C_M_RD)
	394	ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
dfcd8212	395	pmsg->len);
85660f43 RB	396	else
85660f43 RB	397	ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
dfcd8212	398	pmsg->len);
85660f43 RB	399	}
	400	octeon_i2c_stop(i2c);
	401
	402	return (ret != 0) ? ret : num;
	403	}
	404
	405	static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
	406	{
	407	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	408	}
	409
	410	static const struct i2c_algorithm octeon_i2c_algo = {
	411	.master_xfer = octeon_i2c_xfer,
	412	.functionality = octeon_i2c_functionality,
	413	};
	414
	415	static struct i2c_adapter octeon_i2c_ops = {
	416	.owner = THIS_MODULE,
	417	.name = "OCTEON adapter",
	418	.algo = &octeon_i2c_algo,
73f37dc3	419	.timeout = HZ / 50,
85660f43 RB	420	};
85660f43 RB	421
bd7784c2	422	/* calculate and set clock divisors */
dfcd8212	423	static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
85660f43 RB	424	{
	425	int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
	426	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
	427
	428	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
	429	/*
	430	* An mdiv value of less than 2 seems to not work well
dfcd8212	431	* with ds1337 RTCs, so we constrain it to larger values.
85660f43 RB	432	*/
	433	for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
	434	/*
	435	* For given ndiv and mdiv values check the
	436	* two closest thp values.
	437	*/
	438	tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
	439	tclk *= (1 << ndiv_idx);
	440	thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
dfcd8212	441
85660f43 RB	442	for (inc = 0; inc <= 1; inc++) {
	443	thp_idx = thp_base + inc;
	444	if (thp_idx < 5 \|\| thp_idx > 0xff)
	445	continue;
	446
	447	foscl = i2c->sys_freq / (2 * (thp_idx + 1));
	448	foscl = foscl / (1 << ndiv_idx);
	449	foscl = foscl / (mdiv_idx + 1) / 10;
	450	diff = abs(foscl - i2c->twsi_freq);
	451	if (diff < delta_hz) {
	452	delta_hz = diff;
	453	thp = thp_idx;
	454	mdiv = mdiv_idx;
	455	ndiv = ndiv_idx;
	456	}
	457	}
	458	}
	459	}
	460	octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
	461	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) \| ndiv);
85660f43 RB	462	}
85660f43 RB	463
dfcd8212	464	static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
85660f43 RB	465	{
	466	u8 status;
	467	int tries;
	468
	469	/* disable high level controller, enable bus access */
	470	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
	471
	472	/* reset controller */
	473	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
	474
	475	for (tries = 10; tries; tries--) {
	476	udelay(1);
	477	status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
	478	if (status == STAT_IDLE)
	479	return 0;
	480	}
	481	dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
	482	return -EIO;
	483	}
	484
0b255e92	485	static int octeon_i2c_probe(struct platform_device *pdev)
85660f43	486	{
dfcd8212	487	struct device_node *node = pdev->dev.of_node;
85660f43	488	struct resource *res_mem;
dfcd8212 JG	489	struct octeon_i2c *i2c;
dfcd8212 JG	490	int irq, result = 0;
85660f43 RB	491
	492	/* All adaptors have an irq. */
	493	irq = platform_get_irq(pdev, 0);
	494	if (irq < 0)
	495	return irq;
	496
f353a218	497	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
85660f43	498	if (!i2c) {
85660f43 RB	499	result = -ENOMEM;
	500	goto out;
	501	}
	502	i2c->dev = &pdev->dev;
85660f43 RB	503
	504	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	505
	506	if (res_mem == NULL) {
	507	dev_err(i2c->dev, "found no memory resource\n");
	508	result = -ENXIO;
f353a218	509	goto out;
85660f43	510	}
f353a218 DD	511	i2c->twsi_phys = res_mem->start;
f353a218 DD	512	i2c->regsize = resource_size(res_mem);
85660f43	513
f353a218 DD	514	/*
	515	* "clock-rate" is a legacy binding, the official binding is
	516	* "clock-frequency". Try the official one first and then
	517	* fall back if it doesn't exist.
	518	*/
dfcd8212 JG	519	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
dfcd8212 JG	520	of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
f353a218 DD	521	dev_err(i2c->dev,
f353a218 DD	522	"no I2C 'clock-rate' or 'clock-frequency' property\n");
85660f43	523	result = -ENXIO;
f353a218	524	goto out;
85660f43 RB	525	}
85660f43 RB	526
f353a218	527	i2c->sys_freq = octeon_get_io_clock_rate();
85660f43	528
f353a218	529	if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
dfcd8212	530	res_mem->name)) {
85660f43	531	dev_err(i2c->dev, "request_mem_region failed\n");
f353a218	532	goto out;
85660f43	533	}
f353a218	534	i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
85660f43 RB	535
	536	init_waitqueue_head(&i2c->queue);
	537
	538	i2c->irq = irq;
	539
f353a218 DD	540	result = devm_request_irq(&pdev->dev, i2c->irq,
f353a218 DD	541	octeon_i2c_isr, 0, DRV_NAME, i2c);
85660f43 RB	542	if (result < 0) {
85660f43 RB	543	dev_err(i2c->dev, "failed to attach interrupt\n");
f353a218	544	goto out;
85660f43 RB	545	}
85660f43 RB	546
dfcd8212	547	result = octeon_i2c_init_lowlevel(i2c);
85660f43 RB	548	if (result) {
85660f43 RB	549	dev_err(i2c->dev, "init low level failed\n");
f353a218	550	goto out;
85660f43 RB	551	}
85660f43 RB	552
dfcd8212	553	octeon_i2c_set_clock(i2c);
85660f43 RB	554
	555	i2c->adap = octeon_i2c_ops;
	556	i2c->adap.dev.parent = &pdev->dev;
dfcd8212	557	i2c->adap.dev.of_node = node;
85660f43 RB	558	i2c_set_adapdata(&i2c->adap, i2c);
	559	platform_set_drvdata(pdev, i2c);
	560
f353a218	561	result = i2c_add_adapter(&i2c->adap);
85660f43 RB	562	if (result < 0) {
85660f43 RB	563	dev_err(i2c->dev, "failed to add adapter\n");
55827f4a	564	goto out;
85660f43	565	}
dfcd8212	566	dev_info(i2c->dev, "probed\n");
f353a218	567	return 0;
85660f43	568
85660f43 RB	569	out:
	570	return result;
	571	};
	572
0b255e92	573	static int octeon_i2c_remove(struct platform_device *pdev)
85660f43 RB	574	{
	575	struct octeon_i2c *i2c = platform_get_drvdata(pdev);
	576
	577	i2c_del_adapter(&i2c->adap);
85660f43 RB	578	return 0;
	579	};
	580
dfcd8212 JG	581	static const struct of_device_id octeon_i2c_match[] = {
dfcd8212 JG	582	{ .compatible = "cavium,octeon-3860-twsi", },
f353a218 DD	583	{},
	584	};
	585	MODULE_DEVICE_TABLE(of, octeon_i2c_match);
	586
85660f43 RB	587	static struct platform_driver octeon_i2c_driver = {
85660f43 RB	588	.probe = octeon_i2c_probe,
0b255e92	589	.remove = octeon_i2c_remove,
85660f43	590	.driver = {
85660f43	591	.name = DRV_NAME,
f353a218	592	.of_match_table = octeon_i2c_match,
85660f43 RB	593	},
	594	};
	595
a3664b51	596	module_platform_driver(octeon_i2c_driver);
85660f43 RB	597
	598	MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
	599	MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
	600	MODULE_LICENSE("GPL");