Commit | Line | Data |
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beb58aa3 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * SMBus host driver for PA Semi PWRficient | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
beb58aa3 OJ |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/stddef.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/delay.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
21782180 | 24 | #include <linux/io.h> |
beb58aa3 OJ |
25 | |
26 | static struct pci_driver pasemi_smb_driver; | |
27 | ||
28 | struct pasemi_smbus { | |
29 | struct pci_dev *dev; | |
30 | struct i2c_adapter adapter; | |
31 | unsigned long base; | |
32 | int size; | |
33 | }; | |
34 | ||
35 | /* Register offsets */ | |
36 | #define REG_MTXFIFO 0x00 | |
37 | #define REG_MRXFIFO 0x04 | |
38 | #define REG_SMSTA 0x14 | |
39 | #define REG_CTL 0x1c | |
40 | ||
41 | /* Register defs */ | |
42 | #define MTXFIFO_READ 0x00000400 | |
43 | #define MTXFIFO_STOP 0x00000200 | |
44 | #define MTXFIFO_START 0x00000100 | |
45 | #define MTXFIFO_DATA_M 0x000000ff | |
46 | ||
47 | #define MRXFIFO_EMPTY 0x00000100 | |
48 | #define MRXFIFO_DATA_M 0x000000ff | |
49 | ||
50 | #define SMSTA_XEN 0x08000000 | |
be8a1f7c | 51 | #define SMSTA_MTN 0x00200000 |
beb58aa3 OJ |
52 | |
53 | #define CTL_MRR 0x00000400 | |
54 | #define CTL_MTR 0x00000200 | |
55 | #define CTL_CLK_M 0x000000ff | |
56 | ||
57 | #define CLK_100K_DIV 84 | |
58 | #define CLK_400K_DIV 21 | |
59 | ||
60 | static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) | |
61 | { | |
62 | dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n", | |
63 | smbus->base + reg, val); | |
64 | outl(val, smbus->base + reg); | |
65 | } | |
66 | ||
67 | static inline int reg_read(struct pasemi_smbus *smbus, int reg) | |
68 | { | |
69 | int ret; | |
70 | ret = inl(smbus->base + reg); | |
71 | dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n", | |
72 | smbus->base + reg, ret); | |
73 | return ret; | |
74 | } | |
75 | ||
76 | #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) | |
77 | #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO) | |
78 | ||
79 | static void pasemi_smb_clear(struct pasemi_smbus *smbus) | |
80 | { | |
81 | unsigned int status; | |
82 | ||
83 | status = reg_read(smbus, REG_SMSTA); | |
84 | reg_write(smbus, REG_SMSTA, status); | |
85 | } | |
86 | ||
80322143 | 87 | static int pasemi_smb_waitready(struct pasemi_smbus *smbus) |
beb58aa3 OJ |
88 | { |
89 | int timeout = 10; | |
90 | unsigned int status; | |
91 | ||
92 | status = reg_read(smbus, REG_SMSTA); | |
93 | ||
94 | while (!(status & SMSTA_XEN) && timeout--) { | |
95 | msleep(1); | |
96 | status = reg_read(smbus, REG_SMSTA); | |
97 | } | |
98 | ||
be8a1f7c OJ |
99 | /* Got NACK? */ |
100 | if (status & SMSTA_MTN) | |
101 | return -ENXIO; | |
102 | ||
beb58aa3 OJ |
103 | if (timeout < 0) { |
104 | dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status); | |
105 | reg_write(smbus, REG_SMSTA, status); | |
106 | return -ETIME; | |
107 | } | |
108 | ||
109 | /* Clear XEN */ | |
110 | reg_write(smbus, REG_SMSTA, SMSTA_XEN); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter, | |
116 | struct i2c_msg *msg, int stop) | |
117 | { | |
118 | struct pasemi_smbus *smbus = adapter->algo_data; | |
119 | int read, i, err; | |
120 | u32 rd; | |
121 | ||
122 | read = msg->flags & I2C_M_RD ? 1 : 0; | |
123 | ||
124 | TXFIFO_WR(smbus, MTXFIFO_START | (msg->addr << 1) | read); | |
125 | ||
126 | if (read) { | |
127 | TXFIFO_WR(smbus, msg->len | MTXFIFO_READ | | |
128 | (stop ? MTXFIFO_STOP : 0)); | |
129 | ||
130 | err = pasemi_smb_waitready(smbus); | |
131 | if (err) | |
132 | goto reset_out; | |
133 | ||
134 | for (i = 0; i < msg->len; i++) { | |
135 | rd = RXFIFO_RD(smbus); | |
136 | if (rd & MRXFIFO_EMPTY) { | |
137 | err = -ENODATA; | |
138 | goto reset_out; | |
139 | } | |
140 | msg->buf[i] = rd & MRXFIFO_DATA_M; | |
141 | } | |
142 | } else { | |
143 | for (i = 0; i < msg->len - 1; i++) | |
144 | TXFIFO_WR(smbus, msg->buf[i]); | |
145 | ||
080dfbe1 | 146 | TXFIFO_WR(smbus, msg->buf[msg->len-1] | |
beb58aa3 OJ |
147 | (stop ? MTXFIFO_STOP : 0)); |
148 | } | |
149 | ||
150 | return 0; | |
151 | ||
152 | reset_out: | |
153 | reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | | |
154 | (CLK_100K_DIV & CTL_CLK_M))); | |
155 | return err; | |
156 | } | |
157 | ||
158 | static int pasemi_i2c_xfer(struct i2c_adapter *adapter, | |
159 | struct i2c_msg *msgs, int num) | |
160 | { | |
161 | struct pasemi_smbus *smbus = adapter->algo_data; | |
162 | int ret, i; | |
163 | ||
164 | pasemi_smb_clear(smbus); | |
165 | ||
166 | ret = 0; | |
167 | ||
168 | for (i = 0; i < num && !ret; i++) | |
169 | ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1))); | |
170 | ||
171 | return ret ? ret : num; | |
172 | } | |
173 | ||
174 | static int pasemi_smb_xfer(struct i2c_adapter *adapter, | |
175 | u16 addr, unsigned short flags, char read_write, u8 command, | |
176 | int size, union i2c_smbus_data *data) | |
177 | { | |
178 | struct pasemi_smbus *smbus = adapter->algo_data; | |
179 | unsigned int rd; | |
180 | int read_flag, err; | |
181 | int len = 0, i; | |
182 | ||
183 | /* All our ops take 8-bit shifted addresses */ | |
184 | addr <<= 1; | |
185 | read_flag = read_write == I2C_SMBUS_READ; | |
186 | ||
187 | pasemi_smb_clear(smbus); | |
188 | ||
189 | switch (size) { | |
190 | case I2C_SMBUS_QUICK: | |
191 | TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START | | |
192 | MTXFIFO_STOP); | |
193 | break; | |
194 | case I2C_SMBUS_BYTE: | |
195 | TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START); | |
196 | if (read_write) | |
197 | TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ); | |
198 | else | |
199 | TXFIFO_WR(smbus, MTXFIFO_STOP | command); | |
200 | break; | |
201 | case I2C_SMBUS_BYTE_DATA: | |
202 | TXFIFO_WR(smbus, addr | MTXFIFO_START); | |
203 | TXFIFO_WR(smbus, command); | |
204 | if (read_write) { | |
205 | TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); | |
206 | TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP); | |
207 | } else { | |
208 | TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte); | |
209 | } | |
210 | break; | |
211 | case I2C_SMBUS_WORD_DATA: | |
212 | TXFIFO_WR(smbus, addr | MTXFIFO_START); | |
213 | TXFIFO_WR(smbus, command); | |
214 | if (read_write) { | |
215 | TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); | |
216 | TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP); | |
217 | } else { | |
218 | TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M); | |
219 | TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8)); | |
220 | } | |
221 | break; | |
222 | case I2C_SMBUS_BLOCK_DATA: | |
223 | TXFIFO_WR(smbus, addr | MTXFIFO_START); | |
224 | TXFIFO_WR(smbus, command); | |
225 | if (read_write) { | |
226 | TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); | |
227 | TXFIFO_WR(smbus, 1 | MTXFIFO_READ); | |
228 | rd = RXFIFO_RD(smbus); | |
229 | len = min_t(u8, (rd & MRXFIFO_DATA_M), | |
230 | I2C_SMBUS_BLOCK_MAX); | |
080dfbe1 | 231 | TXFIFO_WR(smbus, len | MTXFIFO_READ | |
beb58aa3 OJ |
232 | MTXFIFO_STOP); |
233 | } else { | |
234 | len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX); | |
235 | TXFIFO_WR(smbus, len); | |
236 | for (i = 1; i < len; i++) | |
237 | TXFIFO_WR(smbus, data->block[i]); | |
238 | TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP); | |
239 | } | |
240 | break; | |
241 | case I2C_SMBUS_PROC_CALL: | |
242 | read_write = I2C_SMBUS_READ; | |
243 | TXFIFO_WR(smbus, addr | MTXFIFO_START); | |
244 | TXFIFO_WR(smbus, command); | |
245 | TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M); | |
246 | TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M); | |
247 | TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); | |
248 | TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ); | |
249 | break; | |
250 | case I2C_SMBUS_BLOCK_PROC_CALL: | |
251 | len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1); | |
252 | read_write = I2C_SMBUS_READ; | |
253 | TXFIFO_WR(smbus, addr | MTXFIFO_START); | |
254 | TXFIFO_WR(smbus, command); | |
255 | TXFIFO_WR(smbus, len); | |
256 | for (i = 1; i <= len; i++) | |
257 | TXFIFO_WR(smbus, data->block[i]); | |
258 | TXFIFO_WR(smbus, addr | I2C_SMBUS_READ); | |
259 | TXFIFO_WR(smbus, MTXFIFO_READ | 1); | |
260 | rd = RXFIFO_RD(smbus); | |
261 | len = min_t(u8, (rd & MRXFIFO_DATA_M), | |
262 | I2C_SMBUS_BLOCK_MAX - len); | |
080dfbe1 | 263 | TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP); |
beb58aa3 OJ |
264 | break; |
265 | ||
266 | default: | |
267 | dev_warn(&adapter->dev, "Unsupported transaction %d\n", size); | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | err = pasemi_smb_waitready(smbus); | |
272 | if (err) | |
273 | goto reset_out; | |
274 | ||
275 | if (read_write == I2C_SMBUS_WRITE) | |
276 | return 0; | |
277 | ||
278 | switch (size) { | |
279 | case I2C_SMBUS_BYTE: | |
280 | case I2C_SMBUS_BYTE_DATA: | |
281 | rd = RXFIFO_RD(smbus); | |
282 | if (rd & MRXFIFO_EMPTY) { | |
283 | err = -ENODATA; | |
284 | goto reset_out; | |
285 | } | |
286 | data->byte = rd & MRXFIFO_DATA_M; | |
287 | break; | |
288 | case I2C_SMBUS_WORD_DATA: | |
289 | case I2C_SMBUS_PROC_CALL: | |
290 | rd = RXFIFO_RD(smbus); | |
291 | if (rd & MRXFIFO_EMPTY) { | |
292 | err = -ENODATA; | |
293 | goto reset_out; | |
294 | } | |
295 | data->word = rd & MRXFIFO_DATA_M; | |
296 | rd = RXFIFO_RD(smbus); | |
297 | if (rd & MRXFIFO_EMPTY) { | |
298 | err = -ENODATA; | |
299 | goto reset_out; | |
300 | } | |
301 | data->word |= (rd & MRXFIFO_DATA_M) << 8; | |
302 | break; | |
303 | case I2C_SMBUS_BLOCK_DATA: | |
304 | case I2C_SMBUS_BLOCK_PROC_CALL: | |
305 | data->block[0] = len; | |
306 | for (i = 1; i <= len; i ++) { | |
307 | rd = RXFIFO_RD(smbus); | |
308 | if (rd & MRXFIFO_EMPTY) { | |
309 | err = -ENODATA; | |
310 | goto reset_out; | |
311 | } | |
312 | data->block[i] = rd & MRXFIFO_DATA_M; | |
313 | } | |
314 | break; | |
315 | } | |
316 | ||
317 | return 0; | |
318 | ||
319 | reset_out: | |
320 | reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | | |
321 | (CLK_100K_DIV & CTL_CLK_M))); | |
322 | return err; | |
323 | } | |
324 | ||
325 | static u32 pasemi_smb_func(struct i2c_adapter *adapter) | |
326 | { | |
327 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
328 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
329 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
330 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C; | |
331 | } | |
332 | ||
333 | static const struct i2c_algorithm smbus_algorithm = { | |
334 | .master_xfer = pasemi_i2c_xfer, | |
335 | .smbus_xfer = pasemi_smb_xfer, | |
336 | .functionality = pasemi_smb_func, | |
337 | }; | |
338 | ||
0b255e92 | 339 | static int pasemi_smb_probe(struct pci_dev *dev, |
beb58aa3 OJ |
340 | const struct pci_device_id *id) |
341 | { | |
342 | struct pasemi_smbus *smbus; | |
343 | int error; | |
344 | ||
345 | if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO)) | |
346 | return -ENODEV; | |
347 | ||
348 | smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL); | |
349 | if (!smbus) | |
350 | return -ENOMEM; | |
351 | ||
352 | smbus->dev = dev; | |
353 | smbus->base = pci_resource_start(dev, 0); | |
354 | smbus->size = pci_resource_len(dev, 0); | |
355 | ||
356 | if (!request_region(smbus->base, smbus->size, | |
357 | pasemi_smb_driver.name)) { | |
358 | error = -EBUSY; | |
359 | goto out_kfree; | |
360 | } | |
361 | ||
362 | smbus->adapter.owner = THIS_MODULE; | |
2096b956 | 363 | snprintf(smbus->adapter.name, sizeof(smbus->adapter.name), |
beb58aa3 | 364 | "PA Semi SMBus adapter at 0x%lx", smbus->base); |
3401b2ff | 365 | smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
beb58aa3 OJ |
366 | smbus->adapter.algo = &smbus_algorithm; |
367 | smbus->adapter.algo_data = smbus; | |
ccf60d85 | 368 | smbus->adapter.nr = PCI_FUNC(dev->devfn); |
beb58aa3 | 369 | |
ff23f3ea | 370 | /* set up the sysfs linkage to our parent device */ |
beb58aa3 OJ |
371 | smbus->adapter.dev.parent = &dev->dev; |
372 | ||
373 | reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | | |
374 | (CLK_100K_DIV & CTL_CLK_M))); | |
375 | ||
ccf60d85 | 376 | error = i2c_add_numbered_adapter(&smbus->adapter); |
beb58aa3 OJ |
377 | if (error) |
378 | goto out_release_region; | |
379 | ||
380 | pci_set_drvdata(dev, smbus); | |
381 | ||
382 | return 0; | |
383 | ||
384 | out_release_region: | |
385 | release_region(smbus->base, smbus->size); | |
386 | out_kfree: | |
387 | kfree(smbus); | |
388 | return error; | |
389 | } | |
390 | ||
0b255e92 | 391 | static void pasemi_smb_remove(struct pci_dev *dev) |
beb58aa3 OJ |
392 | { |
393 | struct pasemi_smbus *smbus = pci_get_drvdata(dev); | |
394 | ||
395 | i2c_del_adapter(&smbus->adapter); | |
396 | release_region(smbus->base, smbus->size); | |
397 | kfree(smbus); | |
398 | } | |
399 | ||
392debf1 | 400 | static const struct pci_device_id pasemi_smb_ids[] = { |
beb58aa3 OJ |
401 | { PCI_DEVICE(0x1959, 0xa003) }, |
402 | { 0, } | |
403 | }; | |
404 | ||
405 | MODULE_DEVICE_TABLE(pci, pasemi_smb_ids); | |
406 | ||
407 | static struct pci_driver pasemi_smb_driver = { | |
408 | .name = "i2c-pasemi", | |
409 | .id_table = pasemi_smb_ids, | |
410 | .probe = pasemi_smb_probe, | |
0b255e92 | 411 | .remove = pasemi_smb_remove, |
beb58aa3 OJ |
412 | }; |
413 | ||
56f21788 | 414 | module_pci_driver(pasemi_smb_driver); |
beb58aa3 OJ |
415 | |
416 | MODULE_LICENSE("GPL"); | |
417 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
418 | MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver"); |