Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and |
3 | Philip Edelbrock <phil@netroedge.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* | |
21 | Supports: | |
22 | Intel PIIX4, 440MX | |
506a8b6c | 23 | Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 |
2a2f7404 | 24 | ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 |
032f708b | 25 | AMD Hudson-2, ML, CZ |
1da177e4 LT |
26 | SMSC Victory66 |
27 | ||
2a2f7404 AA |
28 | Note: we assume there can only be one device, with one or more |
29 | SMBus interfaces. | |
1da177e4 LT |
30 | */ |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/stddef.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/i2c.h> | |
c415b303 | 40 | #include <linux/slab.h> |
1da177e4 | 41 | #include <linux/dmi.h> |
54fb4a05 | 42 | #include <linux/acpi.h> |
21782180 | 43 | #include <linux/io.h> |
1da177e4 LT |
44 | |
45 | ||
1da177e4 LT |
46 | /* PIIX4 SMBus address offsets */ |
47 | #define SMBHSTSTS (0 + piix4_smba) | |
48 | #define SMBHSLVSTS (1 + piix4_smba) | |
49 | #define SMBHSTCNT (2 + piix4_smba) | |
50 | #define SMBHSTCMD (3 + piix4_smba) | |
51 | #define SMBHSTADD (4 + piix4_smba) | |
52 | #define SMBHSTDAT0 (5 + piix4_smba) | |
53 | #define SMBHSTDAT1 (6 + piix4_smba) | |
54 | #define SMBBLKDAT (7 + piix4_smba) | |
55 | #define SMBSLVCNT (8 + piix4_smba) | |
56 | #define SMBSHDWCMD (9 + piix4_smba) | |
57 | #define SMBSLVEVT (0xA + piix4_smba) | |
58 | #define SMBSLVDAT (0xC + piix4_smba) | |
59 | ||
60 | /* count for request_region */ | |
61 | #define SMBIOSIZE 8 | |
62 | ||
63 | /* PCI Address Constants */ | |
64 | #define SMBBA 0x090 | |
65 | #define SMBHSTCFG 0x0D2 | |
66 | #define SMBSLVC 0x0D3 | |
67 | #define SMBSHDW1 0x0D4 | |
68 | #define SMBSHDW2 0x0D5 | |
69 | #define SMBREV 0x0D6 | |
70 | ||
71 | /* Other settings */ | |
72 | #define MAX_TIMEOUT 500 | |
73 | #define ENABLE_INT9 0 | |
74 | ||
75 | /* PIIX4 constants */ | |
76 | #define PIIX4_QUICK 0x00 | |
77 | #define PIIX4_BYTE 0x04 | |
78 | #define PIIX4_BYTE_DATA 0x08 | |
79 | #define PIIX4_WORD_DATA 0x0C | |
80 | #define PIIX4_BLOCK_DATA 0x14 | |
81 | ||
82 | /* insmod parameters */ | |
83 | ||
84 | /* If force is set to anything different from 0, we forcibly enable the | |
85 | PIIX4. DANGEROUS! */ | |
60507095 | 86 | static int force; |
1da177e4 LT |
87 | module_param (force, int, 0); |
88 | MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); | |
89 | ||
90 | /* If force_addr is set to anything different from 0, we forcibly enable | |
91 | the PIIX4 at the given address. VERY DANGEROUS! */ | |
60507095 | 92 | static int force_addr; |
1da177e4 LT |
93 | module_param (force_addr, int, 0); |
94 | MODULE_PARM_DESC(force_addr, | |
95 | "Forcibly enable the PIIX4 at the given address. " | |
96 | "EXTREMELY DANGEROUS!"); | |
97 | ||
b1c1759c | 98 | static int srvrworks_csb5_delay; |
d6072f84 | 99 | static struct pci_driver piix4_driver; |
1da177e4 | 100 | |
0b255e92 | 101 | static const struct dmi_system_id piix4_dmi_blacklist[] = { |
c2fc54fc JD |
102 | { |
103 | .ident = "Sapphire AM2RD790", | |
104 | .matches = { | |
105 | DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), | |
106 | DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), | |
107 | }, | |
108 | }, | |
109 | { | |
110 | .ident = "DFI Lanparty UT 790FX", | |
111 | .matches = { | |
112 | DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), | |
113 | DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), | |
114 | }, | |
115 | }, | |
116 | { } | |
117 | }; | |
118 | ||
119 | /* The IBM entry is in a separate table because we only check it | |
120 | on Intel-based systems */ | |
0b255e92 | 121 | static const struct dmi_system_id piix4_dmi_ibm[] = { |
1da177e4 LT |
122 | { |
123 | .ident = "IBM", | |
124 | .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, | |
125 | }, | |
126 | { }, | |
127 | }; | |
128 | ||
14a8086d AA |
129 | struct i2c_piix4_adapdata { |
130 | unsigned short smba; | |
131 | }; | |
132 | ||
0b255e92 BP |
133 | static int piix4_setup(struct pci_dev *PIIX4_dev, |
134 | const struct pci_device_id *id) | |
1da177e4 LT |
135 | { |
136 | unsigned char temp; | |
14a8086d | 137 | unsigned short piix4_smba; |
1da177e4 | 138 | |
b1c1759c DM |
139 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && |
140 | (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) | |
141 | srvrworks_csb5_delay = 1; | |
142 | ||
c2fc54fc JD |
143 | /* On some motherboards, it was reported that accessing the SMBus |
144 | caused severe hardware problems */ | |
145 | if (dmi_check_system(piix4_dmi_blacklist)) { | |
146 | dev_err(&PIIX4_dev->dev, | |
147 | "Accessing the SMBus on this system is unsafe!\n"); | |
148 | return -EPERM; | |
149 | } | |
150 | ||
1da177e4 | 151 | /* Don't access SMBus on IBM systems which get corrupted eeproms */ |
c2fc54fc | 152 | if (dmi_check_system(piix4_dmi_ibm) && |
1da177e4 | 153 | PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { |
f9ba6c04 | 154 | dev_err(&PIIX4_dev->dev, "IBM system detected; this module " |
1da177e4 LT |
155 | "may corrupt your serial eeprom! Refusing to load " |
156 | "module!\n"); | |
157 | return -EPERM; | |
158 | } | |
159 | ||
160 | /* Determine the address of the SMBus areas */ | |
161 | if (force_addr) { | |
162 | piix4_smba = force_addr & 0xfff0; | |
163 | force = 0; | |
164 | } else { | |
165 | pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); | |
166 | piix4_smba &= 0xfff0; | |
167 | if(piix4_smba == 0) { | |
fa63cd56 | 168 | dev_err(&PIIX4_dev->dev, "SMBus base address " |
1da177e4 LT |
169 | "uninitialized - upgrade BIOS or use " |
170 | "force_addr=0xaddr\n"); | |
171 | return -ENODEV; | |
172 | } | |
173 | } | |
174 | ||
54fb4a05 | 175 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 176 | return -ENODEV; |
54fb4a05 | 177 | |
d6072f84 | 178 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { |
fa63cd56 | 179 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", |
1da177e4 | 180 | piix4_smba); |
fa63cd56 | 181 | return -EBUSY; |
1da177e4 LT |
182 | } |
183 | ||
184 | pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); | |
185 | ||
1da177e4 LT |
186 | /* If force_addr is set, we program the new address here. Just to make |
187 | sure, we disable the PIIX4 first. */ | |
188 | if (force_addr) { | |
189 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); | |
190 | pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); | |
191 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); | |
192 | dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " | |
193 | "new address %04x!\n", piix4_smba); | |
194 | } else if ((temp & 1) == 0) { | |
195 | if (force) { | |
196 | /* This should never need to be done, but has been | |
197 | * noted that many Dell machines have the SMBus | |
198 | * interface on the PIIX4 disabled!? NOTE: This assumes | |
199 | * I/O space and other allocations WERE done by the | |
200 | * Bios! Don't complain if your hardware does weird | |
201 | * things after enabling this. :') Check for Bios | |
202 | * updates before resorting to this. | |
203 | */ | |
204 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, | |
205 | temp | 1); | |
8117e41e JP |
206 | dev_notice(&PIIX4_dev->dev, |
207 | "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); | |
1da177e4 LT |
208 | } else { |
209 | dev_err(&PIIX4_dev->dev, | |
66f8a8ff | 210 | "SMBus Host Controller not enabled!\n"); |
1da177e4 | 211 | release_region(piix4_smba, SMBIOSIZE); |
1da177e4 LT |
212 | return -ENODEV; |
213 | } | |
214 | } | |
215 | ||
54aaa1ca | 216 | if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) |
66f8a8ff | 217 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
1da177e4 | 218 | else if ((temp & 0x0E) == 0) |
66f8a8ff | 219 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
1da177e4 LT |
220 | else |
221 | dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " | |
222 | "(or code out of date)!\n"); | |
223 | ||
224 | pci_read_config_byte(PIIX4_dev, SMBREV, &temp); | |
fa63cd56 JD |
225 | dev_info(&PIIX4_dev->dev, |
226 | "SMBus Host Controller at 0x%x, revision %d\n", | |
227 | piix4_smba, temp); | |
1da177e4 | 228 | |
14a8086d | 229 | return piix4_smba; |
1da177e4 LT |
230 | } |
231 | ||
0b255e92 | 232 | static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, |
a94dd00f | 233 | const struct pci_device_id *id, u8 aux) |
87e1960e | 234 | { |
14a8086d | 235 | unsigned short piix4_smba; |
87e1960e | 236 | unsigned short smba_idx = 0xcd6; |
032f708b SH |
237 | u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status; |
238 | u8 i2ccfg, i2ccfg_offset = 0x10; | |
87e1960e | 239 | |
3806e94b | 240 | /* SB800 and later SMBus does not support forcing address */ |
87e1960e | 241 | if (force || force_addr) { |
3806e94b | 242 | dev_err(&PIIX4_dev->dev, "SMBus does not support " |
87e1960e SH |
243 | "forcing address!\n"); |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | /* Determine the address of the SMBus areas */ | |
032f708b SH |
248 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && |
249 | PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && | |
250 | PIIX4_dev->revision >= 0x41) || | |
251 | (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && | |
252 | PIIX4_dev->device == 0x790b && | |
253 | PIIX4_dev->revision >= 0x49)) | |
254 | smb_en = 0x00; | |
255 | else | |
256 | smb_en = (aux) ? 0x28 : 0x2c; | |
a94dd00f | 257 | |
87e1960e SH |
258 | if (!request_region(smba_idx, 2, "smba_idx")) { |
259 | dev_err(&PIIX4_dev->dev, "SMBus base address index region " | |
260 | "0x%x already in use!\n", smba_idx); | |
261 | return -EBUSY; | |
262 | } | |
263 | outb_p(smb_en, smba_idx); | |
264 | smba_en_lo = inb_p(smba_idx + 1); | |
265 | outb_p(smb_en + 1, smba_idx); | |
266 | smba_en_hi = inb_p(smba_idx + 1); | |
267 | release_region(smba_idx, 2); | |
268 | ||
032f708b SH |
269 | if (!smb_en) { |
270 | smb_en_status = smba_en_lo & 0x10; | |
271 | piix4_smba = smba_en_hi << 8; | |
272 | if (aux) | |
273 | piix4_smba |= 0x20; | |
274 | } else { | |
275 | smb_en_status = smba_en_lo & 0x01; | |
276 | piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
277 | } | |
278 | ||
279 | if (!smb_en_status) { | |
87e1960e | 280 | dev_err(&PIIX4_dev->dev, |
66f8a8ff | 281 | "SMBus Host Controller not enabled!\n"); |
87e1960e SH |
282 | return -ENODEV; |
283 | } | |
284 | ||
87e1960e | 285 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 286 | return -ENODEV; |
87e1960e SH |
287 | |
288 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
289 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", | |
290 | piix4_smba); | |
291 | return -EBUSY; | |
292 | } | |
293 | ||
a94dd00f RM |
294 | /* Aux SMBus does not support IRQ information */ |
295 | if (aux) { | |
296 | dev_info(&PIIX4_dev->dev, | |
85fd0fe6 SH |
297 | "Auxiliary SMBus Host Controller at 0x%x\n", |
298 | piix4_smba); | |
a94dd00f RM |
299 | return piix4_smba; |
300 | } | |
301 | ||
87e1960e SH |
302 | /* Request the SMBus I2C bus config region */ |
303 | if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { | |
304 | dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " | |
305 | "0x%x already in use!\n", piix4_smba + i2ccfg_offset); | |
306 | release_region(piix4_smba, SMBIOSIZE); | |
87e1960e SH |
307 | return -EBUSY; |
308 | } | |
309 | i2ccfg = inb_p(piix4_smba + i2ccfg_offset); | |
310 | release_region(piix4_smba + i2ccfg_offset, 1); | |
311 | ||
312 | if (i2ccfg & 1) | |
66f8a8ff | 313 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
87e1960e | 314 | else |
66f8a8ff | 315 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
87e1960e SH |
316 | |
317 | dev_info(&PIIX4_dev->dev, | |
318 | "SMBus Host Controller at 0x%x, revision %d\n", | |
319 | piix4_smba, i2ccfg >> 4); | |
320 | ||
14a8086d | 321 | return piix4_smba; |
87e1960e SH |
322 | } |
323 | ||
0b255e92 BP |
324 | static int piix4_setup_aux(struct pci_dev *PIIX4_dev, |
325 | const struct pci_device_id *id, | |
326 | unsigned short base_reg_addr) | |
2a2f7404 AA |
327 | { |
328 | /* Set up auxiliary SMBus controllers found on some | |
329 | * AMD chipsets e.g. SP5100 (SB700 derivative) */ | |
330 | ||
331 | unsigned short piix4_smba; | |
332 | ||
333 | /* Read address of auxiliary SMBus controller */ | |
334 | pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); | |
335 | if ((piix4_smba & 1) == 0) { | |
336 | dev_dbg(&PIIX4_dev->dev, | |
337 | "Auxiliary SMBus controller not enabled\n"); | |
338 | return -ENODEV; | |
339 | } | |
340 | ||
341 | piix4_smba &= 0xfff0; | |
342 | if (piix4_smba == 0) { | |
343 | dev_dbg(&PIIX4_dev->dev, | |
344 | "Auxiliary SMBus base address uninitialized\n"); | |
345 | return -ENODEV; | |
346 | } | |
347 | ||
348 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) | |
349 | return -ENODEV; | |
350 | ||
351 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
352 | dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " | |
353 | "already in use!\n", piix4_smba); | |
354 | return -EBUSY; | |
355 | } | |
356 | ||
357 | dev_info(&PIIX4_dev->dev, | |
358 | "Auxiliary SMBus Host Controller at 0x%x\n", | |
359 | piix4_smba); | |
360 | ||
361 | return piix4_smba; | |
362 | } | |
363 | ||
e154bf6f | 364 | static int piix4_transaction(struct i2c_adapter *piix4_adapter) |
1da177e4 | 365 | { |
e154bf6f AA |
366 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); |
367 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 LT |
368 | int temp; |
369 | int result = 0; | |
370 | int timeout = 0; | |
371 | ||
e154bf6f | 372 | dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
373 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
374 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
375 | inb_p(SMBHSTDAT1)); | |
376 | ||
377 | /* Make sure the SMBus host is ready to start transmitting */ | |
378 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 379 | dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " |
541e6a02 | 380 | "Resetting...\n", temp); |
1da177e4 LT |
381 | outb_p(temp, SMBHSTSTS); |
382 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 383 | dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); |
97140342 | 384 | return -EBUSY; |
1da177e4 | 385 | } else { |
e154bf6f | 386 | dev_dbg(&piix4_adapter->dev, "Successful!\n"); |
1da177e4 LT |
387 | } |
388 | } | |
389 | ||
390 | /* start the transaction by setting bit 6 */ | |
391 | outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); | |
392 | ||
393 | /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ | |
b1c1759c DM |
394 | if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ |
395 | msleep(2); | |
396 | else | |
397 | msleep(1); | |
398 | ||
b6a31950 | 399 | while ((++timeout < MAX_TIMEOUT) && |
b1c1759c | 400 | ((temp = inb_p(SMBHSTSTS)) & 0x01)) |
1da177e4 | 401 | msleep(1); |
1da177e4 LT |
402 | |
403 | /* If the SMBus is still busy, we give up */ | |
b6a31950 | 404 | if (timeout == MAX_TIMEOUT) { |
e154bf6f | 405 | dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); |
97140342 | 406 | result = -ETIMEDOUT; |
1da177e4 LT |
407 | } |
408 | ||
409 | if (temp & 0x10) { | |
97140342 | 410 | result = -EIO; |
e154bf6f | 411 | dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); |
1da177e4 LT |
412 | } |
413 | ||
414 | if (temp & 0x08) { | |
97140342 | 415 | result = -EIO; |
e154bf6f | 416 | dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " |
1da177e4 LT |
417 | "locked until next hard reset. (sorry!)\n"); |
418 | /* Clock stops and slave is stuck in mid-transmission */ | |
419 | } | |
420 | ||
421 | if (temp & 0x04) { | |
97140342 | 422 | result = -ENXIO; |
e154bf6f | 423 | dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); |
1da177e4 LT |
424 | } |
425 | ||
426 | if (inb_p(SMBHSTSTS) != 0x00) | |
427 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
428 | ||
429 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 430 | dev_err(&piix4_adapter->dev, "Failed reset at end of " |
1da177e4 LT |
431 | "transaction (%02x)\n", temp); |
432 | } | |
e154bf6f | 433 | dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
434 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
435 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
436 | inb_p(SMBHSTDAT1)); | |
437 | return result; | |
438 | } | |
439 | ||
97140342 | 440 | /* Return negative errno on error. */ |
1da177e4 LT |
441 | static s32 piix4_access(struct i2c_adapter * adap, u16 addr, |
442 | unsigned short flags, char read_write, | |
443 | u8 command, int size, union i2c_smbus_data * data) | |
444 | { | |
14a8086d AA |
445 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
446 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 | 447 | int i, len; |
97140342 | 448 | int status; |
1da177e4 LT |
449 | |
450 | switch (size) { | |
1da177e4 | 451 | case I2C_SMBUS_QUICK: |
fa63cd56 | 452 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
453 | SMBHSTADD); |
454 | size = PIIX4_QUICK; | |
455 | break; | |
456 | case I2C_SMBUS_BYTE: | |
fa63cd56 | 457 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
458 | SMBHSTADD); |
459 | if (read_write == I2C_SMBUS_WRITE) | |
460 | outb_p(command, SMBHSTCMD); | |
461 | size = PIIX4_BYTE; | |
462 | break; | |
463 | case I2C_SMBUS_BYTE_DATA: | |
fa63cd56 | 464 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
465 | SMBHSTADD); |
466 | outb_p(command, SMBHSTCMD); | |
467 | if (read_write == I2C_SMBUS_WRITE) | |
468 | outb_p(data->byte, SMBHSTDAT0); | |
469 | size = PIIX4_BYTE_DATA; | |
470 | break; | |
471 | case I2C_SMBUS_WORD_DATA: | |
fa63cd56 | 472 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
473 | SMBHSTADD); |
474 | outb_p(command, SMBHSTCMD); | |
475 | if (read_write == I2C_SMBUS_WRITE) { | |
476 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
477 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
478 | } | |
479 | size = PIIX4_WORD_DATA; | |
480 | break; | |
481 | case I2C_SMBUS_BLOCK_DATA: | |
fa63cd56 | 482 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
483 | SMBHSTADD); |
484 | outb_p(command, SMBHSTCMD); | |
485 | if (read_write == I2C_SMBUS_WRITE) { | |
486 | len = data->block[0]; | |
fa63cd56 JD |
487 | if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) |
488 | return -EINVAL; | |
1da177e4 LT |
489 | outb_p(len, SMBHSTDAT0); |
490 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ | |
491 | for (i = 1; i <= len; i++) | |
492 | outb_p(data->block[i], SMBBLKDAT); | |
493 | } | |
494 | size = PIIX4_BLOCK_DATA; | |
495 | break; | |
ac7fc4fb JD |
496 | default: |
497 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); | |
498 | return -EOPNOTSUPP; | |
1da177e4 LT |
499 | } |
500 | ||
501 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | |
502 | ||
e154bf6f | 503 | status = piix4_transaction(adap); |
97140342 DB |
504 | if (status) |
505 | return status; | |
1da177e4 LT |
506 | |
507 | if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) | |
508 | return 0; | |
509 | ||
510 | ||
511 | switch (size) { | |
3578a075 | 512 | case PIIX4_BYTE: |
1da177e4 LT |
513 | case PIIX4_BYTE_DATA: |
514 | data->byte = inb_p(SMBHSTDAT0); | |
515 | break; | |
516 | case PIIX4_WORD_DATA: | |
517 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
518 | break; | |
519 | case PIIX4_BLOCK_DATA: | |
520 | data->block[0] = inb_p(SMBHSTDAT0); | |
fa63cd56 JD |
521 | if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
522 | return -EPROTO; | |
1da177e4 LT |
523 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
524 | for (i = 1; i <= data->block[0]; i++) | |
525 | data->block[i] = inb_p(SMBBLKDAT); | |
526 | break; | |
527 | } | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static u32 piix4_func(struct i2c_adapter *adapter) | |
532 | { | |
533 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
534 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
535 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
536 | } | |
537 | ||
8f9082c5 | 538 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
539 | .smbus_xfer = piix4_access, |
540 | .functionality = piix4_func, | |
541 | }; | |
542 | ||
392debf1 | 543 | static const struct pci_device_id piix4_ids[] = { |
9b7389c0 JD |
544 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, |
545 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, | |
546 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, | |
547 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, | |
548 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, | |
549 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, | |
550 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, | |
3806e94b | 551 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, |
b996ac90 | 552 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x790b) }, |
9b7389c0 JD |
553 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
554 | PCI_DEVICE_ID_SERVERWORKS_OSB4) }, | |
555 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
556 | PCI_DEVICE_ID_SERVERWORKS_CSB5) }, | |
557 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
558 | PCI_DEVICE_ID_SERVERWORKS_CSB6) }, | |
559 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
560 | PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, | |
506a8b6c FL |
561 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
562 | PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, | |
1da177e4 LT |
563 | { 0, } |
564 | }; | |
565 | ||
566 | MODULE_DEVICE_TABLE (pci, piix4_ids); | |
567 | ||
e154bf6f | 568 | static struct i2c_adapter *piix4_main_adapter; |
2a2f7404 | 569 | static struct i2c_adapter *piix4_aux_adapter; |
e154bf6f | 570 | |
0b255e92 BP |
571 | static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, |
572 | struct i2c_adapter **padap) | |
e154bf6f AA |
573 | { |
574 | struct i2c_adapter *adap; | |
575 | struct i2c_piix4_adapdata *adapdata; | |
576 | int retval; | |
577 | ||
578 | adap = kzalloc(sizeof(*adap), GFP_KERNEL); | |
579 | if (adap == NULL) { | |
580 | release_region(smba, SMBIOSIZE); | |
581 | return -ENOMEM; | |
582 | } | |
583 | ||
584 | adap->owner = THIS_MODULE; | |
585 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
586 | adap->algo = &smbus_algorithm; | |
587 | ||
588 | adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); | |
589 | if (adapdata == NULL) { | |
590 | kfree(adap); | |
591 | release_region(smba, SMBIOSIZE); | |
592 | return -ENOMEM; | |
593 | } | |
594 | ||
595 | adapdata->smba = smba; | |
596 | ||
597 | /* set up the sysfs linkage to our parent device */ | |
598 | adap->dev.parent = &dev->dev; | |
599 | ||
600 | snprintf(adap->name, sizeof(adap->name), | |
601 | "SMBus PIIX4 adapter at %04x", smba); | |
602 | ||
603 | i2c_set_adapdata(adap, adapdata); | |
604 | ||
605 | retval = i2c_add_adapter(adap); | |
606 | if (retval) { | |
607 | dev_err(&dev->dev, "Couldn't register adapter!\n"); | |
608 | kfree(adapdata); | |
609 | kfree(adap); | |
610 | release_region(smba, SMBIOSIZE); | |
611 | return retval; | |
612 | } | |
613 | ||
614 | *padap = adap; | |
615 | return 0; | |
616 | } | |
617 | ||
0b255e92 | 618 | static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 LT |
619 | { |
620 | int retval; | |
621 | ||
76b3e28f CC |
622 | if ((dev->vendor == PCI_VENDOR_ID_ATI && |
623 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && | |
624 | dev->revision >= 0x40) || | |
625 | dev->vendor == PCI_VENDOR_ID_AMD) | |
87e1960e | 626 | /* base address location etc changed in SB800 */ |
a94dd00f | 627 | retval = piix4_setup_sb800(dev, id, 0); |
87e1960e SH |
628 | else |
629 | retval = piix4_setup(dev, id); | |
630 | ||
2a2f7404 | 631 | /* If no main SMBus found, give up */ |
14a8086d | 632 | if (retval < 0) |
1da177e4 LT |
633 | return retval; |
634 | ||
2a2f7404 AA |
635 | /* Try to register main SMBus adapter, give up if we can't */ |
636 | retval = piix4_add_adapter(dev, retval, &piix4_main_adapter); | |
637 | if (retval < 0) | |
638 | return retval; | |
639 | ||
640 | /* Check for auxiliary SMBus on some AMD chipsets */ | |
a94dd00f RM |
641 | retval = -ENODEV; |
642 | ||
2a2f7404 | 643 | if (dev->vendor == PCI_VENDOR_ID_ATI && |
a94dd00f RM |
644 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { |
645 | if (dev->revision < 0x40) { | |
646 | retval = piix4_setup_aux(dev, id, 0x58); | |
647 | } else { | |
648 | /* SB800 added aux bus too */ | |
649 | retval = piix4_setup_sb800(dev, id, 1); | |
2a2f7404 AA |
650 | } |
651 | } | |
652 | ||
a94dd00f RM |
653 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
654 | dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { | |
655 | retval = piix4_setup_sb800(dev, id, 1); | |
656 | } | |
657 | ||
658 | if (retval > 0) { | |
659 | /* Try to add the aux adapter if it exists, | |
660 | * piix4_add_adapter will clean up if this fails */ | |
661 | piix4_add_adapter(dev, retval, &piix4_aux_adapter); | |
662 | } | |
663 | ||
2a2f7404 | 664 | return 0; |
1da177e4 LT |
665 | } |
666 | ||
0b255e92 | 667 | static void piix4_adap_remove(struct i2c_adapter *adap) |
1da177e4 | 668 | { |
14a8086d AA |
669 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
670 | ||
671 | if (adapdata->smba) { | |
672 | i2c_del_adapter(adap); | |
673 | release_region(adapdata->smba, SMBIOSIZE); | |
e154bf6f AA |
674 | kfree(adapdata); |
675 | kfree(adap); | |
1da177e4 LT |
676 | } |
677 | } | |
678 | ||
0b255e92 | 679 | static void piix4_remove(struct pci_dev *dev) |
14a8086d | 680 | { |
e154bf6f AA |
681 | if (piix4_main_adapter) { |
682 | piix4_adap_remove(piix4_main_adapter); | |
683 | piix4_main_adapter = NULL; | |
684 | } | |
2a2f7404 AA |
685 | |
686 | if (piix4_aux_adapter) { | |
687 | piix4_adap_remove(piix4_aux_adapter); | |
688 | piix4_aux_adapter = NULL; | |
689 | } | |
14a8086d AA |
690 | } |
691 | ||
1da177e4 LT |
692 | static struct pci_driver piix4_driver = { |
693 | .name = "piix4_smbus", | |
694 | .id_table = piix4_ids, | |
695 | .probe = piix4_probe, | |
0b255e92 | 696 | .remove = piix4_remove, |
1da177e4 LT |
697 | }; |
698 | ||
56f21788 | 699 | module_pci_driver(piix4_driver); |
1da177e4 LT |
700 | |
701 | MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " | |
702 | "Philip Edelbrock <phil@netroedge.com>"); | |
703 | MODULE_DESCRIPTION("PIIX4 SMBus driver"); | |
704 | MODULE_LICENSE("GPL"); |