Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and |
3 | Philip Edelbrock <phil@netroedge.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* | |
21 | Supports: | |
22 | Intel PIIX4, 440MX | |
506a8b6c | 23 | Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 |
2a2f7404 | 24 | ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 |
b996ac90 | 25 | AMD Hudson-2, CZ |
1da177e4 LT |
26 | SMSC Victory66 |
27 | ||
2a2f7404 AA |
28 | Note: we assume there can only be one device, with one or more |
29 | SMBus interfaces. | |
1da177e4 LT |
30 | */ |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/stddef.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/i2c.h> | |
c415b303 | 40 | #include <linux/slab.h> |
1da177e4 | 41 | #include <linux/init.h> |
1da177e4 | 42 | #include <linux/dmi.h> |
54fb4a05 | 43 | #include <linux/acpi.h> |
21782180 | 44 | #include <linux/io.h> |
1da177e4 LT |
45 | |
46 | ||
1da177e4 LT |
47 | /* PIIX4 SMBus address offsets */ |
48 | #define SMBHSTSTS (0 + piix4_smba) | |
49 | #define SMBHSLVSTS (1 + piix4_smba) | |
50 | #define SMBHSTCNT (2 + piix4_smba) | |
51 | #define SMBHSTCMD (3 + piix4_smba) | |
52 | #define SMBHSTADD (4 + piix4_smba) | |
53 | #define SMBHSTDAT0 (5 + piix4_smba) | |
54 | #define SMBHSTDAT1 (6 + piix4_smba) | |
55 | #define SMBBLKDAT (7 + piix4_smba) | |
56 | #define SMBSLVCNT (8 + piix4_smba) | |
57 | #define SMBSHDWCMD (9 + piix4_smba) | |
58 | #define SMBSLVEVT (0xA + piix4_smba) | |
59 | #define SMBSLVDAT (0xC + piix4_smba) | |
60 | ||
61 | /* count for request_region */ | |
62 | #define SMBIOSIZE 8 | |
63 | ||
64 | /* PCI Address Constants */ | |
65 | #define SMBBA 0x090 | |
66 | #define SMBHSTCFG 0x0D2 | |
67 | #define SMBSLVC 0x0D3 | |
68 | #define SMBSHDW1 0x0D4 | |
69 | #define SMBSHDW2 0x0D5 | |
70 | #define SMBREV 0x0D6 | |
71 | ||
72 | /* Other settings */ | |
73 | #define MAX_TIMEOUT 500 | |
74 | #define ENABLE_INT9 0 | |
75 | ||
76 | /* PIIX4 constants */ | |
77 | #define PIIX4_QUICK 0x00 | |
78 | #define PIIX4_BYTE 0x04 | |
79 | #define PIIX4_BYTE_DATA 0x08 | |
80 | #define PIIX4_WORD_DATA 0x0C | |
81 | #define PIIX4_BLOCK_DATA 0x14 | |
82 | ||
83 | /* insmod parameters */ | |
84 | ||
85 | /* If force is set to anything different from 0, we forcibly enable the | |
86 | PIIX4. DANGEROUS! */ | |
60507095 | 87 | static int force; |
1da177e4 LT |
88 | module_param (force, int, 0); |
89 | MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); | |
90 | ||
91 | /* If force_addr is set to anything different from 0, we forcibly enable | |
92 | the PIIX4 at the given address. VERY DANGEROUS! */ | |
60507095 | 93 | static int force_addr; |
1da177e4 LT |
94 | module_param (force_addr, int, 0); |
95 | MODULE_PARM_DESC(force_addr, | |
96 | "Forcibly enable the PIIX4 at the given address. " | |
97 | "EXTREMELY DANGEROUS!"); | |
98 | ||
b1c1759c | 99 | static int srvrworks_csb5_delay; |
d6072f84 | 100 | static struct pci_driver piix4_driver; |
1da177e4 | 101 | |
0b255e92 | 102 | static const struct dmi_system_id piix4_dmi_blacklist[] = { |
c2fc54fc JD |
103 | { |
104 | .ident = "Sapphire AM2RD790", | |
105 | .matches = { | |
106 | DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), | |
107 | DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), | |
108 | }, | |
109 | }, | |
110 | { | |
111 | .ident = "DFI Lanparty UT 790FX", | |
112 | .matches = { | |
113 | DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), | |
114 | DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), | |
115 | }, | |
116 | }, | |
117 | { } | |
118 | }; | |
119 | ||
120 | /* The IBM entry is in a separate table because we only check it | |
121 | on Intel-based systems */ | |
0b255e92 | 122 | static const struct dmi_system_id piix4_dmi_ibm[] = { |
1da177e4 LT |
123 | { |
124 | .ident = "IBM", | |
125 | .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, | |
126 | }, | |
127 | { }, | |
128 | }; | |
129 | ||
14a8086d AA |
130 | struct i2c_piix4_adapdata { |
131 | unsigned short smba; | |
132 | }; | |
133 | ||
0b255e92 BP |
134 | static int piix4_setup(struct pci_dev *PIIX4_dev, |
135 | const struct pci_device_id *id) | |
1da177e4 LT |
136 | { |
137 | unsigned char temp; | |
14a8086d | 138 | unsigned short piix4_smba; |
1da177e4 | 139 | |
b1c1759c DM |
140 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && |
141 | (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) | |
142 | srvrworks_csb5_delay = 1; | |
143 | ||
c2fc54fc JD |
144 | /* On some motherboards, it was reported that accessing the SMBus |
145 | caused severe hardware problems */ | |
146 | if (dmi_check_system(piix4_dmi_blacklist)) { | |
147 | dev_err(&PIIX4_dev->dev, | |
148 | "Accessing the SMBus on this system is unsafe!\n"); | |
149 | return -EPERM; | |
150 | } | |
151 | ||
1da177e4 | 152 | /* Don't access SMBus on IBM systems which get corrupted eeproms */ |
c2fc54fc | 153 | if (dmi_check_system(piix4_dmi_ibm) && |
1da177e4 | 154 | PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { |
f9ba6c04 | 155 | dev_err(&PIIX4_dev->dev, "IBM system detected; this module " |
1da177e4 LT |
156 | "may corrupt your serial eeprom! Refusing to load " |
157 | "module!\n"); | |
158 | return -EPERM; | |
159 | } | |
160 | ||
161 | /* Determine the address of the SMBus areas */ | |
162 | if (force_addr) { | |
163 | piix4_smba = force_addr & 0xfff0; | |
164 | force = 0; | |
165 | } else { | |
166 | pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); | |
167 | piix4_smba &= 0xfff0; | |
168 | if(piix4_smba == 0) { | |
fa63cd56 | 169 | dev_err(&PIIX4_dev->dev, "SMBus base address " |
1da177e4 LT |
170 | "uninitialized - upgrade BIOS or use " |
171 | "force_addr=0xaddr\n"); | |
172 | return -ENODEV; | |
173 | } | |
174 | } | |
175 | ||
54fb4a05 | 176 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 177 | return -ENODEV; |
54fb4a05 | 178 | |
d6072f84 | 179 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { |
fa63cd56 | 180 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", |
1da177e4 | 181 | piix4_smba); |
fa63cd56 | 182 | return -EBUSY; |
1da177e4 LT |
183 | } |
184 | ||
185 | pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); | |
186 | ||
1da177e4 LT |
187 | /* If force_addr is set, we program the new address here. Just to make |
188 | sure, we disable the PIIX4 first. */ | |
189 | if (force_addr) { | |
190 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); | |
191 | pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); | |
192 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); | |
193 | dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " | |
194 | "new address %04x!\n", piix4_smba); | |
195 | } else if ((temp & 1) == 0) { | |
196 | if (force) { | |
197 | /* This should never need to be done, but has been | |
198 | * noted that many Dell machines have the SMBus | |
199 | * interface on the PIIX4 disabled!? NOTE: This assumes | |
200 | * I/O space and other allocations WERE done by the | |
201 | * Bios! Don't complain if your hardware does weird | |
202 | * things after enabling this. :') Check for Bios | |
203 | * updates before resorting to this. | |
204 | */ | |
205 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, | |
206 | temp | 1); | |
8117e41e JP |
207 | dev_notice(&PIIX4_dev->dev, |
208 | "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); | |
1da177e4 LT |
209 | } else { |
210 | dev_err(&PIIX4_dev->dev, | |
211 | "Host SMBus controller not enabled!\n"); | |
212 | release_region(piix4_smba, SMBIOSIZE); | |
1da177e4 LT |
213 | return -ENODEV; |
214 | } | |
215 | } | |
216 | ||
54aaa1ca | 217 | if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) |
1da177e4 LT |
218 | dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n"); |
219 | else if ((temp & 0x0E) == 0) | |
220 | dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n"); | |
221 | else | |
222 | dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " | |
223 | "(or code out of date)!\n"); | |
224 | ||
225 | pci_read_config_byte(PIIX4_dev, SMBREV, &temp); | |
fa63cd56 JD |
226 | dev_info(&PIIX4_dev->dev, |
227 | "SMBus Host Controller at 0x%x, revision %d\n", | |
228 | piix4_smba, temp); | |
1da177e4 | 229 | |
14a8086d | 230 | return piix4_smba; |
1da177e4 LT |
231 | } |
232 | ||
0b255e92 | 233 | static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, |
a94dd00f | 234 | const struct pci_device_id *id, u8 aux) |
87e1960e | 235 | { |
14a8086d | 236 | unsigned short piix4_smba; |
87e1960e | 237 | unsigned short smba_idx = 0xcd6; |
a94dd00f | 238 | u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en; |
87e1960e | 239 | |
3806e94b | 240 | /* SB800 and later SMBus does not support forcing address */ |
87e1960e | 241 | if (force || force_addr) { |
3806e94b | 242 | dev_err(&PIIX4_dev->dev, "SMBus does not support " |
87e1960e SH |
243 | "forcing address!\n"); |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | /* Determine the address of the SMBus areas */ | |
a94dd00f RM |
248 | smb_en = (aux) ? 0x28 : 0x2c; |
249 | ||
87e1960e SH |
250 | if (!request_region(smba_idx, 2, "smba_idx")) { |
251 | dev_err(&PIIX4_dev->dev, "SMBus base address index region " | |
252 | "0x%x already in use!\n", smba_idx); | |
253 | return -EBUSY; | |
254 | } | |
255 | outb_p(smb_en, smba_idx); | |
256 | smba_en_lo = inb_p(smba_idx + 1); | |
257 | outb_p(smb_en + 1, smba_idx); | |
258 | smba_en_hi = inb_p(smba_idx + 1); | |
259 | release_region(smba_idx, 2); | |
260 | ||
261 | if ((smba_en_lo & 1) == 0) { | |
262 | dev_err(&PIIX4_dev->dev, | |
263 | "Host SMBus controller not enabled!\n"); | |
264 | return -ENODEV; | |
265 | } | |
266 | ||
267 | piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
268 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) | |
18669eab | 269 | return -ENODEV; |
87e1960e SH |
270 | |
271 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
272 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", | |
273 | piix4_smba); | |
274 | return -EBUSY; | |
275 | } | |
276 | ||
a94dd00f RM |
277 | /* Aux SMBus does not support IRQ information */ |
278 | if (aux) { | |
279 | dev_info(&PIIX4_dev->dev, | |
280 | "SMBus Host Controller at 0x%x\n", piix4_smba); | |
281 | return piix4_smba; | |
282 | } | |
283 | ||
87e1960e SH |
284 | /* Request the SMBus I2C bus config region */ |
285 | if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { | |
286 | dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " | |
287 | "0x%x already in use!\n", piix4_smba + i2ccfg_offset); | |
288 | release_region(piix4_smba, SMBIOSIZE); | |
87e1960e SH |
289 | return -EBUSY; |
290 | } | |
291 | i2ccfg = inb_p(piix4_smba + i2ccfg_offset); | |
292 | release_region(piix4_smba + i2ccfg_offset, 1); | |
293 | ||
294 | if (i2ccfg & 1) | |
295 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n"); | |
296 | else | |
297 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n"); | |
298 | ||
299 | dev_info(&PIIX4_dev->dev, | |
300 | "SMBus Host Controller at 0x%x, revision %d\n", | |
301 | piix4_smba, i2ccfg >> 4); | |
302 | ||
14a8086d | 303 | return piix4_smba; |
87e1960e SH |
304 | } |
305 | ||
0b255e92 BP |
306 | static int piix4_setup_aux(struct pci_dev *PIIX4_dev, |
307 | const struct pci_device_id *id, | |
308 | unsigned short base_reg_addr) | |
2a2f7404 AA |
309 | { |
310 | /* Set up auxiliary SMBus controllers found on some | |
311 | * AMD chipsets e.g. SP5100 (SB700 derivative) */ | |
312 | ||
313 | unsigned short piix4_smba; | |
314 | ||
315 | /* Read address of auxiliary SMBus controller */ | |
316 | pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); | |
317 | if ((piix4_smba & 1) == 0) { | |
318 | dev_dbg(&PIIX4_dev->dev, | |
319 | "Auxiliary SMBus controller not enabled\n"); | |
320 | return -ENODEV; | |
321 | } | |
322 | ||
323 | piix4_smba &= 0xfff0; | |
324 | if (piix4_smba == 0) { | |
325 | dev_dbg(&PIIX4_dev->dev, | |
326 | "Auxiliary SMBus base address uninitialized\n"); | |
327 | return -ENODEV; | |
328 | } | |
329 | ||
330 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) | |
331 | return -ENODEV; | |
332 | ||
333 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
334 | dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " | |
335 | "already in use!\n", piix4_smba); | |
336 | return -EBUSY; | |
337 | } | |
338 | ||
339 | dev_info(&PIIX4_dev->dev, | |
340 | "Auxiliary SMBus Host Controller at 0x%x\n", | |
341 | piix4_smba); | |
342 | ||
343 | return piix4_smba; | |
344 | } | |
345 | ||
e154bf6f | 346 | static int piix4_transaction(struct i2c_adapter *piix4_adapter) |
1da177e4 | 347 | { |
e154bf6f AA |
348 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); |
349 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 LT |
350 | int temp; |
351 | int result = 0; | |
352 | int timeout = 0; | |
353 | ||
e154bf6f | 354 | dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
355 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
356 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
357 | inb_p(SMBHSTDAT1)); | |
358 | ||
359 | /* Make sure the SMBus host is ready to start transmitting */ | |
360 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 361 | dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " |
541e6a02 | 362 | "Resetting...\n", temp); |
1da177e4 LT |
363 | outb_p(temp, SMBHSTSTS); |
364 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 365 | dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); |
97140342 | 366 | return -EBUSY; |
1da177e4 | 367 | } else { |
e154bf6f | 368 | dev_dbg(&piix4_adapter->dev, "Successful!\n"); |
1da177e4 LT |
369 | } |
370 | } | |
371 | ||
372 | /* start the transaction by setting bit 6 */ | |
373 | outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); | |
374 | ||
375 | /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ | |
b1c1759c DM |
376 | if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ |
377 | msleep(2); | |
378 | else | |
379 | msleep(1); | |
380 | ||
b6a31950 | 381 | while ((++timeout < MAX_TIMEOUT) && |
b1c1759c | 382 | ((temp = inb_p(SMBHSTSTS)) & 0x01)) |
1da177e4 | 383 | msleep(1); |
1da177e4 LT |
384 | |
385 | /* If the SMBus is still busy, we give up */ | |
b6a31950 | 386 | if (timeout == MAX_TIMEOUT) { |
e154bf6f | 387 | dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); |
97140342 | 388 | result = -ETIMEDOUT; |
1da177e4 LT |
389 | } |
390 | ||
391 | if (temp & 0x10) { | |
97140342 | 392 | result = -EIO; |
e154bf6f | 393 | dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); |
1da177e4 LT |
394 | } |
395 | ||
396 | if (temp & 0x08) { | |
97140342 | 397 | result = -EIO; |
e154bf6f | 398 | dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " |
1da177e4 LT |
399 | "locked until next hard reset. (sorry!)\n"); |
400 | /* Clock stops and slave is stuck in mid-transmission */ | |
401 | } | |
402 | ||
403 | if (temp & 0x04) { | |
97140342 | 404 | result = -ENXIO; |
e154bf6f | 405 | dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); |
1da177e4 LT |
406 | } |
407 | ||
408 | if (inb_p(SMBHSTSTS) != 0x00) | |
409 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
410 | ||
411 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 412 | dev_err(&piix4_adapter->dev, "Failed reset at end of " |
1da177e4 LT |
413 | "transaction (%02x)\n", temp); |
414 | } | |
e154bf6f | 415 | dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
416 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
417 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
418 | inb_p(SMBHSTDAT1)); | |
419 | return result; | |
420 | } | |
421 | ||
97140342 | 422 | /* Return negative errno on error. */ |
1da177e4 LT |
423 | static s32 piix4_access(struct i2c_adapter * adap, u16 addr, |
424 | unsigned short flags, char read_write, | |
425 | u8 command, int size, union i2c_smbus_data * data) | |
426 | { | |
14a8086d AA |
427 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
428 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 | 429 | int i, len; |
97140342 | 430 | int status; |
1da177e4 LT |
431 | |
432 | switch (size) { | |
1da177e4 | 433 | case I2C_SMBUS_QUICK: |
fa63cd56 | 434 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
435 | SMBHSTADD); |
436 | size = PIIX4_QUICK; | |
437 | break; | |
438 | case I2C_SMBUS_BYTE: | |
fa63cd56 | 439 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
440 | SMBHSTADD); |
441 | if (read_write == I2C_SMBUS_WRITE) | |
442 | outb_p(command, SMBHSTCMD); | |
443 | size = PIIX4_BYTE; | |
444 | break; | |
445 | case I2C_SMBUS_BYTE_DATA: | |
fa63cd56 | 446 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
447 | SMBHSTADD); |
448 | outb_p(command, SMBHSTCMD); | |
449 | if (read_write == I2C_SMBUS_WRITE) | |
450 | outb_p(data->byte, SMBHSTDAT0); | |
451 | size = PIIX4_BYTE_DATA; | |
452 | break; | |
453 | case I2C_SMBUS_WORD_DATA: | |
fa63cd56 | 454 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
455 | SMBHSTADD); |
456 | outb_p(command, SMBHSTCMD); | |
457 | if (read_write == I2C_SMBUS_WRITE) { | |
458 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
459 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
460 | } | |
461 | size = PIIX4_WORD_DATA; | |
462 | break; | |
463 | case I2C_SMBUS_BLOCK_DATA: | |
fa63cd56 | 464 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
465 | SMBHSTADD); |
466 | outb_p(command, SMBHSTCMD); | |
467 | if (read_write == I2C_SMBUS_WRITE) { | |
468 | len = data->block[0]; | |
fa63cd56 JD |
469 | if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) |
470 | return -EINVAL; | |
1da177e4 LT |
471 | outb_p(len, SMBHSTDAT0); |
472 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ | |
473 | for (i = 1; i <= len; i++) | |
474 | outb_p(data->block[i], SMBBLKDAT); | |
475 | } | |
476 | size = PIIX4_BLOCK_DATA; | |
477 | break; | |
ac7fc4fb JD |
478 | default: |
479 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); | |
480 | return -EOPNOTSUPP; | |
1da177e4 LT |
481 | } |
482 | ||
483 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | |
484 | ||
e154bf6f | 485 | status = piix4_transaction(adap); |
97140342 DB |
486 | if (status) |
487 | return status; | |
1da177e4 LT |
488 | |
489 | if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) | |
490 | return 0; | |
491 | ||
492 | ||
493 | switch (size) { | |
3578a075 | 494 | case PIIX4_BYTE: |
1da177e4 LT |
495 | case PIIX4_BYTE_DATA: |
496 | data->byte = inb_p(SMBHSTDAT0); | |
497 | break; | |
498 | case PIIX4_WORD_DATA: | |
499 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
500 | break; | |
501 | case PIIX4_BLOCK_DATA: | |
502 | data->block[0] = inb_p(SMBHSTDAT0); | |
fa63cd56 JD |
503 | if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
504 | return -EPROTO; | |
1da177e4 LT |
505 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
506 | for (i = 1; i <= data->block[0]; i++) | |
507 | data->block[i] = inb_p(SMBBLKDAT); | |
508 | break; | |
509 | } | |
510 | return 0; | |
511 | } | |
512 | ||
513 | static u32 piix4_func(struct i2c_adapter *adapter) | |
514 | { | |
515 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
516 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
517 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
518 | } | |
519 | ||
8f9082c5 | 520 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
521 | .smbus_xfer = piix4_access, |
522 | .functionality = piix4_func, | |
523 | }; | |
524 | ||
3527bd50 | 525 | static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = { |
9b7389c0 JD |
526 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, |
527 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, | |
528 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, | |
529 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, | |
530 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, | |
531 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, | |
532 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, | |
3806e94b | 533 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, |
b996ac90 | 534 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x790b) }, |
9b7389c0 JD |
535 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
536 | PCI_DEVICE_ID_SERVERWORKS_OSB4) }, | |
537 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
538 | PCI_DEVICE_ID_SERVERWORKS_CSB5) }, | |
539 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
540 | PCI_DEVICE_ID_SERVERWORKS_CSB6) }, | |
541 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
542 | PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, | |
506a8b6c FL |
543 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
544 | PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, | |
1da177e4 LT |
545 | { 0, } |
546 | }; | |
547 | ||
548 | MODULE_DEVICE_TABLE (pci, piix4_ids); | |
549 | ||
e154bf6f | 550 | static struct i2c_adapter *piix4_main_adapter; |
2a2f7404 | 551 | static struct i2c_adapter *piix4_aux_adapter; |
e154bf6f | 552 | |
0b255e92 BP |
553 | static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, |
554 | struct i2c_adapter **padap) | |
e154bf6f AA |
555 | { |
556 | struct i2c_adapter *adap; | |
557 | struct i2c_piix4_adapdata *adapdata; | |
558 | int retval; | |
559 | ||
560 | adap = kzalloc(sizeof(*adap), GFP_KERNEL); | |
561 | if (adap == NULL) { | |
562 | release_region(smba, SMBIOSIZE); | |
563 | return -ENOMEM; | |
564 | } | |
565 | ||
566 | adap->owner = THIS_MODULE; | |
567 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
568 | adap->algo = &smbus_algorithm; | |
569 | ||
570 | adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); | |
571 | if (adapdata == NULL) { | |
572 | kfree(adap); | |
573 | release_region(smba, SMBIOSIZE); | |
574 | return -ENOMEM; | |
575 | } | |
576 | ||
577 | adapdata->smba = smba; | |
578 | ||
579 | /* set up the sysfs linkage to our parent device */ | |
580 | adap->dev.parent = &dev->dev; | |
581 | ||
582 | snprintf(adap->name, sizeof(adap->name), | |
583 | "SMBus PIIX4 adapter at %04x", smba); | |
584 | ||
585 | i2c_set_adapdata(adap, adapdata); | |
586 | ||
587 | retval = i2c_add_adapter(adap); | |
588 | if (retval) { | |
589 | dev_err(&dev->dev, "Couldn't register adapter!\n"); | |
590 | kfree(adapdata); | |
591 | kfree(adap); | |
592 | release_region(smba, SMBIOSIZE); | |
593 | return retval; | |
594 | } | |
595 | ||
596 | *padap = adap; | |
597 | return 0; | |
598 | } | |
599 | ||
0b255e92 | 600 | static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 LT |
601 | { |
602 | int retval; | |
603 | ||
76b3e28f CC |
604 | if ((dev->vendor == PCI_VENDOR_ID_ATI && |
605 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && | |
606 | dev->revision >= 0x40) || | |
607 | dev->vendor == PCI_VENDOR_ID_AMD) | |
87e1960e | 608 | /* base address location etc changed in SB800 */ |
a94dd00f | 609 | retval = piix4_setup_sb800(dev, id, 0); |
87e1960e SH |
610 | else |
611 | retval = piix4_setup(dev, id); | |
612 | ||
2a2f7404 | 613 | /* If no main SMBus found, give up */ |
14a8086d | 614 | if (retval < 0) |
1da177e4 LT |
615 | return retval; |
616 | ||
2a2f7404 AA |
617 | /* Try to register main SMBus adapter, give up if we can't */ |
618 | retval = piix4_add_adapter(dev, retval, &piix4_main_adapter); | |
619 | if (retval < 0) | |
620 | return retval; | |
621 | ||
622 | /* Check for auxiliary SMBus on some AMD chipsets */ | |
a94dd00f RM |
623 | retval = -ENODEV; |
624 | ||
2a2f7404 | 625 | if (dev->vendor == PCI_VENDOR_ID_ATI && |
a94dd00f RM |
626 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { |
627 | if (dev->revision < 0x40) { | |
628 | retval = piix4_setup_aux(dev, id, 0x58); | |
629 | } else { | |
630 | /* SB800 added aux bus too */ | |
631 | retval = piix4_setup_sb800(dev, id, 1); | |
2a2f7404 AA |
632 | } |
633 | } | |
634 | ||
a94dd00f RM |
635 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
636 | dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { | |
637 | retval = piix4_setup_sb800(dev, id, 1); | |
638 | } | |
639 | ||
640 | if (retval > 0) { | |
641 | /* Try to add the aux adapter if it exists, | |
642 | * piix4_add_adapter will clean up if this fails */ | |
643 | piix4_add_adapter(dev, retval, &piix4_aux_adapter); | |
644 | } | |
645 | ||
2a2f7404 | 646 | return 0; |
1da177e4 LT |
647 | } |
648 | ||
0b255e92 | 649 | static void piix4_adap_remove(struct i2c_adapter *adap) |
1da177e4 | 650 | { |
14a8086d AA |
651 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
652 | ||
653 | if (adapdata->smba) { | |
654 | i2c_del_adapter(adap); | |
655 | release_region(adapdata->smba, SMBIOSIZE); | |
e154bf6f AA |
656 | kfree(adapdata); |
657 | kfree(adap); | |
1da177e4 LT |
658 | } |
659 | } | |
660 | ||
0b255e92 | 661 | static void piix4_remove(struct pci_dev *dev) |
14a8086d | 662 | { |
e154bf6f AA |
663 | if (piix4_main_adapter) { |
664 | piix4_adap_remove(piix4_main_adapter); | |
665 | piix4_main_adapter = NULL; | |
666 | } | |
2a2f7404 AA |
667 | |
668 | if (piix4_aux_adapter) { | |
669 | piix4_adap_remove(piix4_aux_adapter); | |
670 | piix4_aux_adapter = NULL; | |
671 | } | |
14a8086d AA |
672 | } |
673 | ||
1da177e4 LT |
674 | static struct pci_driver piix4_driver = { |
675 | .name = "piix4_smbus", | |
676 | .id_table = piix4_ids, | |
677 | .probe = piix4_probe, | |
0b255e92 | 678 | .remove = piix4_remove, |
1da177e4 LT |
679 | }; |
680 | ||
56f21788 | 681 | module_pci_driver(piix4_driver); |
1da177e4 LT |
682 | |
683 | MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " | |
684 | "Philip Edelbrock <phil@netroedge.com>"); | |
685 | MODULE_DESCRIPTION("PIIX4 SMBus driver"); | |
686 | MODULE_LICENSE("GPL"); |