[deliverable/linux.git] / drivers / i2c / busses / i2c-piix4.c

/*
    Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
    Philip Edelbrock <phil@netroedge.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
   Supports:
	Intel PIIX4, 440MX
	Serverworks OSB4, CSB5, CSB6, HT-1000
	ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
	SMSC Victory66

   Note: we assume there can only be one device, with one SMBus interface.
*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <asm/io.h>


/* PIIX4 SMBus address offsets */
#define SMBHSTSTS	(0 + piix4_smba)
#define SMBHSLVSTS	(1 + piix4_smba)
#define SMBHSTCNT	(2 + piix4_smba)
#define SMBHSTCMD	(3 + piix4_smba)
#define SMBHSTADD	(4 + piix4_smba)
#define SMBHSTDAT0	(5 + piix4_smba)
#define SMBHSTDAT1	(6 + piix4_smba)
#define SMBBLKDAT	(7 + piix4_smba)
#define SMBSLVCNT	(8 + piix4_smba)
#define SMBSHDWCMD	(9 + piix4_smba)
#define SMBSLVEVT	(0xA + piix4_smba)
#define SMBSLVDAT	(0xC + piix4_smba)

/* count for request_region */
#define SMBIOSIZE	8

/* PCI Address Constants */
#define SMBBA		0x090
#define SMBHSTCFG	0x0D2
#define SMBSLVC		0x0D3
#define SMBSHDW1	0x0D4
#define SMBSHDW2	0x0D5
#define SMBREV		0x0D6

/* Other settings */
#define MAX_TIMEOUT	500
#define  ENABLE_INT9	0

/* PIIX4 constants */
#define PIIX4_QUICK		0x00
#define PIIX4_BYTE		0x04
#define PIIX4_BYTE_DATA		0x08
#define PIIX4_WORD_DATA		0x0C
#define PIIX4_BLOCK_DATA	0x14

/* insmod parameters */

/* If force is set to anything different from 0, we forcibly enable the
   PIIX4. DANGEROUS! */
static int force;
module_param (force, int, 0);
MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");

/* If force_addr is set to anything different from 0, we forcibly enable
   the PIIX4 at the given address. VERY DANGEROUS! */
static int force_addr;
module_param (force_addr, int, 0);
MODULE_PARM_DESC(force_addr,
		 "Forcibly enable the PIIX4 at the given address. "
		 "EXTREMELY DANGEROUS!");

static unsigned short piix4_smba;
static int srvrworks_csb5_delay;
static struct pci_driver piix4_driver;
static struct i2c_adapter piix4_adapter;

static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
	{
		.ident = "Sapphire AM2RD790",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
		},
	},
	{
		.ident = "DFI Lanparty UT 790FX",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
		},
	},
	{ }
};

/* The IBM entry is in a separate table because we only check it
   on Intel-based systems */
static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
	{
		.ident = "IBM",
		.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	},
	{ },
};

static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
				const struct pci_device_id *id)
{
	unsigned char temp;

	if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
	    (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
		srvrworks_csb5_delay = 1;

	/* On some motherboards, it was reported that accessing the SMBus
	   caused severe hardware problems */
	if (dmi_check_system(piix4_dmi_blacklist)) {
		dev_err(&PIIX4_dev->dev,
			"Accessing the SMBus on this system is unsafe!\n");
		return -EPERM;
	}

	/* Don't access SMBus on IBM systems which get corrupted eeproms */
	if (dmi_check_system(piix4_dmi_ibm) &&
			PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
		dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
			"may corrupt your serial eeprom! Refusing to load "
			"module!\n");
		return -EPERM;
	}

	/* Determine the address of the SMBus areas */
	if (force_addr) {
		piix4_smba = force_addr & 0xfff0;
		force = 0;
	} else {
		pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
		piix4_smba &= 0xfff0;
		if(piix4_smba == 0) {
			dev_err(&PIIX4_dev->dev, "SMBus base address "
				"uninitialized - upgrade BIOS or use "
				"force_addr=0xaddr\n");
			return -ENODEV;
		}
	}

	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
		return -EBUSY;

	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
			piix4_smba);
		return -EBUSY;
	}

	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);

	/* If force_addr is set, we program the new address here. Just to make
	   sure, we disable the PIIX4 first. */
	if (force_addr) {
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
		pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
		dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
			"new address %04x!\n", piix4_smba);
	} else if ((temp & 1) == 0) {
		if (force) {
			/* This should never need to be done, but has been
			 * noted that many Dell machines have the SMBus
			 * interface on the PIIX4 disabled!? NOTE: This assumes
			 * I/O space and other allocations WERE done by the
			 * Bios!  Don't complain if your hardware does weird
			 * things after enabling this. :') Check for Bios
			 * updates before resorting to this.
			 */
			pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
					      temp | 1);
			dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
				"WARNING: SMBus interface has been "
				"FORCEFULLY ENABLED!\n");
		} else {
			dev_err(&PIIX4_dev->dev,
				"Host SMBus controller not enabled!\n");
			release_region(piix4_smba, SMBIOSIZE);
			piix4_smba = 0;
			return -ENODEV;
		}
	}

	if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	else if ((temp & 0x0E) == 0)
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	else
		dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
			"(or code out of date)!\n");

	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
	dev_info(&PIIX4_dev->dev,
		 "SMBus Host Controller at 0x%x, revision %d\n",
		 piix4_smba, temp);

	return 0;
}

static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
				const struct pci_device_id *id)
{
	unsigned short smba_idx = 0xcd6;
	u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;

	/* SB800 SMBus does not support forcing address */
	if (force || force_addr) {
		dev_err(&PIIX4_dev->dev, "SB800 SMBus does not support "
			"forcing address!\n");
		return -EINVAL;
	}

	/* Determine the address of the SMBus areas */
	if (!request_region(smba_idx, 2, "smba_idx")) {
		dev_err(&PIIX4_dev->dev, "SMBus base address index region "
			"0x%x already in use!\n", smba_idx);
		return -EBUSY;
	}
	outb_p(smb_en, smba_idx);
	smba_en_lo = inb_p(smba_idx + 1);
	outb_p(smb_en + 1, smba_idx);
	smba_en_hi = inb_p(smba_idx + 1);
	release_region(smba_idx, 2);

	if ((smba_en_lo & 1) == 0) {
		dev_err(&PIIX4_dev->dev,
			"Host SMBus controller not enabled!\n");
		return -ENODEV;
	}

	piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
		return -EBUSY;

	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
			piix4_smba);
		return -EBUSY;
	}

	/* Request the SMBus I2C bus config region */
	if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
		dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
			"0x%x already in use!\n", piix4_smba + i2ccfg_offset);
		release_region(piix4_smba, SMBIOSIZE);
		piix4_smba = 0;
		return -EBUSY;
	}
	i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
	release_region(piix4_smba + i2ccfg_offset, 1);

	if (i2ccfg & 1)
		dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
	else
		dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");

	dev_info(&PIIX4_dev->dev,
		 "SMBus Host Controller at 0x%x, revision %d\n",
		 piix4_smba, i2ccfg >> 4);

	return 0;
}

static int piix4_transaction(void)
{
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));

	/* Make sure the SMBus host is ready to start transmitting */
	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
			"Resetting...\n", temp);
		outb_p(temp, SMBHSTSTS);
		if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
			dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
			return -EBUSY;
		} else {
			dev_dbg(&piix4_adapter.dev, "Successful!\n");
		}
	}

	/* start the transaction by setting bit 6 */
	outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);

	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
	if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
		msleep(2);
	else
		msleep(1);

	while ((timeout++ < MAX_TIMEOUT) &&
	       ((temp = inb_p(SMBHSTSTS)) & 0x01))
		msleep(1);

	/* If the SMBus is still busy, we give up */
	if (timeout >= MAX_TIMEOUT) {
		dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
		result = -ETIMEDOUT;
	}

	if (temp & 0x10) {
		result = -EIO;
		dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
	}

	if (temp & 0x08) {
		result = -EIO;
		dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
			"locked until next hard reset. (sorry!)\n");
		/* Clock stops and slave is stuck in mid-transmission */
	}

	if (temp & 0x04) {
		result = -ENXIO;
		dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
	}

	if (inb_p(SMBHSTSTS) != 0x00)
		outb_p(inb(SMBHSTSTS), SMBHSTSTS);

	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_err(&piix4_adapter.dev, "Failed reset at end of "
			"transaction (%02x)\n", temp);
	}
	dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));
	return result;
}

/* Return negative errno on error. */
static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
		 unsigned short flags, char read_write,
		 u8 command, int size, union i2c_smbus_data * data)
{
	int i, len;
	int status;

	switch (size) {
	case I2C_SMBUS_QUICK:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		size = PIIX4_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMBHSTCMD);
		size = PIIX4_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, SMBHSTDAT0);
		size = PIIX4_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word & 0xff, SMBHSTDAT0);
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
		}
		size = PIIX4_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
				return -EINVAL;
			outb_p(len, SMBHSTDAT0);
			i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
			for (i = 1; i <= len; i++)
				outb_p(data->block[i], SMBBLKDAT);
		}
		size = PIIX4_BLOCK_DATA;
		break;
	default:
		dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
		return -EOPNOTSUPP;
	}

	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);

	status = piix4_transaction();
	if (status)
		return status;

	if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
		return 0;


	switch (size) {
	case PIIX4_BYTE:
	case PIIX4_BYTE_DATA:
		data->byte = inb_p(SMBHSTDAT0);
		break;
	case PIIX4_WORD_DATA:
		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
		break;
	case PIIX4_BLOCK_DATA:
		data->block[0] = inb_p(SMBHSTDAT0);
		if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
			return -EPROTO;
		i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
		for (i = 1; i <= data->block[0]; i++)
			data->block[i] = inb_p(SMBBLKDAT);
		break;
	}
	return 0;
}

static u32 piix4_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= piix4_access,
	.functionality	= piix4_func,
};

static struct i2c_adapter piix4_adapter = {
	.owner		= THIS_MODULE,
	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
	.algo		= &smbus_algorithm,
};

static struct pci_device_id piix4_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_OSB4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_CSB5) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_CSB6) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, piix4_ids);

static int __devinit piix4_probe(struct pci_dev *dev,
				const struct pci_device_id *id)
{
	int retval;

	if ((dev->vendor == PCI_VENDOR_ID_ATI) &&
	    (dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) &&
	    (dev->revision >= 0x40))
		/* base address location etc changed in SB800 */
		retval = piix4_setup_sb800(dev, id);
	else
		retval = piix4_setup(dev, id);

	if (retval)
		return retval;

	/* set up the sysfs linkage to our parent device */
	piix4_adapter.dev.parent = &dev->dev;

	snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
		"SMBus PIIX4 adapter at %04x", piix4_smba);

	if ((retval = i2c_add_adapter(&piix4_adapter))) {
		dev_err(&dev->dev, "Couldn't register adapter!\n");
		release_region(piix4_smba, SMBIOSIZE);
		piix4_smba = 0;
	}

	return retval;
}

static void __devexit piix4_remove(struct pci_dev *dev)
{
	if (piix4_smba) {
		i2c_del_adapter(&piix4_adapter);
		release_region(piix4_smba, SMBIOSIZE);
		piix4_smba = 0;
	}
}

static struct pci_driver piix4_driver = {
	.name		= "piix4_smbus",
	.id_table	= piix4_ids,
	.probe		= piix4_probe,
	.remove		= __devexit_p(piix4_remove),
};

static int __init i2c_piix4_init(void)
{
	return pci_register_driver(&piix4_driver);
}

static void __exit i2c_piix4_exit(void)
{
	pci_unregister_driver(&piix4_driver);
}

MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
		"Philip Edelbrock <phil@netroedge.com>");
MODULE_DESCRIPTION("PIIX4 SMBus driver");
MODULE_LICENSE("GPL");

module_init(i2c_piix4_init);
module_exit(i2c_piix4_exit);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
	3	Philip Edelbrock <phil@netroedge.com>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/*
	21	Supports:
	22	Intel PIIX4, 440MX
5f7ea3c5	23	Serverworks OSB4, CSB5, CSB6, HT-1000
60693e5a	24	ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
1da177e4 LT	25	SMSC Victory66
	26
	27	Note: we assume there can only be one device, with one SMBus interface.
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/moduleparam.h>
	32	#include <linux/pci.h>
	33	#include <linux/kernel.h>
	34	#include <linux/delay.h>
	35	#include <linux/stddef.h>
1da177e4 LT	36	#include <linux/ioport.h>
	37	#include <linux/i2c.h>
	38	#include <linux/init.h>
1da177e4	39	#include <linux/dmi.h>
54fb4a05	40	#include <linux/acpi.h>
1da177e4 LT	41	#include <asm/io.h>
	42
	43
1da177e4 LT	44	/* PIIX4 SMBus address offsets */
	45	#define SMBHSTSTS (0 + piix4_smba)
	46	#define SMBHSLVSTS (1 + piix4_smba)
	47	#define SMBHSTCNT (2 + piix4_smba)
	48	#define SMBHSTCMD (3 + piix4_smba)
	49	#define SMBHSTADD (4 + piix4_smba)
	50	#define SMBHSTDAT0 (5 + piix4_smba)
	51	#define SMBHSTDAT1 (6 + piix4_smba)
	52	#define SMBBLKDAT (7 + piix4_smba)
	53	#define SMBSLVCNT (8 + piix4_smba)
	54	#define SMBSHDWCMD (9 + piix4_smba)
	55	#define SMBSLVEVT (0xA + piix4_smba)
	56	#define SMBSLVDAT (0xC + piix4_smba)
	57
	58	/* count for request_region */
	59	#define SMBIOSIZE 8
	60
	61	/* PCI Address Constants */
	62	#define SMBBA 0x090
	63	#define SMBHSTCFG 0x0D2
	64	#define SMBSLVC 0x0D3
	65	#define SMBSHDW1 0x0D4
	66	#define SMBSHDW2 0x0D5
	67	#define SMBREV 0x0D6
	68
	69	/* Other settings */
	70	#define MAX_TIMEOUT 500
	71	#define ENABLE_INT9 0
	72
	73	/* PIIX4 constants */
	74	#define PIIX4_QUICK 0x00
	75	#define PIIX4_BYTE 0x04
	76	#define PIIX4_BYTE_DATA 0x08
	77	#define PIIX4_WORD_DATA 0x0C
	78	#define PIIX4_BLOCK_DATA 0x14
	79
	80	/* insmod parameters */
	81
	82	/* If force is set to anything different from 0, we forcibly enable the
	83	PIIX4. DANGEROUS! */
60507095	84	static int force;
1da177e4 LT	85	module_param (force, int, 0);
	86	MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
	87
	88	/* If force_addr is set to anything different from 0, we forcibly enable
	89	the PIIX4 at the given address. VERY DANGEROUS! */
60507095	90	static int force_addr;
1da177e4 LT	91	module_param (force_addr, int, 0);
	92	MODULE_PARM_DESC(force_addr,
	93	"Forcibly enable the PIIX4 at the given address. "
	94	"EXTREMELY DANGEROUS!");
	95
60507095	96	static unsigned short piix4_smba;
b1c1759c	97	static int srvrworks_csb5_delay;
d6072f84	98	static struct pci_driver piix4_driver;
1da177e4 LT	99	static struct i2c_adapter piix4_adapter;
1da177e4 LT	100
c2fc54fc JD	101	static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
	102	{
	103	.ident = "Sapphire AM2RD790",
	104	.matches = {
	105	DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
	106	DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
	107	},
	108	},
	109	{
	110	.ident = "DFI Lanparty UT 790FX",
	111	.matches = {
	112	DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
	113	DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
	114	},
	115	},
	116	{ }
	117	};
	118
	119	/* The IBM entry is in a separate table because we only check it
	120	on Intel-based systems */
	121	static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
1da177e4 LT	122	{
	123	.ident = "IBM",
	124	.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	125	},
	126	{ },
	127	};
	128
	129	static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
	130	const struct pci_device_id *id)
	131	{
	132	unsigned char temp;
	133
b1c1759c DM	134	if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
	135	(PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
	136	srvrworks_csb5_delay = 1;
	137
c2fc54fc JD	138	/* On some motherboards, it was reported that accessing the SMBus
	139	caused severe hardware problems */
	140	if (dmi_check_system(piix4_dmi_blacklist)) {
	141	dev_err(&PIIX4_dev->dev,
	142	"Accessing the SMBus on this system is unsafe!\n");
	143	return -EPERM;
	144	}
	145
1da177e4	146	/* Don't access SMBus on IBM systems which get corrupted eeproms */
c2fc54fc	147	if (dmi_check_system(piix4_dmi_ibm) &&
1da177e4	148	PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
f9ba6c04	149	dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
1da177e4 LT	150	"may corrupt your serial eeprom! Refusing to load "
	151	"module!\n");
	152	return -EPERM;
	153	}
	154
	155	/* Determine the address of the SMBus areas */
	156	if (force_addr) {
	157	piix4_smba = force_addr & 0xfff0;
	158	force = 0;
	159	} else {
	160	pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
	161	piix4_smba &= 0xfff0;
	162	if(piix4_smba == 0) {
fa63cd56	163	dev_err(&PIIX4_dev->dev, "SMBus base address "
1da177e4 LT	164	"uninitialized - upgrade BIOS or use "
	165	"force_addr=0xaddr\n");
	166	return -ENODEV;
	167	}
	168	}
	169
54fb4a05 JD	170	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
	171	return -EBUSY;
	172
d6072f84	173	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
fa63cd56	174	dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
1da177e4	175	piix4_smba);
fa63cd56	176	return -EBUSY;
1da177e4 LT	177	}
	178
	179	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
	180
1da177e4 LT	181	/* If force_addr is set, we program the new address here. Just to make
	182	sure, we disable the PIIX4 first. */
	183	if (force_addr) {
	184	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
	185	pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
	186	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp \| 0x01);
	187	dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
	188	"new address %04x!\n", piix4_smba);
	189	} else if ((temp & 1) == 0) {
	190	if (force) {
	191	/* This should never need to be done, but has been
	192	* noted that many Dell machines have the SMBus
	193	* interface on the PIIX4 disabled!? NOTE: This assumes
	194	* I/O space and other allocations WERE done by the
	195	* Bios! Don't complain if your hardware does weird
	196	* things after enabling this. :') Check for Bios
	197	* updates before resorting to this.
	198	*/
	199	pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
	200	temp \| 1);
	201	dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
	202	"WARNING: SMBus interface has been "
	203	"FORCEFULLY ENABLED!\n");
	204	} else {
	205	dev_err(&PIIX4_dev->dev,
	206	"Host SMBus controller not enabled!\n");
	207	release_region(piix4_smba, SMBIOSIZE);
	208	piix4_smba = 0;
	209	return -ENODEV;
	210	}
	211	}
	212
54aaa1ca	213	if (((temp & 0x0E) == 8) \|\| ((temp & 0x0E) == 2))
1da177e4 LT	214	dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	215	else if ((temp & 0x0E) == 0)
	216	dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	217	else
	218	dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
	219	"(or code out of date)!\n");
	220
	221	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
fa63cd56 JD	222	dev_info(&PIIX4_dev->dev,
	223	"SMBus Host Controller at 0x%x, revision %d\n",
	224	piix4_smba, temp);
1da177e4 LT	225
	226	return 0;
	227	}
	228
87e1960e SH	229	static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
	230	const struct pci_device_id *id)
	231	{
	232	unsigned short smba_idx = 0xcd6;
	233	u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
	234
	235	/* SB800 SMBus does not support forcing address */
	236	if (force \|\| force_addr) {
	237	dev_err(&PIIX4_dev->dev, "SB800 SMBus does not support "
	238	"forcing address!\n");
	239	return -EINVAL;
	240	}
	241
	242	/* Determine the address of the SMBus areas */
	243	if (!request_region(smba_idx, 2, "smba_idx")) {
	244	dev_err(&PIIX4_dev->dev, "SMBus base address index region "
	245	"0x%x already in use!\n", smba_idx);
	246	return -EBUSY;
	247	}
	248	outb_p(smb_en, smba_idx);
	249	smba_en_lo = inb_p(smba_idx + 1);
	250	outb_p(smb_en + 1, smba_idx);
	251	smba_en_hi = inb_p(smba_idx + 1);
	252	release_region(smba_idx, 2);
	253
	254	if ((smba_en_lo & 1) == 0) {
	255	dev_err(&PIIX4_dev->dev,
	256	"Host SMBus controller not enabled!\n");
	257	return -ENODEV;
	258	}
	259
	260	piix4_smba = ((smba_en_hi << 8) \| smba_en_lo) & 0xffe0;
	261	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
	262	return -EBUSY;
	263
	264	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
	265	dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
	266	piix4_smba);
	267	return -EBUSY;
	268	}
	269
	270	/* Request the SMBus I2C bus config region */
	271	if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
	272	dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
	273	"0x%x already in use!\n", piix4_smba + i2ccfg_offset);
	274	release_region(piix4_smba, SMBIOSIZE);
	275	piix4_smba = 0;
	276	return -EBUSY;
	277	}
	278	i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
	279	release_region(piix4_smba + i2ccfg_offset, 1);
	280
	281	if (i2ccfg & 1)
	282	dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
	283	else
	284	dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");
	285
	286	dev_info(&PIIX4_dev->dev,
	287	"SMBus Host Controller at 0x%x, revision %d\n",
	288	piix4_smba, i2ccfg >> 4);
	289
	290	return 0;
	291	}
	292
1da177e4 LT	293	static int piix4_transaction(void)
	294	{
	295	int temp;
	296	int result = 0;
	297	int timeout = 0;
	298
	299	dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
	300	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	301	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	302	inb_p(SMBHSTDAT1));
	303
	304	/* Make sure the SMBus host is ready to start transmitting */
	305	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	306	dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
541e6a02	307	"Resetting...\n", temp);
1da177e4 LT	308	outb_p(temp, SMBHSTSTS);
	309	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	310	dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
97140342	311	return -EBUSY;
1da177e4	312	} else {
c5d21b7f	313	dev_dbg(&piix4_adapter.dev, "Successful!\n");
1da177e4 LT	314	}
	315	}
	316
	317	/* start the transaction by setting bit 6 */
	318	outb_p(inb(SMBHSTCNT) \| 0x040, SMBHSTCNT);
	319
	320	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
b1c1759c DM	321	if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
	322	msleep(2);
	323	else
	324	msleep(1);
	325
	326	while ((timeout++ < MAX_TIMEOUT) &&
	327	((temp = inb_p(SMBHSTSTS)) & 0x01))
1da177e4	328	msleep(1);
1da177e4 LT	329
	330	/* If the SMBus is still busy, we give up */
	331	if (timeout >= MAX_TIMEOUT) {
	332	dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
97140342	333	result = -ETIMEDOUT;
1da177e4 LT	334	}
	335
	336	if (temp & 0x10) {
97140342	337	result = -EIO;
1da177e4 LT	338	dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
	339	}
	340
	341	if (temp & 0x08) {
97140342	342	result = -EIO;
1da177e4 LT	343	dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
	344	"locked until next hard reset. (sorry!)\n");
	345	/* Clock stops and slave is stuck in mid-transmission */
	346	}
	347
	348	if (temp & 0x04) {
97140342	349	result = -ENXIO;
1da177e4 LT	350	dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
	351	}
	352
	353	if (inb_p(SMBHSTSTS) != 0x00)
	354	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
	355
	356	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	357	dev_err(&piix4_adapter.dev, "Failed reset at end of "
	358	"transaction (%02x)\n", temp);
	359	}
	360	dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
	361	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	362	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	363	inb_p(SMBHSTDAT1));
	364	return result;
	365	}
	366
97140342	367	/* Return negative errno on error. */
1da177e4 LT	368	static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
	369	unsigned short flags, char read_write,
	370	u8 command, int size, union i2c_smbus_data * data)
	371	{
	372	int i, len;
97140342	373	int status;
1da177e4 LT	374
1da177e4 LT	375	switch (size) {
1da177e4	376	case I2C_SMBUS_QUICK:
fa63cd56	377	outb_p((addr << 1) \| read_write,
1da177e4 LT	378	SMBHSTADD);
	379	size = PIIX4_QUICK;
	380	break;
	381	case I2C_SMBUS_BYTE:
fa63cd56	382	outb_p((addr << 1) \| read_write,
1da177e4 LT	383	SMBHSTADD);
	384	if (read_write == I2C_SMBUS_WRITE)
	385	outb_p(command, SMBHSTCMD);
	386	size = PIIX4_BYTE;
	387	break;
	388	case I2C_SMBUS_BYTE_DATA:
fa63cd56	389	outb_p((addr << 1) \| read_write,
1da177e4 LT	390	SMBHSTADD);
	391	outb_p(command, SMBHSTCMD);
	392	if (read_write == I2C_SMBUS_WRITE)
	393	outb_p(data->byte, SMBHSTDAT0);
	394	size = PIIX4_BYTE_DATA;
	395	break;
	396	case I2C_SMBUS_WORD_DATA:
fa63cd56	397	outb_p((addr << 1) \| read_write,
1da177e4 LT	398	SMBHSTADD);
	399	outb_p(command, SMBHSTCMD);
	400	if (read_write == I2C_SMBUS_WRITE) {
	401	outb_p(data->word & 0xff, SMBHSTDAT0);
	402	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
	403	}
	404	size = PIIX4_WORD_DATA;
	405	break;
	406	case I2C_SMBUS_BLOCK_DATA:
fa63cd56	407	outb_p((addr << 1) \| read_write,
1da177e4 LT	408	SMBHSTADD);
	409	outb_p(command, SMBHSTCMD);
	410	if (read_write == I2C_SMBUS_WRITE) {
	411	len = data->block[0];
fa63cd56 JD	412	if (len == 0 \|\| len > I2C_SMBUS_BLOCK_MAX)
fa63cd56 JD	413	return -EINVAL;
1da177e4 LT	414	outb_p(len, SMBHSTDAT0);
	415	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
	416	for (i = 1; i <= len; i++)
	417	outb_p(data->block[i], SMBBLKDAT);
	418	}
	419	size = PIIX4_BLOCK_DATA;
	420	break;
ac7fc4fb JD	421	default:
	422	dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
	423	return -EOPNOTSUPP;
1da177e4 LT	424	}
	425
	426	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
	427
97140342 DB	428	status = piix4_transaction();
	429	if (status)
	430	return status;
1da177e4 LT	431
	432	if ((read_write == I2C_SMBUS_WRITE) \|\| (size == PIIX4_QUICK))
	433	return 0;
	434
	435
	436	switch (size) {
3578a075	437	case PIIX4_BYTE:
1da177e4 LT	438	case PIIX4_BYTE_DATA:
	439	data->byte = inb_p(SMBHSTDAT0);
	440	break;
	441	case PIIX4_WORD_DATA:
	442	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
	443	break;
	444	case PIIX4_BLOCK_DATA:
	445	data->block[0] = inb_p(SMBHSTDAT0);
fa63cd56 JD	446	if (data->block[0] == 0 \|\| data->block[0] > I2C_SMBUS_BLOCK_MAX)
fa63cd56 JD	447	return -EPROTO;
1da177e4 LT	448	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
	449	for (i = 1; i <= data->block[0]; i++)
	450	data->block[i] = inb_p(SMBBLKDAT);
	451	break;
	452	}
	453	return 0;
	454	}
	455
	456	static u32 piix4_func(struct i2c_adapter *adapter)
	457	{
	458	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	459	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	460	I2C_FUNC_SMBUS_BLOCK_DATA;
	461	}
	462
8f9082c5	463	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	464	.smbus_xfer = piix4_access,
	465	.functionality = piix4_func,
	466	};
	467
	468	static struct i2c_adapter piix4_adapter = {
	469	.owner = THIS_MODULE,
3401b2ff	470	.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD,
1da177e4	471	.algo = &smbus_algorithm,
1da177e4 LT	472	};
	473
	474	static struct pci_device_id piix4_ids[] = {
9b7389c0 JD	475	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
	476	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
	477	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
	478	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
	479	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
	480	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
	481	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
	482	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	483	PCI_DEVICE_ID_SERVERWORKS_OSB4) },
	484	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	485	PCI_DEVICE_ID_SERVERWORKS_CSB5) },
	486	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	487	PCI_DEVICE_ID_SERVERWORKS_CSB6) },
	488	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	489	PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
1da177e4 LT	490	{ 0, }
	491	};
	492
	493	MODULE_DEVICE_TABLE (pci, piix4_ids);
	494
	495	static int __devinit piix4_probe(struct pci_dev *dev,
	496	const struct pci_device_id *id)
	497	{
	498	int retval;
	499
87e1960e SH	500	if ((dev->vendor == PCI_VENDOR_ID_ATI) &&
	501	(dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) &&
	502	(dev->revision >= 0x40))
	503	/* base address location etc changed in SB800 */
	504	retval = piix4_setup_sb800(dev, id);
	505	else
	506	retval = piix4_setup(dev, id);
	507
1da177e4 LT	508	if (retval)
	509	return retval;
	510
405ae7d3	511	/* set up the sysfs linkage to our parent device */
1da177e4 LT	512	piix4_adapter.dev.parent = &dev->dev;
1da177e4 LT	513
2096b956	514	snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
1da177e4 LT	515	"SMBus PIIX4 adapter at %04x", piix4_smba);
	516
	517	if ((retval = i2c_add_adapter(&piix4_adapter))) {
	518	dev_err(&dev->dev, "Couldn't register adapter!\n");
	519	release_region(piix4_smba, SMBIOSIZE);
	520	piix4_smba = 0;
	521	}
	522
	523	return retval;
	524	}
	525
	526	static void __devexit piix4_remove(struct pci_dev *dev)
	527	{
	528	if (piix4_smba) {
	529	i2c_del_adapter(&piix4_adapter);
	530	release_region(piix4_smba, SMBIOSIZE);
	531	piix4_smba = 0;
	532	}
	533	}
	534
	535	static struct pci_driver piix4_driver = {
	536	.name = "piix4_smbus",
	537	.id_table = piix4_ids,
	538	.probe = piix4_probe,
	539	.remove = __devexit_p(piix4_remove),
	540	};
	541
	542	static int __init i2c_piix4_init(void)
	543	{
	544	return pci_register_driver(&piix4_driver);
	545	}
	546
	547	static void __exit i2c_piix4_exit(void)
	548	{
	549	pci_unregister_driver(&piix4_driver);
	550	}
	551
	552	MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
	553	"Philip Edelbrock <phil@netroedge.com>");
	554	MODULE_DESCRIPTION("PIIX4 SMBus driver");
	555	MODULE_LICENSE("GPL");
	556
	557	module_init(i2c_piix4_init);
	558	module_exit(i2c_piix4_exit);