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1da177e4 LT |
1 | /* |
2 | piix4.c - Part of lm_sensors, Linux kernel modules for hardware | |
3 | monitoring | |
4 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and | |
5 | Philip Edelbrock <phil@netroedge.com> | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | /* | |
23 | Supports: | |
24 | Intel PIIX4, 440MX | |
5f7ea3c5 | 25 | Serverworks OSB4, CSB5, CSB6, HT-1000 |
60693e5a | 26 | ATI IXP200, IXP300, IXP400, SB600, SB700, SB800 |
1da177e4 LT |
27 | SMSC Victory66 |
28 | ||
29 | Note: we assume there can only be one device, with one SMBus interface. | |
30 | */ | |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/stddef.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/i2c.h> | |
40 | #include <linux/init.h> | |
1da177e4 LT |
41 | #include <linux/dmi.h> |
42 | #include <asm/io.h> | |
43 | ||
44 | ||
1da177e4 LT |
45 | /* PIIX4 SMBus address offsets */ |
46 | #define SMBHSTSTS (0 + piix4_smba) | |
47 | #define SMBHSLVSTS (1 + piix4_smba) | |
48 | #define SMBHSTCNT (2 + piix4_smba) | |
49 | #define SMBHSTCMD (3 + piix4_smba) | |
50 | #define SMBHSTADD (4 + piix4_smba) | |
51 | #define SMBHSTDAT0 (5 + piix4_smba) | |
52 | #define SMBHSTDAT1 (6 + piix4_smba) | |
53 | #define SMBBLKDAT (7 + piix4_smba) | |
54 | #define SMBSLVCNT (8 + piix4_smba) | |
55 | #define SMBSHDWCMD (9 + piix4_smba) | |
56 | #define SMBSLVEVT (0xA + piix4_smba) | |
57 | #define SMBSLVDAT (0xC + piix4_smba) | |
58 | ||
59 | /* count for request_region */ | |
60 | #define SMBIOSIZE 8 | |
61 | ||
62 | /* PCI Address Constants */ | |
63 | #define SMBBA 0x090 | |
64 | #define SMBHSTCFG 0x0D2 | |
65 | #define SMBSLVC 0x0D3 | |
66 | #define SMBSHDW1 0x0D4 | |
67 | #define SMBSHDW2 0x0D5 | |
68 | #define SMBREV 0x0D6 | |
69 | ||
70 | /* Other settings */ | |
71 | #define MAX_TIMEOUT 500 | |
72 | #define ENABLE_INT9 0 | |
73 | ||
74 | /* PIIX4 constants */ | |
75 | #define PIIX4_QUICK 0x00 | |
76 | #define PIIX4_BYTE 0x04 | |
77 | #define PIIX4_BYTE_DATA 0x08 | |
78 | #define PIIX4_WORD_DATA 0x0C | |
79 | #define PIIX4_BLOCK_DATA 0x14 | |
80 | ||
81 | /* insmod parameters */ | |
82 | ||
83 | /* If force is set to anything different from 0, we forcibly enable the | |
84 | PIIX4. DANGEROUS! */ | |
60507095 | 85 | static int force; |
1da177e4 LT |
86 | module_param (force, int, 0); |
87 | MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); | |
88 | ||
89 | /* If force_addr is set to anything different from 0, we forcibly enable | |
90 | the PIIX4 at the given address. VERY DANGEROUS! */ | |
60507095 | 91 | static int force_addr; |
1da177e4 LT |
92 | module_param (force_addr, int, 0); |
93 | MODULE_PARM_DESC(force_addr, | |
94 | "Forcibly enable the PIIX4 at the given address. " | |
95 | "EXTREMELY DANGEROUS!"); | |
96 | ||
60507095 | 97 | static unsigned short piix4_smba; |
b1c1759c | 98 | static int srvrworks_csb5_delay; |
d6072f84 | 99 | static struct pci_driver piix4_driver; |
1da177e4 LT |
100 | static struct i2c_adapter piix4_adapter; |
101 | ||
c2fc54fc JD |
102 | static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = { |
103 | { | |
104 | .ident = "Sapphire AM2RD790", | |
105 | .matches = { | |
106 | DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), | |
107 | DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), | |
108 | }, | |
109 | }, | |
110 | { | |
111 | .ident = "DFI Lanparty UT 790FX", | |
112 | .matches = { | |
113 | DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), | |
114 | DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), | |
115 | }, | |
116 | }, | |
117 | { } | |
118 | }; | |
119 | ||
120 | /* The IBM entry is in a separate table because we only check it | |
121 | on Intel-based systems */ | |
122 | static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = { | |
1da177e4 LT |
123 | { |
124 | .ident = "IBM", | |
125 | .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, | |
126 | }, | |
127 | { }, | |
128 | }; | |
129 | ||
130 | static int __devinit piix4_setup(struct pci_dev *PIIX4_dev, | |
131 | const struct pci_device_id *id) | |
132 | { | |
133 | unsigned char temp; | |
134 | ||
b1c1759c DM |
135 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && |
136 | (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) | |
137 | srvrworks_csb5_delay = 1; | |
138 | ||
c2fc54fc JD |
139 | /* On some motherboards, it was reported that accessing the SMBus |
140 | caused severe hardware problems */ | |
141 | if (dmi_check_system(piix4_dmi_blacklist)) { | |
142 | dev_err(&PIIX4_dev->dev, | |
143 | "Accessing the SMBus on this system is unsafe!\n"); | |
144 | return -EPERM; | |
145 | } | |
146 | ||
1da177e4 | 147 | /* Don't access SMBus on IBM systems which get corrupted eeproms */ |
c2fc54fc | 148 | if (dmi_check_system(piix4_dmi_ibm) && |
1da177e4 | 149 | PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { |
f9ba6c04 | 150 | dev_err(&PIIX4_dev->dev, "IBM system detected; this module " |
1da177e4 LT |
151 | "may corrupt your serial eeprom! Refusing to load " |
152 | "module!\n"); | |
153 | return -EPERM; | |
154 | } | |
155 | ||
156 | /* Determine the address of the SMBus areas */ | |
157 | if (force_addr) { | |
158 | piix4_smba = force_addr & 0xfff0; | |
159 | force = 0; | |
160 | } else { | |
161 | pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); | |
162 | piix4_smba &= 0xfff0; | |
163 | if(piix4_smba == 0) { | |
fa63cd56 | 164 | dev_err(&PIIX4_dev->dev, "SMBus base address " |
1da177e4 LT |
165 | "uninitialized - upgrade BIOS or use " |
166 | "force_addr=0xaddr\n"); | |
167 | return -ENODEV; | |
168 | } | |
169 | } | |
170 | ||
d6072f84 | 171 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { |
fa63cd56 | 172 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", |
1da177e4 | 173 | piix4_smba); |
fa63cd56 | 174 | return -EBUSY; |
1da177e4 LT |
175 | } |
176 | ||
177 | pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); | |
178 | ||
1da177e4 LT |
179 | /* If force_addr is set, we program the new address here. Just to make |
180 | sure, we disable the PIIX4 first. */ | |
181 | if (force_addr) { | |
182 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); | |
183 | pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); | |
184 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); | |
185 | dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " | |
186 | "new address %04x!\n", piix4_smba); | |
187 | } else if ((temp & 1) == 0) { | |
188 | if (force) { | |
189 | /* This should never need to be done, but has been | |
190 | * noted that many Dell machines have the SMBus | |
191 | * interface on the PIIX4 disabled!? NOTE: This assumes | |
192 | * I/O space and other allocations WERE done by the | |
193 | * Bios! Don't complain if your hardware does weird | |
194 | * things after enabling this. :') Check for Bios | |
195 | * updates before resorting to this. | |
196 | */ | |
197 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, | |
198 | temp | 1); | |
199 | dev_printk(KERN_NOTICE, &PIIX4_dev->dev, | |
200 | "WARNING: SMBus interface has been " | |
201 | "FORCEFULLY ENABLED!\n"); | |
202 | } else { | |
203 | dev_err(&PIIX4_dev->dev, | |
204 | "Host SMBus controller not enabled!\n"); | |
205 | release_region(piix4_smba, SMBIOSIZE); | |
206 | piix4_smba = 0; | |
207 | return -ENODEV; | |
208 | } | |
209 | } | |
210 | ||
54aaa1ca | 211 | if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) |
1da177e4 LT |
212 | dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n"); |
213 | else if ((temp & 0x0E) == 0) | |
214 | dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n"); | |
215 | else | |
216 | dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " | |
217 | "(or code out of date)!\n"); | |
218 | ||
219 | pci_read_config_byte(PIIX4_dev, SMBREV, &temp); | |
fa63cd56 JD |
220 | dev_info(&PIIX4_dev->dev, |
221 | "SMBus Host Controller at 0x%x, revision %d\n", | |
222 | piix4_smba, temp); | |
1da177e4 LT |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
1da177e4 LT |
227 | static int piix4_transaction(void) |
228 | { | |
229 | int temp; | |
230 | int result = 0; | |
231 | int timeout = 0; | |
232 | ||
233 | dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, " | |
234 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), | |
235 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
236 | inb_p(SMBHSTDAT1)); | |
237 | ||
238 | /* Make sure the SMBus host is ready to start transmitting */ | |
239 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
240 | dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). " | |
541e6a02 | 241 | "Resetting...\n", temp); |
1da177e4 LT |
242 | outb_p(temp, SMBHSTSTS); |
243 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
244 | dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp); | |
97140342 | 245 | return -EBUSY; |
1da177e4 | 246 | } else { |
c5d21b7f | 247 | dev_dbg(&piix4_adapter.dev, "Successful!\n"); |
1da177e4 LT |
248 | } |
249 | } | |
250 | ||
251 | /* start the transaction by setting bit 6 */ | |
252 | outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); | |
253 | ||
254 | /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ | |
b1c1759c DM |
255 | if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ |
256 | msleep(2); | |
257 | else | |
258 | msleep(1); | |
259 | ||
260 | while ((timeout++ < MAX_TIMEOUT) && | |
261 | ((temp = inb_p(SMBHSTSTS)) & 0x01)) | |
1da177e4 | 262 | msleep(1); |
1da177e4 LT |
263 | |
264 | /* If the SMBus is still busy, we give up */ | |
265 | if (timeout >= MAX_TIMEOUT) { | |
266 | dev_err(&piix4_adapter.dev, "SMBus Timeout!\n"); | |
97140342 | 267 | result = -ETIMEDOUT; |
1da177e4 LT |
268 | } |
269 | ||
270 | if (temp & 0x10) { | |
97140342 | 271 | result = -EIO; |
1da177e4 LT |
272 | dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n"); |
273 | } | |
274 | ||
275 | if (temp & 0x08) { | |
97140342 | 276 | result = -EIO; |
1da177e4 LT |
277 | dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be " |
278 | "locked until next hard reset. (sorry!)\n"); | |
279 | /* Clock stops and slave is stuck in mid-transmission */ | |
280 | } | |
281 | ||
282 | if (temp & 0x04) { | |
97140342 | 283 | result = -ENXIO; |
1da177e4 LT |
284 | dev_dbg(&piix4_adapter.dev, "Error: no response!\n"); |
285 | } | |
286 | ||
287 | if (inb_p(SMBHSTSTS) != 0x00) | |
288 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
289 | ||
290 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
291 | dev_err(&piix4_adapter.dev, "Failed reset at end of " | |
292 | "transaction (%02x)\n", temp); | |
293 | } | |
294 | dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, " | |
295 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), | |
296 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
297 | inb_p(SMBHSTDAT1)); | |
298 | return result; | |
299 | } | |
300 | ||
97140342 | 301 | /* Return negative errno on error. */ |
1da177e4 LT |
302 | static s32 piix4_access(struct i2c_adapter * adap, u16 addr, |
303 | unsigned short flags, char read_write, | |
304 | u8 command, int size, union i2c_smbus_data * data) | |
305 | { | |
306 | int i, len; | |
97140342 | 307 | int status; |
1da177e4 LT |
308 | |
309 | switch (size) { | |
310 | case I2C_SMBUS_PROC_CALL: | |
311 | dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n"); | |
97140342 | 312 | return -EOPNOTSUPP; |
1da177e4 | 313 | case I2C_SMBUS_QUICK: |
fa63cd56 | 314 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
315 | SMBHSTADD); |
316 | size = PIIX4_QUICK; | |
317 | break; | |
318 | case I2C_SMBUS_BYTE: | |
fa63cd56 | 319 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
320 | SMBHSTADD); |
321 | if (read_write == I2C_SMBUS_WRITE) | |
322 | outb_p(command, SMBHSTCMD); | |
323 | size = PIIX4_BYTE; | |
324 | break; | |
325 | case I2C_SMBUS_BYTE_DATA: | |
fa63cd56 | 326 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
327 | SMBHSTADD); |
328 | outb_p(command, SMBHSTCMD); | |
329 | if (read_write == I2C_SMBUS_WRITE) | |
330 | outb_p(data->byte, SMBHSTDAT0); | |
331 | size = PIIX4_BYTE_DATA; | |
332 | break; | |
333 | case I2C_SMBUS_WORD_DATA: | |
fa63cd56 | 334 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
335 | SMBHSTADD); |
336 | outb_p(command, SMBHSTCMD); | |
337 | if (read_write == I2C_SMBUS_WRITE) { | |
338 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
339 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
340 | } | |
341 | size = PIIX4_WORD_DATA; | |
342 | break; | |
343 | case I2C_SMBUS_BLOCK_DATA: | |
fa63cd56 | 344 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
345 | SMBHSTADD); |
346 | outb_p(command, SMBHSTCMD); | |
347 | if (read_write == I2C_SMBUS_WRITE) { | |
348 | len = data->block[0]; | |
fa63cd56 JD |
349 | if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) |
350 | return -EINVAL; | |
1da177e4 LT |
351 | outb_p(len, SMBHSTDAT0); |
352 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ | |
353 | for (i = 1; i <= len; i++) | |
354 | outb_p(data->block[i], SMBBLKDAT); | |
355 | } | |
356 | size = PIIX4_BLOCK_DATA; | |
357 | break; | |
358 | } | |
359 | ||
360 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | |
361 | ||
97140342 DB |
362 | status = piix4_transaction(); |
363 | if (status) | |
364 | return status; | |
1da177e4 LT |
365 | |
366 | if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) | |
367 | return 0; | |
368 | ||
369 | ||
370 | switch (size) { | |
3578a075 | 371 | case PIIX4_BYTE: |
1da177e4 LT |
372 | case PIIX4_BYTE_DATA: |
373 | data->byte = inb_p(SMBHSTDAT0); | |
374 | break; | |
375 | case PIIX4_WORD_DATA: | |
376 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
377 | break; | |
378 | case PIIX4_BLOCK_DATA: | |
379 | data->block[0] = inb_p(SMBHSTDAT0); | |
fa63cd56 JD |
380 | if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
381 | return -EPROTO; | |
1da177e4 LT |
382 | i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
383 | for (i = 1; i <= data->block[0]; i++) | |
384 | data->block[i] = inb_p(SMBBLKDAT); | |
385 | break; | |
386 | } | |
387 | return 0; | |
388 | } | |
389 | ||
390 | static u32 piix4_func(struct i2c_adapter *adapter) | |
391 | { | |
392 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
393 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
394 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
395 | } | |
396 | ||
8f9082c5 | 397 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
398 | .smbus_xfer = piix4_access, |
399 | .functionality = piix4_func, | |
400 | }; | |
401 | ||
402 | static struct i2c_adapter piix4_adapter = { | |
403 | .owner = THIS_MODULE, | |
9ace555d | 404 | .id = I2C_HW_SMBUS_PIIX4, |
1da177e4 LT |
405 | .class = I2C_CLASS_HWMON, |
406 | .algo = &smbus_algorithm, | |
1da177e4 LT |
407 | }; |
408 | ||
409 | static struct pci_device_id piix4_ids[] = { | |
9b7389c0 JD |
410 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, |
411 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, | |
412 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, | |
413 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, | |
414 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, | |
415 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, | |
416 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, | |
417 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
418 | PCI_DEVICE_ID_SERVERWORKS_OSB4) }, | |
419 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
420 | PCI_DEVICE_ID_SERVERWORKS_CSB5) }, | |
421 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
422 | PCI_DEVICE_ID_SERVERWORKS_CSB6) }, | |
423 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
424 | PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, | |
1da177e4 LT |
425 | { 0, } |
426 | }; | |
427 | ||
428 | MODULE_DEVICE_TABLE (pci, piix4_ids); | |
429 | ||
430 | static int __devinit piix4_probe(struct pci_dev *dev, | |
431 | const struct pci_device_id *id) | |
432 | { | |
433 | int retval; | |
434 | ||
435 | retval = piix4_setup(dev, id); | |
436 | if (retval) | |
437 | return retval; | |
438 | ||
405ae7d3 | 439 | /* set up the sysfs linkage to our parent device */ |
1da177e4 LT |
440 | piix4_adapter.dev.parent = &dev->dev; |
441 | ||
2096b956 | 442 | snprintf(piix4_adapter.name, sizeof(piix4_adapter.name), |
1da177e4 LT |
443 | "SMBus PIIX4 adapter at %04x", piix4_smba); |
444 | ||
445 | if ((retval = i2c_add_adapter(&piix4_adapter))) { | |
446 | dev_err(&dev->dev, "Couldn't register adapter!\n"); | |
447 | release_region(piix4_smba, SMBIOSIZE); | |
448 | piix4_smba = 0; | |
449 | } | |
450 | ||
451 | return retval; | |
452 | } | |
453 | ||
454 | static void __devexit piix4_remove(struct pci_dev *dev) | |
455 | { | |
456 | if (piix4_smba) { | |
457 | i2c_del_adapter(&piix4_adapter); | |
458 | release_region(piix4_smba, SMBIOSIZE); | |
459 | piix4_smba = 0; | |
460 | } | |
461 | } | |
462 | ||
463 | static struct pci_driver piix4_driver = { | |
464 | .name = "piix4_smbus", | |
465 | .id_table = piix4_ids, | |
466 | .probe = piix4_probe, | |
467 | .remove = __devexit_p(piix4_remove), | |
468 | }; | |
469 | ||
470 | static int __init i2c_piix4_init(void) | |
471 | { | |
472 | return pci_register_driver(&piix4_driver); | |
473 | } | |
474 | ||
475 | static void __exit i2c_piix4_exit(void) | |
476 | { | |
477 | pci_unregister_driver(&piix4_driver); | |
478 | } | |
479 | ||
480 | MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " | |
481 | "Philip Edelbrock <phil@netroedge.com>"); | |
482 | MODULE_DESCRIPTION("PIIX4 SMBus driver"); | |
483 | MODULE_LICENSE("GPL"); | |
484 | ||
485 | module_init(i2c_piix4_init); | |
486 | module_exit(i2c_piix4_exit); |