Commit | Line | Data |
---|---|---|
b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
3ad2f3fb | 15 | * Jun 2002: Properly separated algo/adap [FB] |
b652b438 RK |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
b652b438 RK |
25 | #include <linux/init.h> |
26 | #include <linux/time.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/i2c-pxa.h> | |
baa8cab0 | 32 | #include <linux/of_i2c.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
21782180 | 37 | #include <linux/io.h> |
b459396e | 38 | #include <linux/i2c/pxa-i2c.h> |
b652b438 | 39 | |
b652b438 | 40 | #include <asm/irq.h> |
283afa06 | 41 | |
7e94dd15 SAS |
42 | #ifndef CONFIG_HAVE_CLK |
43 | #define clk_get(dev, id) NULL | |
44 | #define clk_put(clk) do { } while (0) | |
45 | #define clk_disable(clk) do { } while (0) | |
46 | #define clk_enable(clk) do { } while (0) | |
47 | #endif | |
48 | ||
d6668c7c SAS |
49 | struct pxa_reg_layout { |
50 | u32 ibmr; | |
51 | u32 idbr; | |
52 | u32 icr; | |
53 | u32 isr; | |
54 | u32 isar; | |
55 | }; | |
56 | ||
57 | enum pxa_i2c_types { | |
58 | REGS_PXA2XX, | |
59 | REGS_PXA3XX, | |
7e94dd15 | 60 | REGS_CE4100, |
d6668c7c SAS |
61 | }; |
62 | ||
f23d4911 | 63 | /* |
d6668c7c | 64 | * I2C registers definitions |
f23d4911 | 65 | */ |
d6668c7c SAS |
66 | static struct pxa_reg_layout pxa_reg_layout[] = { |
67 | [REGS_PXA2XX] = { | |
d6668c7c SAS |
68 | .ibmr = 0x00, |
69 | .idbr = 0x08, | |
70 | .icr = 0x10, | |
71 | .isr = 0x18, | |
72 | .isar = 0x20, | |
73 | }, | |
23e74a86 VK |
74 | [REGS_PXA3XX] = { |
75 | .ibmr = 0x00, | |
76 | .idbr = 0x04, | |
77 | .icr = 0x08, | |
78 | .isr = 0x0c, | |
79 | .isar = 0x10, | |
80 | }, | |
7e94dd15 SAS |
81 | [REGS_CE4100] = { |
82 | .ibmr = 0x14, | |
83 | .idbr = 0x0c, | |
84 | .icr = 0x00, | |
85 | .isr = 0x04, | |
86 | /* no isar register */ | |
87 | }, | |
d6668c7c | 88 | }; |
f23d4911 EM |
89 | |
90 | static const struct platform_device_id i2c_pxa_id_table[] = { | |
d6668c7c SAS |
91 | { "pxa2xx-i2c", REGS_PXA2XX }, |
92 | { "pxa3xx-pwri2c", REGS_PXA3XX }, | |
7e94dd15 | 93 | { "ce4100-i2c", REGS_CE4100 }, |
f23d4911 EM |
94 | { }, |
95 | }; | |
96 | MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); | |
97 | ||
283afa06 | 98 | /* |
d6668c7c | 99 | * I2C bit definitions |
283afa06 | 100 | */ |
283afa06 EM |
101 | |
102 | #define ICR_START (1 << 0) /* start bit */ | |
103 | #define ICR_STOP (1 << 1) /* stop bit */ | |
104 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | |
105 | #define ICR_TB (1 << 3) /* transfer byte bit */ | |
106 | #define ICR_MA (1 << 4) /* master abort */ | |
107 | #define ICR_SCLE (1 << 5) /* master clock enable */ | |
108 | #define ICR_IUE (1 << 6) /* unit enable */ | |
109 | #define ICR_GCD (1 << 7) /* general call disable */ | |
110 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | |
111 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | |
112 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | |
113 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | |
114 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | |
115 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | |
116 | #define ICR_UR (1 << 14) /* unit reset */ | |
117 | #define ICR_FM (1 << 15) /* fast mode */ | |
118 | ||
119 | #define ISR_RWM (1 << 0) /* read/write mode */ | |
120 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | |
121 | #define ISR_UB (1 << 2) /* unit busy */ | |
122 | #define ISR_IBB (1 << 3) /* bus busy */ | |
123 | #define ISR_SSD (1 << 4) /* slave stop detected */ | |
124 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | |
125 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | |
126 | #define ISR_IRF (1 << 7) /* rx buffer full */ | |
127 | #define ISR_GCAD (1 << 8) /* general call address detected */ | |
128 | #define ISR_SAD (1 << 9) /* slave address detected */ | |
129 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | |
b652b438 RK |
130 | |
131 | struct pxa_i2c { | |
132 | spinlock_t lock; | |
133 | wait_queue_head_t wait; | |
134 | struct i2c_msg *msg; | |
135 | unsigned int msg_num; | |
136 | unsigned int msg_idx; | |
137 | unsigned int msg_ptr; | |
138 | unsigned int slave_addr; | |
139 | ||
140 | struct i2c_adapter adap; | |
c3cef3f3 | 141 | struct clk *clk; |
b652b438 RK |
142 | #ifdef CONFIG_I2C_PXA_SLAVE |
143 | struct i2c_slave_client *slave; | |
144 | #endif | |
145 | ||
146 | unsigned int irqlogidx; | |
147 | u32 isrlog[32]; | |
148 | u32 icrlog[32]; | |
a7b4e550 GL |
149 | |
150 | void __iomem *reg_base; | |
d6668c7c SAS |
151 | void __iomem *reg_ibmr; |
152 | void __iomem *reg_idbr; | |
153 | void __iomem *reg_icr; | |
154 | void __iomem *reg_isr; | |
155 | void __iomem *reg_isar; | |
a7b4e550 GL |
156 | |
157 | unsigned long iobase; | |
158 | unsigned long iosize; | |
159 | ||
160 | int irq; | |
c46c9482 JC |
161 | unsigned int use_pio :1; |
162 | unsigned int fast_mode :1; | |
b652b438 RK |
163 | }; |
164 | ||
d6668c7c SAS |
165 | #define _IBMR(i2c) ((i2c)->reg_ibmr) |
166 | #define _IDBR(i2c) ((i2c)->reg_idbr) | |
167 | #define _ICR(i2c) ((i2c)->reg_icr) | |
168 | #define _ISR(i2c) ((i2c)->reg_isr) | |
169 | #define _ISAR(i2c) ((i2c)->reg_isar) | |
a7b4e550 | 170 | |
b652b438 RK |
171 | /* |
172 | * I2C Slave mode address | |
173 | */ | |
174 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
175 | ||
b652b438 RK |
176 | #ifdef DEBUG |
177 | ||
178 | struct bits { | |
179 | u32 mask; | |
180 | const char *set; | |
181 | const char *unset; | |
182 | }; | |
ed11399d | 183 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
184 | |
185 | static inline void | |
186 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
187 | { | |
188 | printk("%s %08x: ", prefix, val); | |
189 | while (num--) { | |
190 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
191 | if (str) | |
192 | printk("%s ", str); | |
193 | bits++; | |
194 | } | |
195 | } | |
196 | ||
197 | static const struct bits isr_bits[] = { | |
ed11399d JS |
198 | PXA_BIT(ISR_RWM, "RX", "TX"), |
199 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
200 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
201 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
202 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
203 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
204 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
205 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
206 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
207 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
208 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
209 | }; |
210 | ||
211 | static void decode_ISR(unsigned int val) | |
212 | { | |
6fd60fa9 | 213 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
214 | printk("\n"); |
215 | } | |
216 | ||
217 | static const struct bits icr_bits[] = { | |
ed11399d JS |
218 | PXA_BIT(ICR_START, "START", NULL), |
219 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
220 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
221 | PXA_BIT(ICR_TB, "TB", NULL), | |
222 | PXA_BIT(ICR_MA, "MA", NULL), | |
223 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
224 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
225 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
226 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
227 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
228 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
229 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
230 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
231 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
232 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
233 | }; |
234 | ||
d6a7b5f8 | 235 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 RK |
236 | static void decode_ICR(unsigned int val) |
237 | { | |
6fd60fa9 | 238 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
239 | printk("\n"); |
240 | } | |
d6a7b5f8 | 241 | #endif |
b652b438 RK |
242 | |
243 | static unsigned int i2c_debug = DEBUG; | |
244 | ||
245 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
246 | { | |
a7b4e550 GL |
247 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
248 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
249 | } |
250 | ||
08882d20 | 251 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
b652b438 RK |
252 | |
253 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
254 | { | |
255 | unsigned int i; | |
154d22b0 FS |
256 | printk(KERN_ERR "i2c: error: %s\n", why); |
257 | printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
b652b438 | 258 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); |
154d22b0 FS |
259 | printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n", |
260 | readl(_ICR(i2c)), readl(_ISR(i2c))); | |
261 | printk(KERN_DEBUG "i2c: log: "); | |
b652b438 RK |
262 | for (i = 0; i < i2c->irqlogidx; i++) |
263 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
264 | printk("\n"); | |
265 | } | |
266 | ||
0d813d99 WS |
267 | #else /* ifdef DEBUG */ |
268 | ||
269 | #define i2c_debug 0 | |
270 | ||
271 | #define show_state(i2c) do { } while (0) | |
272 | #define decode_ISR(val) do { } while (0) | |
273 | #define decode_ICR(val) do { } while (0) | |
274 | #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) | |
275 | ||
276 | #endif /* ifdef DEBUG / else */ | |
277 | ||
278 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
279 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); | |
280 | ||
b652b438 RK |
281 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) |
282 | { | |
a7b4e550 | 283 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
284 | } |
285 | ||
286 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
287 | { | |
387fa6a5 | 288 | int i = 250; |
b652b438 RK |
289 | |
290 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 291 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
292 | return; |
293 | } | |
294 | ||
387fa6a5 | 295 | while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
a7b4e550 | 296 | unsigned long icr = readl(_ICR(i2c)); |
b652b438 RK |
297 | |
298 | icr &= ~ICR_START; | |
299 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
300 | ||
a7b4e550 | 301 | writel(icr, _ICR(i2c)); |
b652b438 RK |
302 | |
303 | show_state(i2c); | |
304 | ||
387fa6a5 DB |
305 | mdelay(1); |
306 | i --; | |
b652b438 RK |
307 | } |
308 | ||
a7b4e550 GL |
309 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
310 | _ICR(i2c)); | |
b652b438 RK |
311 | } |
312 | ||
313 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
314 | { | |
315 | int timeout = DEF_TIMEOUT; | |
316 | ||
a7b4e550 GL |
317 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
318 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
319 | timeout += 4; |
320 | ||
321 | msleep(2); | |
322 | show_state(i2c); | |
323 | } | |
324 | ||
d10db3a0 | 325 | if (timeout < 0) |
b652b438 RK |
326 | show_state(i2c); |
327 | ||
d10db3a0 | 328 | return timeout < 0 ? I2C_RETRY : 0; |
b652b438 RK |
329 | } |
330 | ||
331 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
332 | { | |
333 | unsigned long timeout = jiffies + HZ*4; | |
334 | ||
335 | while (time_before(jiffies, timeout)) { | |
336 | if (i2c_debug > 1) | |
6fd60fa9 | 337 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 338 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 339 | |
a7b4e550 | 340 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 341 | if (i2c_debug > 0) |
6fd60fa9 | 342 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
343 | goto out; |
344 | } | |
345 | ||
346 | /* wait for unit and bus being not busy, and we also do a | |
347 | * quick check of the i2c lines themselves to ensure they've | |
348 | * gone high... | |
349 | */ | |
a7b4e550 | 350 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 351 | if (i2c_debug > 0) |
6fd60fa9 | 352 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
353 | return 1; |
354 | } | |
355 | ||
356 | msleep(1); | |
357 | } | |
358 | ||
359 | if (i2c_debug > 0) | |
6fd60fa9 | 360 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
361 | out: |
362 | return 0; | |
363 | } | |
364 | ||
365 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
366 | { | |
367 | if (i2c_debug) | |
6fd60fa9 | 368 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 369 | |
a7b4e550 | 370 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 371 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 372 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 373 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
374 | return I2C_RETRY; |
375 | } | |
376 | } | |
377 | ||
a7b4e550 | 378 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
379 | return 0; |
380 | } | |
381 | ||
382 | #ifdef CONFIG_I2C_PXA_SLAVE | |
383 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
384 | { | |
385 | unsigned long timeout = jiffies + HZ*1; | |
386 | ||
387 | /* wait for stop */ | |
388 | ||
389 | show_state(i2c); | |
390 | ||
391 | while (time_before(jiffies, timeout)) { | |
392 | if (i2c_debug > 1) | |
6fd60fa9 | 393 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 394 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 395 | |
a7b4e550 GL |
396 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
397 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
398 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 399 | if (i2c_debug > 1) |
6fd60fa9 | 400 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
401 | return 1; |
402 | } | |
403 | ||
404 | msleep(1); | |
405 | } | |
406 | ||
407 | if (i2c_debug > 0) | |
6fd60fa9 | 408 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
409 | return 0; |
410 | } | |
411 | ||
412 | /* | |
413 | * clear the hold on the bus, and take of anything else | |
414 | * that has been configured | |
415 | */ | |
416 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
417 | { | |
418 | show_state(i2c); | |
419 | ||
420 | if (errcode < 0) { | |
421 | udelay(100); /* simple delay */ | |
422 | } else { | |
423 | /* we need to wait for the stop condition to end */ | |
424 | ||
425 | /* if we where in stop, then clear... */ | |
a7b4e550 | 426 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 427 | udelay(100); |
a7b4e550 | 428 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
429 | } |
430 | ||
431 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
432 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
433 | __func__); | |
b652b438 RK |
434 | return; |
435 | } | |
436 | } | |
437 | ||
a7b4e550 GL |
438 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
439 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
440 | |
441 | if (i2c_debug) { | |
a7b4e550 GL |
442 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
443 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
444 | } |
445 | } | |
446 | #else | |
447 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
448 | #endif | |
449 | ||
450 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
451 | { | |
452 | pr_debug("Resetting I2C Controller Unit\n"); | |
453 | ||
454 | /* abort any transfer currently under way */ | |
455 | i2c_pxa_abort(i2c); | |
456 | ||
457 | /* reset according to 9.8 */ | |
a7b4e550 GL |
458 | writel(ICR_UR, _ICR(i2c)); |
459 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
460 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 461 | |
7e94dd15 SAS |
462 | if (i2c->reg_isar) |
463 | writel(i2c->slave_addr, _ISAR(i2c)); | |
b652b438 RK |
464 | |
465 | /* set control register values */ | |
c46c9482 | 466 | writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); |
b652b438 RK |
467 | |
468 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 469 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 470 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
471 | #endif |
472 | ||
473 | i2c_pxa_set_slave(i2c, 0); | |
474 | ||
475 | /* enable unit */ | |
a7b4e550 | 476 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
477 | udelay(100); |
478 | } | |
479 | ||
480 | ||
481 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
482 | /* |
483 | * PXA I2C Slave mode | |
484 | */ | |
485 | ||
486 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
487 | { | |
488 | if (isr & ISR_BED) { | |
489 | /* what should we do here? */ | |
490 | } else { | |
84b5abe6 RK |
491 | int ret = 0; |
492 | ||
493 | if (i2c->slave != NULL) | |
494 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 495 | |
a7b4e550 GL |
496 | writel(ret, _IDBR(i2c)); |
497 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
498 | } |
499 | } | |
500 | ||
501 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
502 | { | |
a7b4e550 | 503 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
504 | |
505 | if (i2c->slave != NULL) | |
506 | i2c->slave->write(i2c->slave->data, byte); | |
507 | ||
a7b4e550 | 508 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
509 | } |
510 | ||
511 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
512 | { | |
513 | int timeout; | |
514 | ||
515 | if (i2c_debug > 0) | |
6fd60fa9 | 516 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
517 | (isr & ISR_RWM) ? 'r' : 't'); |
518 | ||
519 | if (i2c->slave != NULL) | |
520 | i2c->slave->event(i2c->slave->data, | |
521 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
522 | ||
523 | /* | |
524 | * slave could interrupt in the middle of us generating a | |
525 | * start condition... if this happens, we'd better back off | |
526 | * and stop holding the poor thing up | |
527 | */ | |
a7b4e550 GL |
528 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
529 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
530 | |
531 | timeout = 0x10000; | |
532 | ||
533 | while (1) { | |
a7b4e550 | 534 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
535 | break; |
536 | ||
537 | timeout--; | |
538 | ||
539 | if (timeout <= 0) { | |
6fd60fa9 | 540 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
541 | break; |
542 | } | |
543 | } | |
544 | ||
a7b4e550 | 545 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
546 | } |
547 | ||
548 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
549 | { | |
550 | if (i2c_debug > 2) | |
6fd60fa9 | 551 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
552 | |
553 | if (i2c->slave != NULL) | |
554 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
555 | ||
556 | if (i2c_debug > 2) | |
6fd60fa9 | 557 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
558 | |
559 | /* | |
560 | * If we have a master-mode message waiting, | |
561 | * kick it off now that the slave has completed. | |
562 | */ | |
563 | if (i2c->msg) | |
564 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
565 | } | |
566 | #else | |
567 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
568 | { | |
569 | if (isr & ISR_BED) { | |
570 | /* what should we do here? */ | |
571 | } else { | |
a7b4e550 GL |
572 | writel(0, _IDBR(i2c)); |
573 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
574 | } |
575 | } | |
576 | ||
577 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
578 | { | |
a7b4e550 | 579 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
580 | } |
581 | ||
582 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
583 | { | |
584 | int timeout; | |
585 | ||
586 | /* | |
587 | * slave could interrupt in the middle of us generating a | |
588 | * start condition... if this happens, we'd better back off | |
589 | * and stop holding the poor thing up | |
590 | */ | |
a7b4e550 GL |
591 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
592 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
593 | |
594 | timeout = 0x10000; | |
595 | ||
596 | while (1) { | |
a7b4e550 | 597 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
598 | break; |
599 | ||
600 | timeout--; | |
601 | ||
602 | if (timeout <= 0) { | |
6fd60fa9 | 603 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
604 | break; |
605 | } | |
606 | } | |
607 | ||
a7b4e550 | 608 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
609 | } |
610 | ||
611 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
612 | { | |
613 | if (i2c->msg) | |
614 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
615 | } | |
616 | #endif | |
617 | ||
618 | /* | |
619 | * PXA I2C Master mode | |
620 | */ | |
621 | ||
622 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
623 | { | |
624 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
625 | ||
626 | if (msg->flags & I2C_M_RD) | |
627 | addr |= 1; | |
628 | ||
629 | return addr; | |
630 | } | |
631 | ||
632 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
633 | { | |
634 | u32 icr; | |
635 | ||
636 | /* | |
637 | * Step 1: target slave address into IDBR | |
638 | */ | |
a7b4e550 | 639 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
640 | |
641 | /* | |
642 | * Step 2: initiate the write. | |
643 | */ | |
a7b4e550 GL |
644 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
645 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
646 | } |
647 | ||
7d054817 JD |
648 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
649 | { | |
650 | u32 icr; | |
651 | ||
652 | /* | |
653 | * Clear the STOP and ACK flags | |
654 | */ | |
655 | icr = readl(_ICR(i2c)); | |
656 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 657 | writel(icr, _ICR(i2c)); |
7d054817 JD |
658 | } |
659 | ||
b7a36701 MR |
660 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
661 | { | |
662 | /* make timeout the same as for interrupt based functions */ | |
663 | long timeout = 2 * DEF_TIMEOUT; | |
664 | ||
665 | /* | |
666 | * Wait for the bus to become free. | |
667 | */ | |
668 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
669 | udelay(1000); | |
670 | show_state(i2c); | |
671 | } | |
672 | ||
d10db3a0 | 673 | if (timeout < 0) { |
b7a36701 MR |
674 | show_state(i2c); |
675 | dev_err(&i2c->adap.dev, | |
676 | "i2c_pxa: timeout waiting for bus free\n"); | |
677 | return I2C_RETRY; | |
678 | } | |
679 | ||
680 | /* | |
681 | * Set master mode. | |
682 | */ | |
683 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
689 | struct i2c_msg *msg, int num) | |
690 | { | |
691 | unsigned long timeout = 500000; /* 5 seconds */ | |
692 | int ret = 0; | |
693 | ||
694 | ret = i2c_pxa_pio_set_master(i2c); | |
695 | if (ret) | |
696 | goto out; | |
697 | ||
698 | i2c->msg = msg; | |
699 | i2c->msg_num = num; | |
700 | i2c->msg_idx = 0; | |
701 | i2c->msg_ptr = 0; | |
702 | i2c->irqlogidx = 0; | |
703 | ||
704 | i2c_pxa_start_message(i2c); | |
705 | ||
a746b578 | 706 | while (i2c->msg_num > 0 && --timeout) { |
b7a36701 MR |
707 | i2c_pxa_handler(0, i2c); |
708 | udelay(10); | |
709 | } | |
710 | ||
711 | i2c_pxa_stop_message(i2c); | |
712 | ||
713 | /* | |
714 | * We place the return code in i2c->msg_idx. | |
715 | */ | |
716 | ret = i2c->msg_idx; | |
717 | ||
718 | out: | |
719 | if (timeout == 0) | |
720 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
721 | ||
722 | return ret; | |
723 | } | |
724 | ||
b652b438 | 725 | /* |
3fb9a655 | 726 | * We are protected by the adapter bus mutex. |
b652b438 RK |
727 | */ |
728 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
729 | { | |
730 | long timeout; | |
731 | int ret; | |
732 | ||
733 | /* | |
734 | * Wait for the bus to become free. | |
735 | */ | |
736 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
737 | if (ret) { | |
6fd60fa9 | 738 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
739 | goto out; |
740 | } | |
741 | ||
742 | /* | |
743 | * Set master mode. | |
744 | */ | |
745 | ret = i2c_pxa_set_master(i2c); | |
746 | if (ret) { | |
6fd60fa9 | 747 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
748 | goto out; |
749 | } | |
750 | ||
751 | spin_lock_irq(&i2c->lock); | |
752 | ||
753 | i2c->msg = msg; | |
754 | i2c->msg_num = num; | |
755 | i2c->msg_idx = 0; | |
756 | i2c->msg_ptr = 0; | |
757 | i2c->irqlogidx = 0; | |
758 | ||
759 | i2c_pxa_start_message(i2c); | |
760 | ||
761 | spin_unlock_irq(&i2c->lock); | |
762 | ||
763 | /* | |
764 | * The rest of the processing occurs in the interrupt handler. | |
765 | */ | |
766 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 767 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
768 | |
769 | /* | |
770 | * We place the return code in i2c->msg_idx. | |
771 | */ | |
772 | ret = i2c->msg_idx; | |
773 | ||
93c92cfd | 774 | if (!timeout && i2c->msg_num) { |
b652b438 | 775 | i2c_pxa_scream_blue_murder(i2c, "timeout"); |
93c92cfd SAS |
776 | ret = I2C_RETRY; |
777 | } | |
b652b438 RK |
778 | |
779 | out: | |
780 | return ret; | |
781 | } | |
782 | ||
b7a36701 MR |
783 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
784 | struct i2c_msg msgs[], int num) | |
785 | { | |
786 | struct pxa_i2c *i2c = adap->algo_data; | |
787 | int ret, i; | |
788 | ||
789 | /* If the I2C controller is disabled we need to reset it | |
790 | (probably due to a suspend/resume destroying state). We do | |
791 | this here as we can then avoid worrying about resuming the | |
792 | controller before its users. */ | |
793 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
794 | i2c_pxa_reset(i2c); | |
795 | ||
796 | for (i = adap->retries; i >= 0; i--) { | |
797 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
798 | if (ret != I2C_RETRY) | |
799 | goto out; | |
800 | ||
801 | if (i2c_debug) | |
802 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
803 | udelay(100); | |
804 | } | |
805 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
806 | ret = -EREMOTEIO; | |
807 | out: | |
808 | i2c_pxa_set_slave(i2c, ret); | |
809 | return ret; | |
810 | } | |
811 | ||
b652b438 RK |
812 | /* |
813 | * i2c_pxa_master_complete - complete the message and wake up. | |
814 | */ | |
815 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
816 | { | |
817 | i2c->msg_ptr = 0; | |
818 | i2c->msg = NULL; | |
819 | i2c->msg_idx ++; | |
820 | i2c->msg_num = 0; | |
821 | if (ret) | |
822 | i2c->msg_idx = ret; | |
b7a36701 MR |
823 | if (!i2c->use_pio) |
824 | wake_up(&i2c->wait); | |
b652b438 RK |
825 | } |
826 | ||
827 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
828 | { | |
a7b4e550 | 829 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
830 | |
831 | again: | |
832 | /* | |
833 | * If ISR_ALD is set, we lost arbitration. | |
834 | */ | |
835 | if (isr & ISR_ALD) { | |
836 | /* | |
837 | * Do we need to do anything here? The PXA docs | |
838 | * are vague about what happens. | |
839 | */ | |
840 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
841 | ||
842 | /* | |
843 | * We ignore this error. We seem to see spurious ALDs | |
844 | * for seemingly no reason. If we handle them as I think | |
845 | * they should, we end up causing an I2C error, which | |
846 | * is painful for some systems. | |
847 | */ | |
848 | return; /* ignore */ | |
849 | } | |
850 | ||
851 | if (isr & ISR_BED) { | |
852 | int ret = BUS_ERROR; | |
853 | ||
854 | /* | |
855 | * I2C bus error - either the device NAK'd us, or | |
856 | * something more serious happened. If we were NAK'd | |
857 | * on the initial address phase, we can retry. | |
858 | */ | |
859 | if (isr & ISR_ACKNAK) { | |
860 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
861 | ret = I2C_RETRY; | |
862 | else | |
863 | ret = XFER_NAKED; | |
864 | } | |
865 | i2c_pxa_master_complete(i2c, ret); | |
866 | } else if (isr & ISR_RWM) { | |
867 | /* | |
868 | * Read mode. We have just sent the address byte, and | |
869 | * now we must initiate the transfer. | |
870 | */ | |
871 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
872 | i2c->msg_idx == i2c->msg_num - 1) | |
873 | icr |= ICR_STOP | ICR_ACKNAK; | |
874 | ||
875 | icr |= ICR_ALDIE | ICR_TB; | |
876 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
877 | /* | |
878 | * Write mode. Write the next data byte. | |
879 | */ | |
a7b4e550 | 880 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
881 | |
882 | icr |= ICR_ALDIE | ICR_TB; | |
883 | ||
884 | /* | |
885 | * If this is the last byte of the last message, send | |
886 | * a STOP. | |
887 | */ | |
888 | if (i2c->msg_ptr == i2c->msg->len && | |
889 | i2c->msg_idx == i2c->msg_num - 1) | |
890 | icr |= ICR_STOP; | |
891 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
892 | /* | |
893 | * Next segment of the message. | |
894 | */ | |
895 | i2c->msg_ptr = 0; | |
896 | i2c->msg_idx ++; | |
897 | i2c->msg++; | |
898 | ||
899 | /* | |
900 | * If we aren't doing a repeated start and address, | |
901 | * go back and try to send the next byte. Note that | |
902 | * we do not support switching the R/W direction here. | |
903 | */ | |
904 | if (i2c->msg->flags & I2C_M_NOSTART) | |
905 | goto again; | |
906 | ||
907 | /* | |
908 | * Write the next address. | |
909 | */ | |
a7b4e550 | 910 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
911 | |
912 | /* | |
913 | * And trigger a repeated start, and send the byte. | |
914 | */ | |
915 | icr &= ~ICR_ALDIE; | |
916 | icr |= ICR_START | ICR_TB; | |
917 | } else { | |
918 | if (i2c->msg->len == 0) { | |
919 | /* | |
920 | * Device probes have a message length of zero | |
921 | * and need the bus to be reset before it can | |
922 | * be used again. | |
923 | */ | |
924 | i2c_pxa_reset(i2c); | |
925 | } | |
926 | i2c_pxa_master_complete(i2c, 0); | |
927 | } | |
928 | ||
929 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
930 | ||
a7b4e550 | 931 | writel(icr, _ICR(i2c)); |
b652b438 RK |
932 | show_state(i2c); |
933 | } | |
934 | ||
935 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
936 | { | |
a7b4e550 | 937 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
938 | |
939 | /* | |
940 | * Read the byte. | |
941 | */ | |
a7b4e550 | 942 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
943 | |
944 | if (i2c->msg_ptr < i2c->msg->len) { | |
945 | /* | |
946 | * If this is the last byte of the last | |
947 | * message, send a STOP. | |
948 | */ | |
949 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
950 | icr |= ICR_STOP | ICR_ACKNAK; | |
951 | ||
952 | icr |= ICR_ALDIE | ICR_TB; | |
953 | } else { | |
954 | i2c_pxa_master_complete(i2c, 0); | |
955 | } | |
956 | ||
957 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
958 | ||
a7b4e550 | 959 | writel(icr, _ICR(i2c)); |
b652b438 RK |
960 | } |
961 | ||
c66dc529 SAS |
962 | #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ |
963 | ISR_SAD | ISR_BED) | |
7d12e780 | 964 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
965 | { |
966 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 967 | u32 isr = readl(_ISR(i2c)); |
b652b438 | 968 | |
c66dc529 SAS |
969 | isr &= VALID_INT_SOURCE; |
970 | if (!isr) | |
971 | return IRQ_NONE; | |
972 | ||
b652b438 | 973 | if (i2c_debug > 2 && 0) { |
6fd60fa9 | 974 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 975 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
976 | decode_ISR(isr); |
977 | } | |
978 | ||
7e3d7db5 | 979 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
980 | i2c->isrlog[i2c->irqlogidx++] = isr; |
981 | ||
982 | show_state(i2c); | |
983 | ||
984 | /* | |
985 | * Always clear all pending IRQs. | |
986 | */ | |
c66dc529 | 987 | writel(isr, _ISR(i2c)); |
b652b438 RK |
988 | |
989 | if (isr & ISR_SAD) | |
990 | i2c_pxa_slave_start(i2c, isr); | |
991 | if (isr & ISR_SSD) | |
992 | i2c_pxa_slave_stop(i2c); | |
993 | ||
994 | if (i2c_pxa_is_slavemode(i2c)) { | |
995 | if (isr & ISR_ITE) | |
996 | i2c_pxa_slave_txempty(i2c, isr); | |
997 | if (isr & ISR_IRF) | |
998 | i2c_pxa_slave_rxfull(i2c, isr); | |
999 | } else if (i2c->msg) { | |
1000 | if (isr & ISR_ITE) | |
1001 | i2c_pxa_irq_txempty(i2c, isr); | |
1002 | if (isr & ISR_IRF) | |
1003 | i2c_pxa_irq_rxfull(i2c, isr); | |
1004 | } else { | |
1005 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
1006 | } | |
1007 | ||
1008 | return IRQ_HANDLED; | |
1009 | } | |
1010 | ||
1011 | ||
1012 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
1013 | { | |
1014 | struct pxa_i2c *i2c = adap->algo_data; | |
1015 | int ret, i; | |
1016 | ||
1017 | for (i = adap->retries; i >= 0; i--) { | |
1018 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
1019 | if (ret != I2C_RETRY) | |
1020 | goto out; | |
1021 | ||
1022 | if (i2c_debug) | |
6fd60fa9 | 1023 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
1024 | udelay(100); |
1025 | } | |
1026 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
1027 | ret = -EREMOTEIO; | |
1028 | out: | |
1029 | i2c_pxa_set_slave(i2c, ret); | |
1030 | return ret; | |
1031 | } | |
1032 | ||
da16e324 RK |
1033 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
1034 | { | |
1035 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
1036 | } | |
1037 | ||
8f9082c5 | 1038 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 1039 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 1040 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
1041 | }; |
1042 | ||
b7a36701 MR |
1043 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
1044 | .master_xfer = i2c_pxa_pio_xfer, | |
1045 | .functionality = i2c_pxa_functionality, | |
1046 | }; | |
1047 | ||
3ae5eaec | 1048 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 1049 | { |
6776f3d2 | 1050 | struct pxa_i2c *i2c; |
a7b4e550 | 1051 | struct resource *res; |
3ae5eaec | 1052 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
21e2ecfe | 1053 | const struct platform_device_id *id = platform_get_device_id(dev); |
d6668c7c | 1054 | enum pxa_i2c_types i2c_type = id->driver_data; |
b652b438 | 1055 | int ret; |
a7b4e550 | 1056 | int irq; |
b652b438 | 1057 | |
a7b4e550 GL |
1058 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1059 | irq = platform_get_irq(dev, 0); | |
1060 | if (res == NULL || irq < 0) | |
1061 | return -ENODEV; | |
1062 | ||
c6ffddea | 1063 | if (!request_mem_region(res->start, resource_size(res), res->name)) |
a7b4e550 GL |
1064 | return -ENOMEM; |
1065 | ||
6776f3d2 | 1066 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
1067 | if (!i2c) { |
1068 | ret = -ENOMEM; | |
1069 | goto emalloc; | |
1070 | } | |
1071 | ||
6776f3d2 | 1072 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
1073 | i2c->adap.retries = 5; |
1074 | ||
1075 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 1076 | init_waitqueue_head(&i2c->wait); |
6776f3d2 | 1077 | |
a92b36ed WS |
1078 | /* |
1079 | * If "dev->id" is negative we consider it as zero. | |
1080 | * The reason to do so is to avoid sysfs names that only make | |
1081 | * sense when there are multiple adapters. | |
1082 | */ | |
1083 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; | |
1084 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", | |
1085 | i2c->adap.nr); | |
a7b4e550 | 1086 | |
e0d8b13a | 1087 | i2c->clk = clk_get(&dev->dev, NULL); |
c3cef3f3 RK |
1088 | if (IS_ERR(i2c->clk)) { |
1089 | ret = PTR_ERR(i2c->clk); | |
1090 | goto eclk; | |
1091 | } | |
1092 | ||
c6ffddea | 1093 | i2c->reg_base = ioremap(res->start, resource_size(res)); |
a7b4e550 GL |
1094 | if (!i2c->reg_base) { |
1095 | ret = -EIO; | |
1096 | goto eremap; | |
1097 | } | |
d6668c7c SAS |
1098 | |
1099 | i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; | |
1100 | i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; | |
1101 | i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; | |
1102 | i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; | |
7e94dd15 SAS |
1103 | if (i2c_type != REGS_CE4100) |
1104 | i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; | |
a7b4e550 GL |
1105 | |
1106 | i2c->iobase = res->start; | |
c6ffddea | 1107 | i2c->iosize = resource_size(res); |
a7b4e550 GL |
1108 | |
1109 | i2c->irq = irq; | |
b652b438 RK |
1110 | |
1111 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1112 | ||
1113 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
1114 | if (plat) { |
1115 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 1116 | i2c->slave = plat->slave; |
b652b438 RK |
1117 | } |
1118 | #endif | |
1119 | ||
c3cef3f3 | 1120 | clk_enable(i2c->clk); |
a7b4e550 | 1121 | |
b7a36701 MR |
1122 | if (plat) { |
1123 | i2c->adap.class = plat->class; | |
1124 | i2c->use_pio = plat->use_pio; | |
c46c9482 | 1125 | i2c->fast_mode = plat->fast_mode; |
b7a36701 MR |
1126 | } |
1127 | ||
1128 | if (i2c->use_pio) { | |
1129 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1130 | } else { | |
1131 | i2c->adap.algo = &i2c_pxa_algorithm; | |
c66dc529 | 1132 | ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED, |
b7a36701 MR |
1133 | i2c->adap.name, i2c); |
1134 | if (ret) | |
1135 | goto ereqirq; | |
1136 | } | |
a7b4e550 | 1137 | |
b652b438 RK |
1138 | i2c_pxa_reset(i2c); |
1139 | ||
1140 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1141 | i2c->adap.dev.parent = &dev->dev; |
baa8cab0 SAS |
1142 | #ifdef CONFIG_OF |
1143 | i2c->adap.dev.of_node = dev->dev.of_node; | |
1144 | #endif | |
b652b438 | 1145 | |
7e94dd15 SAS |
1146 | if (i2c_type == REGS_CE4100) |
1147 | ret = i2c_add_adapter(&i2c->adap); | |
1148 | else | |
1149 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
b652b438 RK |
1150 | if (ret < 0) { |
1151 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1152 | goto eadapt; |
b652b438 | 1153 | } |
baa8cab0 | 1154 | of_i2c_register_devices(&i2c->adap); |
b652b438 | 1155 | |
3ae5eaec | 1156 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1157 | |
1158 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1159 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
22e965c2 | 1160 | dev_name(&i2c->adap.dev), i2c->slave_addr); |
b652b438 RK |
1161 | #else |
1162 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
22e965c2 | 1163 | dev_name(&i2c->adap.dev)); |
b652b438 RK |
1164 | #endif |
1165 | return 0; | |
1166 | ||
a7b4e550 | 1167 | eadapt: |
b7a36701 MR |
1168 | if (!i2c->use_pio) |
1169 | free_irq(irq, i2c); | |
a7b4e550 | 1170 | ereqirq: |
c3cef3f3 | 1171 | clk_disable(i2c->clk); |
a92b36ed | 1172 | iounmap(i2c->reg_base); |
a7b4e550 | 1173 | eremap: |
c3cef3f3 RK |
1174 | clk_put(i2c->clk); |
1175 | eclk: | |
a7b4e550 GL |
1176 | kfree(i2c); |
1177 | emalloc: | |
c6ffddea | 1178 | release_mem_region(res->start, resource_size(res)); |
b652b438 RK |
1179 | return ret; |
1180 | } | |
1181 | ||
a92b36ed | 1182 | static int __exit i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1183 | { |
3ae5eaec | 1184 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1185 | |
3ae5eaec | 1186 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
1187 | |
1188 | i2c_del_adapter(&i2c->adap); | |
b7a36701 MR |
1189 | if (!i2c->use_pio) |
1190 | free_irq(i2c->irq, i2c); | |
c3cef3f3 RK |
1191 | |
1192 | clk_disable(i2c->clk); | |
1193 | clk_put(i2c->clk); | |
c3cef3f3 | 1194 | |
a92b36ed | 1195 | iounmap(i2c->reg_base); |
a7b4e550 GL |
1196 | release_mem_region(i2c->iobase, i2c->iosize); |
1197 | kfree(i2c); | |
b652b438 RK |
1198 | |
1199 | return 0; | |
1200 | } | |
1201 | ||
e7d48fa2 | 1202 | #ifdef CONFIG_PM |
57f4d4f1 | 1203 | static int i2c_pxa_suspend_noirq(struct device *dev) |
e7d48fa2 | 1204 | { |
57f4d4f1 MD |
1205 | struct platform_device *pdev = to_platform_device(dev); |
1206 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
1207 | ||
e7d48fa2 | 1208 | clk_disable(i2c->clk); |
57f4d4f1 | 1209 | |
e7d48fa2 RK |
1210 | return 0; |
1211 | } | |
1212 | ||
57f4d4f1 | 1213 | static int i2c_pxa_resume_noirq(struct device *dev) |
e7d48fa2 | 1214 | { |
57f4d4f1 MD |
1215 | struct platform_device *pdev = to_platform_device(dev); |
1216 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
e7d48fa2 RK |
1217 | |
1218 | clk_enable(i2c->clk); | |
1219 | i2c_pxa_reset(i2c); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
57f4d4f1 | 1223 | |
47145210 | 1224 | static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { |
57f4d4f1 MD |
1225 | .suspend_noirq = i2c_pxa_suspend_noirq, |
1226 | .resume_noirq = i2c_pxa_resume_noirq, | |
1227 | }; | |
1228 | ||
1229 | #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) | |
e7d48fa2 | 1230 | #else |
57f4d4f1 | 1231 | #define I2C_PXA_DEV_PM_OPS NULL |
e7d48fa2 RK |
1232 | #endif |
1233 | ||
3ae5eaec | 1234 | static struct platform_driver i2c_pxa_driver = { |
b652b438 | 1235 | .probe = i2c_pxa_probe, |
a92b36ed | 1236 | .remove = __exit_p(i2c_pxa_remove), |
3ae5eaec RK |
1237 | .driver = { |
1238 | .name = "pxa2xx-i2c", | |
a92b36ed | 1239 | .owner = THIS_MODULE, |
57f4d4f1 | 1240 | .pm = I2C_PXA_DEV_PM_OPS, |
3ae5eaec | 1241 | }, |
f23d4911 | 1242 | .id_table = i2c_pxa_id_table, |
b652b438 RK |
1243 | }; |
1244 | ||
1245 | static int __init i2c_adap_pxa_init(void) | |
1246 | { | |
3ae5eaec | 1247 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1248 | } |
1249 | ||
a92b36ed | 1250 | static void __exit i2c_adap_pxa_exit(void) |
b652b438 | 1251 | { |
d6a7b5f8 | 1252 | platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1253 | } |
1254 | ||
ece5f7b3 | 1255 | MODULE_LICENSE("GPL"); |
add8eda7 | 1256 | MODULE_ALIAS("platform:pxa2xx-i2c"); |
ece5f7b3 | 1257 | |
47a9b137 | 1258 | subsys_initcall(i2c_adap_pxa_init); |
b652b438 | 1259 | module_exit(i2c_adap_pxa_exit); |