Commit | Line | Data |
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b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
15 | * Jun 2002: Properly seperated algo/adap [FB] | |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] | |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c-id.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/i2c-pxa.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
b652b438 RK |
36 | |
37 | #include <asm/hardware.h> | |
38 | #include <asm/irq.h> | |
a7b4e550 | 39 | #include <asm/io.h> |
b652b438 RK |
40 | #include <asm/arch/i2c.h> |
41 | #include <asm/arch/pxa-regs.h> | |
a683b14d | 42 | #include <asm/arch/pxa2xx-gpio.h> |
b652b438 RK |
43 | |
44 | struct pxa_i2c { | |
45 | spinlock_t lock; | |
46 | wait_queue_head_t wait; | |
47 | struct i2c_msg *msg; | |
48 | unsigned int msg_num; | |
49 | unsigned int msg_idx; | |
50 | unsigned int msg_ptr; | |
51 | unsigned int slave_addr; | |
52 | ||
53 | struct i2c_adapter adap; | |
c3cef3f3 | 54 | struct clk *clk; |
b652b438 RK |
55 | #ifdef CONFIG_I2C_PXA_SLAVE |
56 | struct i2c_slave_client *slave; | |
57 | #endif | |
58 | ||
59 | unsigned int irqlogidx; | |
60 | u32 isrlog[32]; | |
61 | u32 icrlog[32]; | |
a7b4e550 GL |
62 | |
63 | void __iomem *reg_base; | |
64 | ||
65 | unsigned long iobase; | |
66 | unsigned long iosize; | |
67 | ||
68 | int irq; | |
b7a36701 | 69 | int use_pio; |
b652b438 RK |
70 | }; |
71 | ||
a7b4e550 GL |
72 | #define _IBMR(i2c) ((i2c)->reg_base + 0) |
73 | #define _IDBR(i2c) ((i2c)->reg_base + 8) | |
74 | #define _ICR(i2c) ((i2c)->reg_base + 0x10) | |
75 | #define _ISR(i2c) ((i2c)->reg_base + 0x18) | |
76 | #define _ISAR(i2c) ((i2c)->reg_base + 0x20) | |
77 | ||
b652b438 RK |
78 | /* |
79 | * I2C Slave mode address | |
80 | */ | |
81 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
82 | ||
b652b438 RK |
83 | #ifdef DEBUG |
84 | ||
85 | struct bits { | |
86 | u32 mask; | |
87 | const char *set; | |
88 | const char *unset; | |
89 | }; | |
ed11399d | 90 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
91 | |
92 | static inline void | |
93 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
94 | { | |
95 | printk("%s %08x: ", prefix, val); | |
96 | while (num--) { | |
97 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
98 | if (str) | |
99 | printk("%s ", str); | |
100 | bits++; | |
101 | } | |
102 | } | |
103 | ||
104 | static const struct bits isr_bits[] = { | |
ed11399d JS |
105 | PXA_BIT(ISR_RWM, "RX", "TX"), |
106 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
107 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
108 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
109 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
110 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
111 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
112 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
113 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
114 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
115 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
116 | }; |
117 | ||
118 | static void decode_ISR(unsigned int val) | |
119 | { | |
6fd60fa9 | 120 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
121 | printk("\n"); |
122 | } | |
123 | ||
124 | static const struct bits icr_bits[] = { | |
ed11399d JS |
125 | PXA_BIT(ICR_START, "START", NULL), |
126 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
127 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
128 | PXA_BIT(ICR_TB, "TB", NULL), | |
129 | PXA_BIT(ICR_MA, "MA", NULL), | |
130 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
131 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
132 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
133 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
134 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
135 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
136 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
137 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
138 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
139 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
140 | }; |
141 | ||
d6a7b5f8 | 142 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 RK |
143 | static void decode_ICR(unsigned int val) |
144 | { | |
6fd60fa9 | 145 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
146 | printk("\n"); |
147 | } | |
d6a7b5f8 | 148 | #endif |
b652b438 RK |
149 | |
150 | static unsigned int i2c_debug = DEBUG; | |
151 | ||
152 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
153 | { | |
a7b4e550 GL |
154 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
155 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
156 | } |
157 | ||
08882d20 | 158 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
b652b438 RK |
159 | #else |
160 | #define i2c_debug 0 | |
161 | ||
162 | #define show_state(i2c) do { } while (0) | |
163 | #define decode_ISR(val) do { } while (0) | |
164 | #define decode_ICR(val) do { } while (0) | |
165 | #endif | |
166 | ||
6fd60fa9 | 167 | #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) |
b652b438 RK |
168 | |
169 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
b7a36701 | 170 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); |
b652b438 RK |
171 | |
172 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
173 | { | |
174 | unsigned int i; | |
175 | printk("i2c: error: %s\n", why); | |
176 | printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
177 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); | |
6fd60fa9 | 178 | printk("i2c: ICR: %08x ISR: %08x\n" |
a7b4e550 | 179 | "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c))); |
b652b438 RK |
180 | for (i = 0; i < i2c->irqlogidx; i++) |
181 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
182 | printk("\n"); | |
183 | } | |
184 | ||
185 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) | |
186 | { | |
a7b4e550 | 187 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
188 | } |
189 | ||
190 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
191 | { | |
192 | unsigned long timeout = jiffies + HZ/4; | |
193 | ||
194 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 195 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
196 | return; |
197 | } | |
198 | ||
a7b4e550 GL |
199 | while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
200 | unsigned long icr = readl(_ICR(i2c)); | |
b652b438 RK |
201 | |
202 | icr &= ~ICR_START; | |
203 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
204 | ||
a7b4e550 | 205 | writel(icr, _ICR(i2c)); |
b652b438 RK |
206 | |
207 | show_state(i2c); | |
208 | ||
209 | msleep(1); | |
210 | } | |
211 | ||
a7b4e550 GL |
212 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
213 | _ICR(i2c)); | |
b652b438 RK |
214 | } |
215 | ||
216 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
217 | { | |
218 | int timeout = DEF_TIMEOUT; | |
219 | ||
a7b4e550 GL |
220 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
221 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
222 | timeout += 4; |
223 | ||
224 | msleep(2); | |
225 | show_state(i2c); | |
226 | } | |
227 | ||
228 | if (timeout <= 0) | |
229 | show_state(i2c); | |
230 | ||
231 | return timeout <= 0 ? I2C_RETRY : 0; | |
232 | } | |
233 | ||
234 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
235 | { | |
236 | unsigned long timeout = jiffies + HZ*4; | |
237 | ||
238 | while (time_before(jiffies, timeout)) { | |
239 | if (i2c_debug > 1) | |
6fd60fa9 | 240 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 241 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 242 | |
a7b4e550 | 243 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 244 | if (i2c_debug > 0) |
6fd60fa9 | 245 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
246 | goto out; |
247 | } | |
248 | ||
249 | /* wait for unit and bus being not busy, and we also do a | |
250 | * quick check of the i2c lines themselves to ensure they've | |
251 | * gone high... | |
252 | */ | |
a7b4e550 | 253 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 254 | if (i2c_debug > 0) |
6fd60fa9 | 255 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
256 | return 1; |
257 | } | |
258 | ||
259 | msleep(1); | |
260 | } | |
261 | ||
262 | if (i2c_debug > 0) | |
6fd60fa9 | 263 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
264 | out: |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
269 | { | |
270 | if (i2c_debug) | |
6fd60fa9 | 271 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 272 | |
a7b4e550 | 273 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 274 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 275 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 276 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
277 | return I2C_RETRY; |
278 | } | |
279 | } | |
280 | ||
a7b4e550 | 281 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
282 | return 0; |
283 | } | |
284 | ||
285 | #ifdef CONFIG_I2C_PXA_SLAVE | |
286 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
287 | { | |
288 | unsigned long timeout = jiffies + HZ*1; | |
289 | ||
290 | /* wait for stop */ | |
291 | ||
292 | show_state(i2c); | |
293 | ||
294 | while (time_before(jiffies, timeout)) { | |
295 | if (i2c_debug > 1) | |
6fd60fa9 | 296 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 297 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 298 | |
a7b4e550 GL |
299 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
300 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
301 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 302 | if (i2c_debug > 1) |
6fd60fa9 | 303 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
304 | return 1; |
305 | } | |
306 | ||
307 | msleep(1); | |
308 | } | |
309 | ||
310 | if (i2c_debug > 0) | |
6fd60fa9 | 311 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
312 | return 0; |
313 | } | |
314 | ||
315 | /* | |
316 | * clear the hold on the bus, and take of anything else | |
317 | * that has been configured | |
318 | */ | |
319 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
320 | { | |
321 | show_state(i2c); | |
322 | ||
323 | if (errcode < 0) { | |
324 | udelay(100); /* simple delay */ | |
325 | } else { | |
326 | /* we need to wait for the stop condition to end */ | |
327 | ||
328 | /* if we where in stop, then clear... */ | |
a7b4e550 | 329 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 330 | udelay(100); |
a7b4e550 | 331 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
332 | } |
333 | ||
334 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
335 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
336 | __func__); | |
b652b438 RK |
337 | return; |
338 | } | |
339 | } | |
340 | ||
a7b4e550 GL |
341 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
342 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
343 | |
344 | if (i2c_debug) { | |
a7b4e550 GL |
345 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
346 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
347 | } |
348 | } | |
349 | #else | |
350 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
351 | #endif | |
352 | ||
353 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
354 | { | |
355 | pr_debug("Resetting I2C Controller Unit\n"); | |
356 | ||
357 | /* abort any transfer currently under way */ | |
358 | i2c_pxa_abort(i2c); | |
359 | ||
360 | /* reset according to 9.8 */ | |
a7b4e550 GL |
361 | writel(ICR_UR, _ICR(i2c)); |
362 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
363 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 364 | |
a7b4e550 | 365 | writel(i2c->slave_addr, _ISAR(i2c)); |
b652b438 RK |
366 | |
367 | /* set control register values */ | |
a7b4e550 | 368 | writel(I2C_ICR_INIT, _ICR(i2c)); |
b652b438 RK |
369 | |
370 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 371 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 372 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
373 | #endif |
374 | ||
375 | i2c_pxa_set_slave(i2c, 0); | |
376 | ||
377 | /* enable unit */ | |
a7b4e550 | 378 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
379 | udelay(100); |
380 | } | |
381 | ||
382 | ||
383 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
384 | /* |
385 | * PXA I2C Slave mode | |
386 | */ | |
387 | ||
388 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
389 | { | |
390 | if (isr & ISR_BED) { | |
391 | /* what should we do here? */ | |
392 | } else { | |
84b5abe6 RK |
393 | int ret = 0; |
394 | ||
395 | if (i2c->slave != NULL) | |
396 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 397 | |
a7b4e550 GL |
398 | writel(ret, _IDBR(i2c)); |
399 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
400 | } |
401 | } | |
402 | ||
403 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
404 | { | |
a7b4e550 | 405 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
406 | |
407 | if (i2c->slave != NULL) | |
408 | i2c->slave->write(i2c->slave->data, byte); | |
409 | ||
a7b4e550 | 410 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
411 | } |
412 | ||
413 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
414 | { | |
415 | int timeout; | |
416 | ||
417 | if (i2c_debug > 0) | |
6fd60fa9 | 418 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
419 | (isr & ISR_RWM) ? 'r' : 't'); |
420 | ||
421 | if (i2c->slave != NULL) | |
422 | i2c->slave->event(i2c->slave->data, | |
423 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
424 | ||
425 | /* | |
426 | * slave could interrupt in the middle of us generating a | |
427 | * start condition... if this happens, we'd better back off | |
428 | * and stop holding the poor thing up | |
429 | */ | |
a7b4e550 GL |
430 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
431 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
432 | |
433 | timeout = 0x10000; | |
434 | ||
435 | while (1) { | |
a7b4e550 | 436 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
437 | break; |
438 | ||
439 | timeout--; | |
440 | ||
441 | if (timeout <= 0) { | |
6fd60fa9 | 442 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
443 | break; |
444 | } | |
445 | } | |
446 | ||
a7b4e550 | 447 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
448 | } |
449 | ||
450 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
451 | { | |
452 | if (i2c_debug > 2) | |
6fd60fa9 | 453 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
454 | |
455 | if (i2c->slave != NULL) | |
456 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
457 | ||
458 | if (i2c_debug > 2) | |
6fd60fa9 | 459 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
460 | |
461 | /* | |
462 | * If we have a master-mode message waiting, | |
463 | * kick it off now that the slave has completed. | |
464 | */ | |
465 | if (i2c->msg) | |
466 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
467 | } | |
468 | #else | |
469 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
470 | { | |
471 | if (isr & ISR_BED) { | |
472 | /* what should we do here? */ | |
473 | } else { | |
a7b4e550 GL |
474 | writel(0, _IDBR(i2c)); |
475 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
476 | } |
477 | } | |
478 | ||
479 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
480 | { | |
a7b4e550 | 481 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
482 | } |
483 | ||
484 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
485 | { | |
486 | int timeout; | |
487 | ||
488 | /* | |
489 | * slave could interrupt in the middle of us generating a | |
490 | * start condition... if this happens, we'd better back off | |
491 | * and stop holding the poor thing up | |
492 | */ | |
a7b4e550 GL |
493 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
494 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
495 | |
496 | timeout = 0x10000; | |
497 | ||
498 | while (1) { | |
a7b4e550 | 499 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
500 | break; |
501 | ||
502 | timeout--; | |
503 | ||
504 | if (timeout <= 0) { | |
6fd60fa9 | 505 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
506 | break; |
507 | } | |
508 | } | |
509 | ||
a7b4e550 | 510 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
511 | } |
512 | ||
513 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
514 | { | |
515 | if (i2c->msg) | |
516 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
517 | } | |
518 | #endif | |
519 | ||
520 | /* | |
521 | * PXA I2C Master mode | |
522 | */ | |
523 | ||
524 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
525 | { | |
526 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
527 | ||
528 | if (msg->flags & I2C_M_RD) | |
529 | addr |= 1; | |
530 | ||
531 | return addr; | |
532 | } | |
533 | ||
534 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
535 | { | |
536 | u32 icr; | |
537 | ||
538 | /* | |
539 | * Step 1: target slave address into IDBR | |
540 | */ | |
a7b4e550 | 541 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
542 | |
543 | /* | |
544 | * Step 2: initiate the write. | |
545 | */ | |
a7b4e550 GL |
546 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
547 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
548 | } |
549 | ||
7d054817 JD |
550 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
551 | { | |
552 | u32 icr; | |
553 | ||
554 | /* | |
555 | * Clear the STOP and ACK flags | |
556 | */ | |
557 | icr = readl(_ICR(i2c)); | |
558 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 559 | writel(icr, _ICR(i2c)); |
7d054817 JD |
560 | } |
561 | ||
b7a36701 MR |
562 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
563 | { | |
564 | /* make timeout the same as for interrupt based functions */ | |
565 | long timeout = 2 * DEF_TIMEOUT; | |
566 | ||
567 | /* | |
568 | * Wait for the bus to become free. | |
569 | */ | |
570 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
571 | udelay(1000); | |
572 | show_state(i2c); | |
573 | } | |
574 | ||
575 | if (timeout <= 0) { | |
576 | show_state(i2c); | |
577 | dev_err(&i2c->adap.dev, | |
578 | "i2c_pxa: timeout waiting for bus free\n"); | |
579 | return I2C_RETRY; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Set master mode. | |
584 | */ | |
585 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
591 | struct i2c_msg *msg, int num) | |
592 | { | |
593 | unsigned long timeout = 500000; /* 5 seconds */ | |
594 | int ret = 0; | |
595 | ||
596 | ret = i2c_pxa_pio_set_master(i2c); | |
597 | if (ret) | |
598 | goto out; | |
599 | ||
600 | i2c->msg = msg; | |
601 | i2c->msg_num = num; | |
602 | i2c->msg_idx = 0; | |
603 | i2c->msg_ptr = 0; | |
604 | i2c->irqlogidx = 0; | |
605 | ||
606 | i2c_pxa_start_message(i2c); | |
607 | ||
608 | while (timeout-- && i2c->msg_num > 0) { | |
609 | i2c_pxa_handler(0, i2c); | |
610 | udelay(10); | |
611 | } | |
612 | ||
613 | i2c_pxa_stop_message(i2c); | |
614 | ||
615 | /* | |
616 | * We place the return code in i2c->msg_idx. | |
617 | */ | |
618 | ret = i2c->msg_idx; | |
619 | ||
620 | out: | |
621 | if (timeout == 0) | |
622 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
623 | ||
624 | return ret; | |
625 | } | |
626 | ||
b652b438 | 627 | /* |
3fb9a655 | 628 | * We are protected by the adapter bus mutex. |
b652b438 RK |
629 | */ |
630 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
631 | { | |
632 | long timeout; | |
633 | int ret; | |
634 | ||
635 | /* | |
636 | * Wait for the bus to become free. | |
637 | */ | |
638 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
639 | if (ret) { | |
6fd60fa9 | 640 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
641 | goto out; |
642 | } | |
643 | ||
644 | /* | |
645 | * Set master mode. | |
646 | */ | |
647 | ret = i2c_pxa_set_master(i2c); | |
648 | if (ret) { | |
6fd60fa9 | 649 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
650 | goto out; |
651 | } | |
652 | ||
653 | spin_lock_irq(&i2c->lock); | |
654 | ||
655 | i2c->msg = msg; | |
656 | i2c->msg_num = num; | |
657 | i2c->msg_idx = 0; | |
658 | i2c->msg_ptr = 0; | |
659 | i2c->irqlogidx = 0; | |
660 | ||
661 | i2c_pxa_start_message(i2c); | |
662 | ||
663 | spin_unlock_irq(&i2c->lock); | |
664 | ||
665 | /* | |
666 | * The rest of the processing occurs in the interrupt handler. | |
667 | */ | |
668 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 669 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
670 | |
671 | /* | |
672 | * We place the return code in i2c->msg_idx. | |
673 | */ | |
674 | ret = i2c->msg_idx; | |
675 | ||
676 | if (timeout == 0) | |
677 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
678 | ||
679 | out: | |
680 | return ret; | |
681 | } | |
682 | ||
b7a36701 MR |
683 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
684 | struct i2c_msg msgs[], int num) | |
685 | { | |
686 | struct pxa_i2c *i2c = adap->algo_data; | |
687 | int ret, i; | |
688 | ||
689 | /* If the I2C controller is disabled we need to reset it | |
690 | (probably due to a suspend/resume destroying state). We do | |
691 | this here as we can then avoid worrying about resuming the | |
692 | controller before its users. */ | |
693 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
694 | i2c_pxa_reset(i2c); | |
695 | ||
696 | for (i = adap->retries; i >= 0; i--) { | |
697 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
698 | if (ret != I2C_RETRY) | |
699 | goto out; | |
700 | ||
701 | if (i2c_debug) | |
702 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
703 | udelay(100); | |
704 | } | |
705 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
706 | ret = -EREMOTEIO; | |
707 | out: | |
708 | i2c_pxa_set_slave(i2c, ret); | |
709 | return ret; | |
710 | } | |
711 | ||
b652b438 RK |
712 | /* |
713 | * i2c_pxa_master_complete - complete the message and wake up. | |
714 | */ | |
715 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
716 | { | |
717 | i2c->msg_ptr = 0; | |
718 | i2c->msg = NULL; | |
719 | i2c->msg_idx ++; | |
720 | i2c->msg_num = 0; | |
721 | if (ret) | |
722 | i2c->msg_idx = ret; | |
b7a36701 MR |
723 | if (!i2c->use_pio) |
724 | wake_up(&i2c->wait); | |
b652b438 RK |
725 | } |
726 | ||
727 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
728 | { | |
a7b4e550 | 729 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
730 | |
731 | again: | |
732 | /* | |
733 | * If ISR_ALD is set, we lost arbitration. | |
734 | */ | |
735 | if (isr & ISR_ALD) { | |
736 | /* | |
737 | * Do we need to do anything here? The PXA docs | |
738 | * are vague about what happens. | |
739 | */ | |
740 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
741 | ||
742 | /* | |
743 | * We ignore this error. We seem to see spurious ALDs | |
744 | * for seemingly no reason. If we handle them as I think | |
745 | * they should, we end up causing an I2C error, which | |
746 | * is painful for some systems. | |
747 | */ | |
748 | return; /* ignore */ | |
749 | } | |
750 | ||
751 | if (isr & ISR_BED) { | |
752 | int ret = BUS_ERROR; | |
753 | ||
754 | /* | |
755 | * I2C bus error - either the device NAK'd us, or | |
756 | * something more serious happened. If we were NAK'd | |
757 | * on the initial address phase, we can retry. | |
758 | */ | |
759 | if (isr & ISR_ACKNAK) { | |
760 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
761 | ret = I2C_RETRY; | |
762 | else | |
763 | ret = XFER_NAKED; | |
764 | } | |
765 | i2c_pxa_master_complete(i2c, ret); | |
766 | } else if (isr & ISR_RWM) { | |
767 | /* | |
768 | * Read mode. We have just sent the address byte, and | |
769 | * now we must initiate the transfer. | |
770 | */ | |
771 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
772 | i2c->msg_idx == i2c->msg_num - 1) | |
773 | icr |= ICR_STOP | ICR_ACKNAK; | |
774 | ||
775 | icr |= ICR_ALDIE | ICR_TB; | |
776 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
777 | /* | |
778 | * Write mode. Write the next data byte. | |
779 | */ | |
a7b4e550 | 780 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
781 | |
782 | icr |= ICR_ALDIE | ICR_TB; | |
783 | ||
784 | /* | |
785 | * If this is the last byte of the last message, send | |
786 | * a STOP. | |
787 | */ | |
788 | if (i2c->msg_ptr == i2c->msg->len && | |
789 | i2c->msg_idx == i2c->msg_num - 1) | |
790 | icr |= ICR_STOP; | |
791 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
792 | /* | |
793 | * Next segment of the message. | |
794 | */ | |
795 | i2c->msg_ptr = 0; | |
796 | i2c->msg_idx ++; | |
797 | i2c->msg++; | |
798 | ||
799 | /* | |
800 | * If we aren't doing a repeated start and address, | |
801 | * go back and try to send the next byte. Note that | |
802 | * we do not support switching the R/W direction here. | |
803 | */ | |
804 | if (i2c->msg->flags & I2C_M_NOSTART) | |
805 | goto again; | |
806 | ||
807 | /* | |
808 | * Write the next address. | |
809 | */ | |
a7b4e550 | 810 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
811 | |
812 | /* | |
813 | * And trigger a repeated start, and send the byte. | |
814 | */ | |
815 | icr &= ~ICR_ALDIE; | |
816 | icr |= ICR_START | ICR_TB; | |
817 | } else { | |
818 | if (i2c->msg->len == 0) { | |
819 | /* | |
820 | * Device probes have a message length of zero | |
821 | * and need the bus to be reset before it can | |
822 | * be used again. | |
823 | */ | |
824 | i2c_pxa_reset(i2c); | |
825 | } | |
826 | i2c_pxa_master_complete(i2c, 0); | |
827 | } | |
828 | ||
829 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
830 | ||
a7b4e550 | 831 | writel(icr, _ICR(i2c)); |
b652b438 RK |
832 | show_state(i2c); |
833 | } | |
834 | ||
835 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
836 | { | |
a7b4e550 | 837 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
838 | |
839 | /* | |
840 | * Read the byte. | |
841 | */ | |
a7b4e550 | 842 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
843 | |
844 | if (i2c->msg_ptr < i2c->msg->len) { | |
845 | /* | |
846 | * If this is the last byte of the last | |
847 | * message, send a STOP. | |
848 | */ | |
849 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
850 | icr |= ICR_STOP | ICR_ACKNAK; | |
851 | ||
852 | icr |= ICR_ALDIE | ICR_TB; | |
853 | } else { | |
854 | i2c_pxa_master_complete(i2c, 0); | |
855 | } | |
856 | ||
857 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
858 | ||
a7b4e550 | 859 | writel(icr, _ICR(i2c)); |
b652b438 RK |
860 | } |
861 | ||
7d12e780 | 862 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
863 | { |
864 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 865 | u32 isr = readl(_ISR(i2c)); |
b652b438 RK |
866 | |
867 | if (i2c_debug > 2 && 0) { | |
6fd60fa9 | 868 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 869 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
870 | decode_ISR(isr); |
871 | } | |
872 | ||
7e3d7db5 | 873 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
874 | i2c->isrlog[i2c->irqlogidx++] = isr; |
875 | ||
876 | show_state(i2c); | |
877 | ||
878 | /* | |
879 | * Always clear all pending IRQs. | |
880 | */ | |
a7b4e550 | 881 | writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c)); |
b652b438 RK |
882 | |
883 | if (isr & ISR_SAD) | |
884 | i2c_pxa_slave_start(i2c, isr); | |
885 | if (isr & ISR_SSD) | |
886 | i2c_pxa_slave_stop(i2c); | |
887 | ||
888 | if (i2c_pxa_is_slavemode(i2c)) { | |
889 | if (isr & ISR_ITE) | |
890 | i2c_pxa_slave_txempty(i2c, isr); | |
891 | if (isr & ISR_IRF) | |
892 | i2c_pxa_slave_rxfull(i2c, isr); | |
893 | } else if (i2c->msg) { | |
894 | if (isr & ISR_ITE) | |
895 | i2c_pxa_irq_txempty(i2c, isr); | |
896 | if (isr & ISR_IRF) | |
897 | i2c_pxa_irq_rxfull(i2c, isr); | |
898 | } else { | |
899 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
900 | } | |
901 | ||
902 | return IRQ_HANDLED; | |
903 | } | |
904 | ||
905 | ||
906 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
907 | { | |
908 | struct pxa_i2c *i2c = adap->algo_data; | |
909 | int ret, i; | |
910 | ||
ece5f7b3 RP |
911 | /* If the I2C controller is disabled we need to reset it (probably due |
912 | to a suspend/resume destroying state). We do this here as we can then | |
913 | avoid worrying about resuming the controller before its users. */ | |
a7b4e550 | 914 | if (!(readl(_ICR(i2c)) & ICR_IUE)) |
ece5f7b3 RP |
915 | i2c_pxa_reset(i2c); |
916 | ||
b652b438 RK |
917 | for (i = adap->retries; i >= 0; i--) { |
918 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
919 | if (ret != I2C_RETRY) | |
920 | goto out; | |
921 | ||
922 | if (i2c_debug) | |
6fd60fa9 | 923 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
924 | udelay(100); |
925 | } | |
926 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
927 | ret = -EREMOTEIO; | |
928 | out: | |
929 | i2c_pxa_set_slave(i2c, ret); | |
930 | return ret; | |
931 | } | |
932 | ||
da16e324 RK |
933 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
934 | { | |
935 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
936 | } | |
937 | ||
8f9082c5 | 938 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 939 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 940 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
941 | }; |
942 | ||
b7a36701 MR |
943 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
944 | .master_xfer = i2c_pxa_pio_xfer, | |
945 | .functionality = i2c_pxa_functionality, | |
946 | }; | |
947 | ||
a7b4e550 | 948 | #define res_len(r) ((r)->end - (r)->start + 1) |
3ae5eaec | 949 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 950 | { |
6776f3d2 | 951 | struct pxa_i2c *i2c; |
a7b4e550 | 952 | struct resource *res; |
3ae5eaec | 953 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
b652b438 | 954 | int ret; |
a7b4e550 | 955 | int irq; |
b652b438 | 956 | |
a7b4e550 GL |
957 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
958 | irq = platform_get_irq(dev, 0); | |
959 | if (res == NULL || irq < 0) | |
960 | return -ENODEV; | |
961 | ||
962 | if (!request_mem_region(res->start, res_len(res), res->name)) | |
963 | return -ENOMEM; | |
964 | ||
6776f3d2 | 965 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
966 | if (!i2c) { |
967 | ret = -ENOMEM; | |
968 | goto emalloc; | |
969 | } | |
970 | ||
6776f3d2 | 971 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
972 | i2c->adap.retries = 5; |
973 | ||
974 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 975 | init_waitqueue_head(&i2c->wait); |
6776f3d2 | 976 | |
a92b36ed WS |
977 | /* |
978 | * If "dev->id" is negative we consider it as zero. | |
979 | * The reason to do so is to avoid sysfs names that only make | |
980 | * sense when there are multiple adapters. | |
981 | */ | |
982 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; | |
983 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", | |
984 | i2c->adap.nr); | |
a7b4e550 | 985 | |
c3cef3f3 RK |
986 | i2c->clk = clk_get(&dev->dev, "I2CCLK"); |
987 | if (IS_ERR(i2c->clk)) { | |
988 | ret = PTR_ERR(i2c->clk); | |
989 | goto eclk; | |
990 | } | |
991 | ||
a7b4e550 GL |
992 | i2c->reg_base = ioremap(res->start, res_len(res)); |
993 | if (!i2c->reg_base) { | |
994 | ret = -EIO; | |
995 | goto eremap; | |
996 | } | |
997 | ||
998 | i2c->iobase = res->start; | |
999 | i2c->iosize = res_len(res); | |
1000 | ||
1001 | i2c->irq = irq; | |
b652b438 RK |
1002 | |
1003 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1004 | ||
1005 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
1006 | if (plat) { |
1007 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 1008 | i2c->slave = plat->slave; |
b652b438 RK |
1009 | } |
1010 | #endif | |
1011 | ||
c3cef3f3 | 1012 | clk_enable(i2c->clk); |
a7b4e550 | 1013 | |
b7a36701 MR |
1014 | if (plat) { |
1015 | i2c->adap.class = plat->class; | |
1016 | i2c->use_pio = plat->use_pio; | |
1017 | } | |
1018 | ||
1019 | if (i2c->use_pio) { | |
1020 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1021 | } else { | |
1022 | i2c->adap.algo = &i2c_pxa_algorithm; | |
1023 | ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, | |
1024 | i2c->adap.name, i2c); | |
1025 | if (ret) | |
1026 | goto ereqirq; | |
1027 | } | |
a7b4e550 | 1028 | |
b652b438 RK |
1029 | i2c_pxa_reset(i2c); |
1030 | ||
1031 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1032 | i2c->adap.dev.parent = &dev->dev; |
b652b438 | 1033 | |
066af983 | 1034 | ret = i2c_add_numbered_adapter(&i2c->adap); |
b652b438 RK |
1035 | if (ret < 0) { |
1036 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1037 | goto eadapt; |
b652b438 RK |
1038 | } |
1039 | ||
3ae5eaec | 1040 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1041 | |
1042 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1043 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
1044 | i2c->adap.dev.bus_id, i2c->slave_addr); | |
1045 | #else | |
1046 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
1047 | i2c->adap.dev.bus_id); | |
1048 | #endif | |
1049 | return 0; | |
1050 | ||
a7b4e550 | 1051 | eadapt: |
b7a36701 MR |
1052 | if (!i2c->use_pio) |
1053 | free_irq(irq, i2c); | |
a7b4e550 | 1054 | ereqirq: |
c3cef3f3 | 1055 | clk_disable(i2c->clk); |
a92b36ed | 1056 | iounmap(i2c->reg_base); |
a7b4e550 | 1057 | eremap: |
c3cef3f3 RK |
1058 | clk_put(i2c->clk); |
1059 | eclk: | |
a7b4e550 GL |
1060 | kfree(i2c); |
1061 | emalloc: | |
1062 | release_mem_region(res->start, res_len(res)); | |
b652b438 RK |
1063 | return ret; |
1064 | } | |
1065 | ||
a92b36ed | 1066 | static int __exit i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1067 | { |
3ae5eaec | 1068 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1069 | |
3ae5eaec | 1070 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
1071 | |
1072 | i2c_del_adapter(&i2c->adap); | |
b7a36701 MR |
1073 | if (!i2c->use_pio) |
1074 | free_irq(i2c->irq, i2c); | |
c3cef3f3 RK |
1075 | |
1076 | clk_disable(i2c->clk); | |
1077 | clk_put(i2c->clk); | |
c3cef3f3 | 1078 | |
a92b36ed | 1079 | iounmap(i2c->reg_base); |
a7b4e550 GL |
1080 | release_mem_region(i2c->iobase, i2c->iosize); |
1081 | kfree(i2c); | |
b652b438 RK |
1082 | |
1083 | return 0; | |
1084 | } | |
1085 | ||
3ae5eaec | 1086 | static struct platform_driver i2c_pxa_driver = { |
b652b438 | 1087 | .probe = i2c_pxa_probe, |
a92b36ed | 1088 | .remove = __exit_p(i2c_pxa_remove), |
3ae5eaec RK |
1089 | .driver = { |
1090 | .name = "pxa2xx-i2c", | |
a92b36ed | 1091 | .owner = THIS_MODULE, |
3ae5eaec | 1092 | }, |
b652b438 RK |
1093 | }; |
1094 | ||
1095 | static int __init i2c_adap_pxa_init(void) | |
1096 | { | |
3ae5eaec | 1097 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1098 | } |
1099 | ||
a92b36ed | 1100 | static void __exit i2c_adap_pxa_exit(void) |
b652b438 | 1101 | { |
d6a7b5f8 | 1102 | platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1103 | } |
1104 | ||
ece5f7b3 | 1105 | MODULE_LICENSE("GPL"); |
add8eda7 | 1106 | MODULE_ALIAS("platform:pxa2xx-i2c"); |
ece5f7b3 | 1107 | |
b652b438 RK |
1108 | module_init(i2c_adap_pxa_init); |
1109 | module_exit(i2c_adap_pxa_exit); |