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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / drivers / i2c / busses / i2c-pxa.c
CommitLineData
b652b438
RK		 1/*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/i2c.h>
25#include <linux/i2c-id.h>
26#include <linux/init.h>
27#include <linux/time.h>
28#include <linux/sched.h>
29#include <linux/delay.h>
30#include <linux/errno.h>
31#include <linux/interrupt.h>
32#include <linux/i2c-pxa.h>
d052d1be 33#include <linux/platform_device.h>
b652b438
RK		 34
35#include <asm/hardware.h>
36#include <asm/irq.h>
37#include <asm/arch/i2c.h>
38#include <asm/arch/pxa-regs.h>
39
40struct pxa_i2c {
41 spinlock_t lock;
42 wait_queue_head_t wait;
43 struct i2c_msg *msg;
44 unsigned int msg_num;
45 unsigned int msg_idx;
46 unsigned int msg_ptr;
47 unsigned int slave_addr;
48
49 struct i2c_adapter adap;
50#ifdef CONFIG_I2C_PXA_SLAVE
51 struct i2c_slave_client *slave;
52#endif
53
54 unsigned int irqlogidx;
55 u32 isrlog[32];
56 u32 icrlog[32];
57};
58
59/*
60 * I2C Slave mode address
61 */
62#define I2C_PXA_SLAVE_ADDR 0x1
63
b652b438
RK		 64#ifdef DEBUG
65
66struct bits {
67 u32 mask;
68 const char *set;
69 const char *unset;
70};
71#define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
72
73static inline void
74decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
75{
76 printk("%s %08x: ", prefix, val);
77 while (num--) {
78 const char *str = val & bits->mask ? bits->set : bits->unset;
79 if (str)
80 printk("%s ", str);
81 bits++;
82 }
83}
84
85static const struct bits isr_bits[] = {
86 BIT(ISR_RWM, "RX", "TX"),
87 BIT(ISR_ACKNAK, "NAK", "ACK"),
88 BIT(ISR_UB, "Bsy", "Rdy"),
89 BIT(ISR_IBB, "BusBsy", "BusRdy"),
90 BIT(ISR_SSD, "SlaveStop", NULL),
91 BIT(ISR_ALD, "ALD", NULL),
92 BIT(ISR_ITE, "TxEmpty", NULL),
93 BIT(ISR_IRF, "RxFull", NULL),
94 BIT(ISR_GCAD, "GenCall", NULL),
95 BIT(ISR_SAD, "SlaveAddr", NULL),
96 BIT(ISR_BED, "BusErr", NULL),
97};
98
99static void decode_ISR(unsigned int val)
100{
6fd60fa9 101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
b652b438
RK		 102 printk("\n");
103}
104
105static const struct bits icr_bits[] = {
106 BIT(ICR_START, "START", NULL),
107 BIT(ICR_STOP, "STOP", NULL),
108 BIT(ICR_ACKNAK, "ACKNAK", NULL),
109 BIT(ICR_TB, "TB", NULL),
110 BIT(ICR_MA, "MA", NULL),
111 BIT(ICR_SCLE, "SCLE", "scle"),
112 BIT(ICR_IUE, "IUE", "iue"),
113 BIT(ICR_GCD, "GCD", NULL),
114 BIT(ICR_ITEIE, "ITEIE", NULL),
115 BIT(ICR_IRFIE, "IRFIE", NULL),
116 BIT(ICR_BEIE, "BEIE", NULL),
117 BIT(ICR_SSDIE, "SSDIE", NULL),
118 BIT(ICR_ALDIE, "ALDIE", NULL),
119 BIT(ICR_SADIE, "SADIE", NULL),
120 BIT(ICR_UR, "UR", "ur"),
121};
122
123static void decode_ICR(unsigned int val)
124{
6fd60fa9 125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
b652b438
RK		 126 printk("\n");
127}
128
129static unsigned int i2c_debug = DEBUG;
130
131static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
132{
6fd60fa9 133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
b652b438
RK		 134}
135
136#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
137#else
138#define i2c_debug 0
139
140#define show_state(i2c) do { } while (0)
141#define decode_ISR(val) do { } while (0)
142#define decode_ICR(val) do { } while (0)
143#endif
144
6fd60fa9 145#define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
b652b438
RK		 146
147static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
148
149static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
150{
151 unsigned int i;
152 printk("i2c: error: %s\n", why);
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
6fd60fa9
RK		 155 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR);
b652b438
RK		 157 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
159 printk("\n");
160}
161
162static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
163{
164 return !(ICR & ICR_SCLE);
165}
166
167static void i2c_pxa_abort(struct pxa_i2c *i2c)
168{
169 unsigned long timeout = jiffies + HZ/4;
170
171 if (i2c_pxa_is_slavemode(i2c)) {
6fd60fa9 172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
b652b438
RK		 173 return;
174 }
175
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
177 unsigned long icr = ICR;
178
179 icr &= ~ICR_START;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
181
182 ICR = icr;
183
184 show_state(i2c);
185
186 msleep(1);
187 }
188
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
190}
191
192static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
193{
194 int timeout = DEF_TIMEOUT;
195
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0)
198 timeout += 4;
199
200 msleep(2);
201 show_state(i2c);
202 }
203
204 if (timeout <= 0)
205 show_state(i2c);
206
207 return timeout <= 0 ? I2C_RETRY : 0;
208}
209
210static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
211{
212 unsigned long timeout = jiffies + HZ*4;
213
214 while (time_before(jiffies, timeout)) {
215 if (i2c_debug > 1)
6fd60fa9
RK		 216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR);
b652b438
RK		 218
219 if (ISR & ISR_SAD) {
220 if (i2c_debug > 0)
6fd60fa9 221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
b652b438
RK		 222 goto out;
223 }
224
225 /* wait for unit and bus being not busy, and we also do a
226 * quick check of the i2c lines themselves to ensure they've
227 * gone high...
228 */
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
230 if (i2c_debug > 0)
6fd60fa9 231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
b652b438
RK		 232 return 1;
233 }
234
235 msleep(1);
236 }
237
238 if (i2c_debug > 0)
6fd60fa9 239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
b652b438
RK		 240 out:
241 return 0;
242}
243
244static int i2c_pxa_set_master(struct pxa_i2c *i2c)
245{
246 if (i2c_debug)
6fd60fa9 247 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
b652b438
RK		 248
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
6fd60fa9 250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
b652b438 251 if (!i2c_pxa_wait_master(i2c)) {
6fd60fa9 252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
b652b438
RK		 253 return I2C_RETRY;
254 }
255 }
256
257 ICR |= ICR_SCLE;
258 return 0;
259}
260
261#ifdef CONFIG_I2C_PXA_SLAVE
262static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
263{
264 unsigned long timeout = jiffies + HZ*1;
265
266 /* wait for stop */
267
268 show_state(i2c);
269
270 while (time_before(jiffies, timeout)) {
271 if (i2c_debug > 1)
6fd60fa9
RK		 272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR);
b652b438
RK		 274
275 if ((ISR & (ISR_UB|ISR_IBB|ISR_SAD)) == ISR_SAD ||
276 (ICR & ICR_SCLE) == 0) {
277 if (i2c_debug > 1)
6fd60fa9 278 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
b652b438
RK		 279 return 1;
280 }
281
282 msleep(1);
283 }
284
285 if (i2c_debug > 0)
6fd60fa9 286 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
b652b438
RK		 287 return 0;
288}
289
290/*
291 * clear the hold on the bus, and take of anything else
292 * that has been configured
293 */
294static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
295{
296 show_state(i2c);
297
298 if (errcode < 0) {
299 udelay(100); /* simple delay */
300 } else {
301 /* we need to wait for the stop condition to end */
302
303 /* if we where in stop, then clear... */
304 if (ICR & ICR_STOP) {
305 udelay(100);
306 ICR &= ~ICR_STOP;
307 }
308
309 if (!i2c_pxa_wait_slave(i2c)) {
6fd60fa9
RK		 310 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
311 __func__);
b652b438
RK		 312 return;
313 }
314 }
315
316 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
317 ICR &= ~ICR_SCLE;
318
319 if (i2c_debug) {
6fd60fa9 320 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
b652b438
RK		 321 decode_ICR(ICR);
322 }
323}
324#else
325#define i2c_pxa_set_slave(i2c, err) do { } while (0)
326#endif
327
328static void i2c_pxa_reset(struct pxa_i2c *i2c)
329{
330 pr_debug("Resetting I2C Controller Unit\n");
331
332 /* abort any transfer currently under way */
333 i2c_pxa_abort(i2c);
334
335 /* reset according to 9.8 */
336 ICR = ICR_UR;
337 ISR = I2C_ISR_INIT;
338 ICR &= ~ICR_UR;
339
340 ISAR = i2c->slave_addr;
341
342 /* set control register values */
343 ICR = I2C_ICR_INIT;
344
345#ifdef CONFIG_I2C_PXA_SLAVE
6fd60fa9 346 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
b652b438
RK		 347 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
348#endif
349
350 i2c_pxa_set_slave(i2c, 0);
351
352 /* enable unit */
353 ICR |= ICR_IUE;
354 udelay(100);
355}
356
357
358#ifdef CONFIG_I2C_PXA_SLAVE
359/*
360 * I2C EEPROM emulation.
361 */
362static struct i2c_eeprom_emu eeprom = {
363 .size = I2C_EEPROM_EMU_SIZE,
364 .watch = LIST_HEAD_INIT(eeprom.watch),
365};
366
367struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
368{
369 return &eeprom;
370}
371
372int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
373 unsigned int addr, unsigned int size,
374 struct i2c_eeprom_emu_watcher *watcher)
375{
376 struct i2c_eeprom_emu_watch *watch;
377 unsigned long flags;
378
379 if (addr + size > emu->size)
380 return -EINVAL;
381
382 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
383 if (watch) {
384 watch->start = addr;
385 watch->end = addr + size - 1;
386 watch->ops = watcher;
387 watch->data = data;
388
389 local_irq_save(flags);
390 list_add(&watch->node, &emu->watch);
391 local_irq_restore(flags);
392 }
393
394 return watch ? 0 : -ENOMEM;
395}
396
397void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
398 struct i2c_eeprom_emu_watcher *watcher)
399{
400 struct i2c_eeprom_emu_watch *watch, *n;
401 unsigned long flags;
402
403 list_for_each_entry_safe(watch, n, &emu->watch, node) {
404 if (watch->ops == watcher && watch->data == data) {
405 local_irq_save(flags);
406 list_del(&watch->node);
407 local_irq_restore(flags);
408 kfree(watch);
409 }
410 }
411}
412
413static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
414{
415 struct i2c_eeprom_emu *emu = ptr;
416
417 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
418
419 switch (event) {
420 case I2C_SLAVE_EVENT_START_WRITE:
421 emu->seen_start = 1;
422 eedbg(2, "i2c_eeprom: write initiated\n");
423 break;
424
425 case I2C_SLAVE_EVENT_START_READ:
426 emu->seen_start = 0;
427 eedbg(2, "i2c_eeprom: read initiated\n");
428 break;
429
430 case I2C_SLAVE_EVENT_STOP:
431 emu->seen_start = 0;
432 eedbg(2, "i2c_eeprom: received stop\n");
433 break;
434
435 default:
436 eedbg(0, "i2c_eeprom: unhandled event\n");
437 break;
438 }
439}
440
441static int i2c_eeprom_emu_read(void *ptr)
442{
443 struct i2c_eeprom_emu *emu = ptr;
444 int ret;
445
446 ret = emu->bytes[emu->ptr];
447 emu->ptr = (emu->ptr + 1) % emu->size;
448
449 return ret;
450}
451
452static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
453{
454 struct i2c_eeprom_emu *emu = ptr;
455 struct i2c_eeprom_emu_watch *watch;
456
457 if (emu->seen_start != 0) {
458 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
459 emu->ptr = val;
460 emu->seen_start = 0;
461 return;
462 }
463
464 emu->bytes[emu->ptr] = val;
465
466 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
467 emu->ptr, val);
468
469 list_for_each_entry(watch, &emu->watch, node) {
470 if (!watch->ops || !watch->ops->write)
471 continue;
472 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
473 watch->ops->write(watch->data, emu->ptr, val);
474 }
475
476 emu->ptr = (emu->ptr + 1) % emu->size;
477}
478
479struct i2c_slave_client eeprom_client = {
480 .data = &eeprom,
481 .event = i2c_eeprom_emu_event,
482 .read = i2c_eeprom_emu_read,
483 .write = i2c_eeprom_emu_write
484};
485
486/*
487 * PXA I2C Slave mode
488 */
489
490static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
491{
492 if (isr & ISR_BED) {
493 /* what should we do here? */
494 } else {
495 int ret = i2c->slave->read(i2c->slave->data);
496
497 IDBR = ret;
498 ICR |= ICR_TB; /* allow next byte */
499 }
500}
501
502static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
503{
504 unsigned int byte = IDBR;
505
506 if (i2c->slave != NULL)
507 i2c->slave->write(i2c->slave->data, byte);
508
509 ICR |= ICR_TB;
510}
511
512static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
513{
514 int timeout;
515
516 if (i2c_debug > 0)
6fd60fa9 517 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
b652b438
RK		 518 (isr & ISR_RWM) ? 'r' : 't');
519
520 if (i2c->slave != NULL)
521 i2c->slave->event(i2c->slave->data,
522 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
523
524 /*
525 * slave could interrupt in the middle of us generating a
526 * start condition... if this happens, we'd better back off
527 * and stop holding the poor thing up
528 */
529 ICR &= ~(ICR_START|ICR_STOP);
530 ICR |= ICR_TB;
531
532 timeout = 0x10000;
533
534 while (1) {
535 if ((IBMR & 2) == 2)
536 break;
537
538 timeout--;
539
540 if (timeout <= 0) {
6fd60fa9 541 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
b652b438
RK		 542 break;
543 }
544 }
545
546 ICR &= ~ICR_SCLE;
547}
548
549static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
550{
551 if (i2c_debug > 2)
6fd60fa9 552 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
b652b438
RK		 553
554 if (i2c->slave != NULL)
555 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
556
557 if (i2c_debug > 2)
6fd60fa9 558 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
b652b438
RK		 559
560 /*
561 * If we have a master-mode message waiting,
562 * kick it off now that the slave has completed.
563 */
564 if (i2c->msg)
565 i2c_pxa_master_complete(i2c, I2C_RETRY);
566}
567#else
568static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
569{
570 if (isr & ISR_BED) {
571 /* what should we do here? */
572 } else {
573 IDBR = 0;
574 ICR |= ICR_TB;
575 }
576}
577
578static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
579{
580 ICR |= ICR_TB | ICR_ACKNAK;
581}
582
583static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
584{
585 int timeout;
586
587 /*
588 * slave could interrupt in the middle of us generating a
589 * start condition... if this happens, we'd better back off
590 * and stop holding the poor thing up
591 */
592 ICR &= ~(ICR_START|ICR_STOP);
593 ICR |= ICR_TB | ICR_ACKNAK;
594
595 timeout = 0x10000;
596
597 while (1) {
598 if ((IBMR & 2) == 2)
599 break;
600
601 timeout--;
602
603 if (timeout <= 0) {
6fd60fa9 604 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
b652b438
RK		 605 break;
606 }
607 }
608
609 ICR &= ~ICR_SCLE;
610}
611
612static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
613{
614 if (i2c->msg)
615 i2c_pxa_master_complete(i2c, I2C_RETRY);
616}
617#endif
618
619/*
620 * PXA I2C Master mode
621 */
622
623static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
624{
625 unsigned int addr = (msg->addr & 0x7f) << 1;
626
627 if (msg->flags & I2C_M_RD)
628 addr |= 1;
629
630 return addr;
631}
632
633static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
634{
635 u32 icr;
636
637 /*
638 * Step 1: target slave address into IDBR
639 */
640 IDBR = i2c_pxa_addr_byte(i2c->msg);
641
642 /*
643 * Step 2: initiate the write.
644 */
645 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
646 ICR = icr | ICR_START | ICR_TB;
647}
648
649/*
650 * We are protected by the adapter bus semaphore.
651 */
652static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
653{
654 long timeout;
655 int ret;
656
657 /*
658 * Wait for the bus to become free.
659 */
660 ret = i2c_pxa_wait_bus_not_busy(i2c);
661 if (ret) {
6fd60fa9 662 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
b652b438
RK		 663 goto out;
664 }
665
666 /*
667 * Set master mode.
668 */
669 ret = i2c_pxa_set_master(i2c);
670 if (ret) {
6fd60fa9 671 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
b652b438
RK		 672 goto out;
673 }
674
675 spin_lock_irq(&i2c->lock);
676
677 i2c->msg = msg;
678 i2c->msg_num = num;
679 i2c->msg_idx = 0;
680 i2c->msg_ptr = 0;
681 i2c->irqlogidx = 0;
682
683 i2c_pxa_start_message(i2c);
684
685 spin_unlock_irq(&i2c->lock);
686
687 /*
688 * The rest of the processing occurs in the interrupt handler.
689 */
690 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
691
692 /*
693 * We place the return code in i2c->msg_idx.
694 */
695 ret = i2c->msg_idx;
696
697 if (timeout == 0)
698 i2c_pxa_scream_blue_murder(i2c, "timeout");
699
700 out:
701 return ret;
702}
703
704/*
705 * i2c_pxa_master_complete - complete the message and wake up.
706 */
707static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
708{
709 i2c->msg_ptr = 0;
710 i2c->msg = NULL;
711 i2c->msg_idx ++;
712 i2c->msg_num = 0;
713 if (ret)
714 i2c->msg_idx = ret;
715 wake_up(&i2c->wait);
716}
717
718static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
719{
720 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
721
722 again:
723 /*
724 * If ISR_ALD is set, we lost arbitration.
725 */
726 if (isr & ISR_ALD) {
727 /*
728 * Do we need to do anything here? The PXA docs
729 * are vague about what happens.
730 */
731 i2c_pxa_scream_blue_murder(i2c, "ALD set");
732
733 /*
734 * We ignore this error. We seem to see spurious ALDs
735 * for seemingly no reason. If we handle them as I think
736 * they should, we end up causing an I2C error, which
737 * is painful for some systems.
738 */
739 return; /* ignore */
740 }
741
742 if (isr & ISR_BED) {
743 int ret = BUS_ERROR;
744
745 /*
746 * I2C bus error - either the device NAK'd us, or
747 * something more serious happened. If we were NAK'd
748 * on the initial address phase, we can retry.
749 */
750 if (isr & ISR_ACKNAK) {
751 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
752 ret = I2C_RETRY;
753 else
754 ret = XFER_NAKED;
755 }
756 i2c_pxa_master_complete(i2c, ret);
757 } else if (isr & ISR_RWM) {
758 /*
759 * Read mode. We have just sent the address byte, and
760 * now we must initiate the transfer.
761 */
762 if (i2c->msg_ptr == i2c->msg->len - 1 &&
763 i2c->msg_idx == i2c->msg_num - 1)
764 icr |= ICR_STOP | ICR_ACKNAK;
765
766 icr |= ICR_ALDIE | ICR_TB;
767 } else if (i2c->msg_ptr < i2c->msg->len) {
768 /*
769 * Write mode. Write the next data byte.
770 */
771 IDBR = i2c->msg->buf[i2c->msg_ptr++];
772
773 icr |= ICR_ALDIE | ICR_TB;
774
775 /*
776 * If this is the last byte of the last message, send
777 * a STOP.
778 */
779 if (i2c->msg_ptr == i2c->msg->len &&
780 i2c->msg_idx == i2c->msg_num - 1)
781 icr |= ICR_STOP;
782 } else if (i2c->msg_idx < i2c->msg_num - 1) {
783 /*
784 * Next segment of the message.
785 */
786 i2c->msg_ptr = 0;
787 i2c->msg_idx ++;
788 i2c->msg++;
789
790 /*
791 * If we aren't doing a repeated start and address,
792 * go back and try to send the next byte. Note that
793 * we do not support switching the R/W direction here.
794 */
795 if (i2c->msg->flags & I2C_M_NOSTART)
796 goto again;
797
798 /*
799 * Write the next address.
800 */
801 IDBR = i2c_pxa_addr_byte(i2c->msg);
802
803 /*
804 * And trigger a repeated start, and send the byte.
805 */
806 icr &= ~ICR_ALDIE;
807 icr |= ICR_START | ICR_TB;
808 } else {
809 if (i2c->msg->len == 0) {
810 /*
811 * Device probes have a message length of zero
812 * and need the bus to be reset before it can
813 * be used again.
814 */
815 i2c_pxa_reset(i2c);
816 }
817 i2c_pxa_master_complete(i2c, 0);
818 }
819
820 i2c->icrlog[i2c->irqlogidx-1] = icr;
821
822 ICR = icr;
823 show_state(i2c);
824}
825
826static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
827{
828 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
829
830 /*
831 * Read the byte.
832 */
833 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
834
835 if (i2c->msg_ptr < i2c->msg->len) {
836 /*
837 * If this is the last byte of the last
838 * message, send a STOP.
839 */
840 if (i2c->msg_ptr == i2c->msg->len - 1)
841 icr |= ICR_STOP | ICR_ACKNAK;
842
843 icr |= ICR_ALDIE | ICR_TB;
844 } else {
845 i2c_pxa_master_complete(i2c, 0);
846 }
847
848 i2c->icrlog[i2c->irqlogidx-1] = icr;
849
850 ICR = icr;
851}
852
853static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
854{
855 struct pxa_i2c *i2c = dev_id;
856 u32 isr = ISR;
857
858 if (i2c_debug > 2 && 0) {
6fd60fa9
RK		 859 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
860 __func__, isr, ICR, IBMR);
b652b438
RK		 861 decode_ISR(isr);
862 }
863
864 if (i2c->irqlogidx < sizeof(i2c->isrlog)/sizeof(u32))
865 i2c->isrlog[i2c->irqlogidx++] = isr;
866
867 show_state(i2c);
868
869 /*
870 * Always clear all pending IRQs.
871 */
872 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
873
874 if (isr & ISR_SAD)
875 i2c_pxa_slave_start(i2c, isr);
876 if (isr & ISR_SSD)
877 i2c_pxa_slave_stop(i2c);
878
879 if (i2c_pxa_is_slavemode(i2c)) {
880 if (isr & ISR_ITE)
881 i2c_pxa_slave_txempty(i2c, isr);
882 if (isr & ISR_IRF)
883 i2c_pxa_slave_rxfull(i2c, isr);
884 } else if (i2c->msg) {
885 if (isr & ISR_ITE)
886 i2c_pxa_irq_txempty(i2c, isr);
887 if (isr & ISR_IRF)
888 i2c_pxa_irq_rxfull(i2c, isr);
889 } else {
890 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
891 }
892
893 return IRQ_HANDLED;
894}
895
896
897static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
898{
899 struct pxa_i2c *i2c = adap->algo_data;
900 int ret, i;
901
902 for (i = adap->retries; i >= 0; i--) {
903 ret = i2c_pxa_do_xfer(i2c, msgs, num);
904 if (ret != I2C_RETRY)
905 goto out;
906
907 if (i2c_debug)
6fd60fa9 908 dev_dbg(&adap->dev, "Retrying transmission\n");
b652b438
RK		 909 udelay(100);
910 }
911 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
912 ret = -EREMOTEIO;
913 out:
914 i2c_pxa_set_slave(i2c, ret);
915 return ret;
916}
917
da16e324
RK		 918static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
919{
920 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
921}
922
b652b438 923static struct i2c_algorithm i2c_pxa_algorithm = {
b652b438 924 .master_xfer = i2c_pxa_xfer,
da16e324 925 .functionality = i2c_pxa_functionality,
b652b438
RK		 926};
927
928static struct pxa_i2c i2c_pxa = {
929 .lock = SPIN_LOCK_UNLOCKED,
930 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
931 .adap = {
da16e324 932 .owner = THIS_MODULE,
b652b438 933 .algo = &i2c_pxa_algorithm,
da16e324 934 .name = "pxa2xx-i2c",
b652b438
RK		 935 .retries = 5,
936 },
937};
938
939static int i2c_pxa_probe(struct device *dev)
940{
941 struct pxa_i2c *i2c = &i2c_pxa;
942 struct i2c_pxa_platform_data *plat = dev->platform_data;
943 int ret;
944
945#ifdef CONFIG_PXA27x
946 pxa_gpio_mode(GPIO117_I2CSCL_MD);
947 pxa_gpio_mode(GPIO118_I2CSDA_MD);
948 udelay(100);
949#endif
950
951 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
952
953#ifdef CONFIG_I2C_PXA_SLAVE
954 i2c->slave = &eeprom_client;
955 if (plat) {
956 i2c->slave_addr = plat->slave_addr;
957 if (plat->slave)
958 i2c->slave = plat->slave;
959 }
960#endif
961
962 pxa_set_cken(CKEN14_I2C, 1);
963 ret = request_irq(IRQ_I2C, i2c_pxa_handler, SA_INTERRUPT,
964 "pxa2xx-i2c", i2c);
965 if (ret)
966 goto out;
967
968 i2c_pxa_reset(i2c);
969
970 i2c->adap.algo_data = i2c;
971 i2c->adap.dev.parent = dev;
972
973 ret = i2c_add_adapter(&i2c->adap);
974 if (ret < 0) {
975 printk(KERN_INFO "I2C: Failed to add bus\n");
976 goto err_irq;
977 }
978
979 dev_set_drvdata(dev, i2c);
980
981#ifdef CONFIG_I2C_PXA_SLAVE
982 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
983 i2c->adap.dev.bus_id, i2c->slave_addr);
984#else
985 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
986 i2c->adap.dev.bus_id);
987#endif
988 return 0;
989
990 err_irq:
991 free_irq(IRQ_I2C, i2c);
992 out:
993 return ret;
994}
995
996static int i2c_pxa_remove(struct device *dev)
997{
998 struct pxa_i2c *i2c = dev_get_drvdata(dev);
999
1000 dev_set_drvdata(dev, NULL);
1001
1002 i2c_del_adapter(&i2c->adap);
1003 free_irq(IRQ_I2C, i2c);
1004 pxa_set_cken(CKEN14_I2C, 0);
1005
1006 return 0;
1007}
1008
1009static struct device_driver i2c_pxa_driver = {
1010 .name = "pxa2xx-i2c",
1011 .bus = &platform_bus_type,
1012 .probe = i2c_pxa_probe,
1013 .remove = i2c_pxa_remove,
1014};
1015
1016static int __init i2c_adap_pxa_init(void)
1017{
1018 return driver_register(&i2c_pxa_driver);
1019}
1020
1021static void i2c_adap_pxa_exit(void)
1022{
1023 return driver_unregister(&i2c_pxa_driver);
1024}
1025
1026module_init(i2c_adap_pxa_init);
1027module_exit(i2c_adap_pxa_exit);
Linux kernel - Deliverables
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