[deliverable/linux.git] / drivers / i2c / busses / i2c-rcar.c

/*
 * Driver for the Renesas RCar I2C unit
 *
 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
 *
 * Copyright (C) 2012-14 Renesas Solutions Corp.
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 *
 * This file used out-of-tree driver i2c-rcar.c
 * Copyright (C) 2011-2012 Renesas Electronics Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/i2c-rcar.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>

/* register offsets */
#define ICSCR	0x00	/* slave ctrl */
#define ICMCR	0x04	/* master ctrl */
#define ICSSR	0x08	/* slave status */
#define ICMSR	0x0C	/* master status */
#define ICSIER	0x10	/* slave irq enable */
#define ICMIER	0x14	/* master irq enable */
#define ICCCR	0x18	/* clock dividers */
#define ICSAR	0x1C	/* slave address */
#define ICMAR	0x20	/* master address */
#define ICRXTX	0x24	/* data port */

/* ICMCR */
#define MDBS	(1 << 7)	/* non-fifo mode switch */
#define FSCL	(1 << 6)	/* override SCL pin */
#define FSDA	(1 << 5)	/* override SDA pin */
#define OBPC	(1 << 4)	/* override pins */
#define MIE	(1 << 3)	/* master if enable */
#define TSBE	(1 << 2)
#define FSB	(1 << 1)	/* force stop bit */
#define ESG	(1 << 0)	/* en startbit gen */

/* ICMSR (also for ICMIE) */
#define MNR	(1 << 6)	/* nack received */
#define MAL	(1 << 5)	/* arbitration lost */
#define MST	(1 << 4)	/* sent a stop */
#define MDE	(1 << 3)
#define MDT	(1 << 2)
#define MDR	(1 << 1)
#define MAT	(1 << 0)	/* slave addr xfer done */


#define RCAR_BUS_PHASE_START	(MDBS | MIE | ESG)
#define RCAR_BUS_PHASE_DATA	(MDBS | MIE)
#define RCAR_BUS_PHASE_STOP	(MDBS | MIE | FSB)

#define RCAR_IRQ_SEND	(MNR | MAL | MST | MAT | MDE)
#define RCAR_IRQ_RECV	(MNR | MAL | MST | MAT | MDR)
#define RCAR_IRQ_STOP	(MST)

#define RCAR_IRQ_ACK_SEND	(~(MAT | MDE))
#define RCAR_IRQ_ACK_RECV	(~(MAT | MDR))

#define ID_LAST_MSG	(1 << 0)
#define ID_IOERROR	(1 << 1)
#define ID_DONE		(1 << 2)
#define ID_ARBLOST	(1 << 3)
#define ID_NACK		(1 << 4)

enum rcar_i2c_type {
	I2C_RCAR_GEN1,
	I2C_RCAR_GEN2,
};

struct rcar_i2c_priv {
	void __iomem *io;
	struct i2c_adapter adap;
	struct i2c_msg	*msg;
	struct clk *clk;

	wait_queue_head_t wait;

	int pos;
	u32 icccr;
	u32 flags;
	enum rcar_i2c_type devtype;
};

#define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
#define rcar_i2c_is_recv(p)		((p)->msg->flags & I2C_M_RD)

#define rcar_i2c_flags_set(p, f)	((p)->flags |= (f))
#define rcar_i2c_flags_has(p, f)	((p)->flags & (f))

#define LOOP_TIMEOUT	1024


static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
{
	writel(val, priv->io + reg);
}

static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
{
	return readl(priv->io + reg);
}

static void rcar_i2c_init(struct rcar_i2c_priv *priv)
{
	/*
	 * reset slave mode.
	 * slave mode is not used on this driver
	 */
	rcar_i2c_write(priv, ICSIER, 0);
	rcar_i2c_write(priv, ICSAR, 0);
	rcar_i2c_write(priv, ICSCR, 0);
	rcar_i2c_write(priv, ICSSR, 0);

	/* reset master mode */
	rcar_i2c_write(priv, ICMIER, 0);
	rcar_i2c_write(priv, ICMCR, 0);
	rcar_i2c_write(priv, ICMSR, 0);
	rcar_i2c_write(priv, ICMAR, 0);
}

static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
{
	int i;

	for (i = 0; i < LOOP_TIMEOUT; i++) {
		/* make sure that bus is not busy */
		if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
			return 0;
		udelay(1);
	}

	return -EBUSY;
}

static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
				    u32 bus_speed,
				    struct device *dev)
{
	u32 scgd, cdf;
	u32 round, ick;
	u32 scl;
	u32 cdf_width;
	unsigned long rate;

	switch (priv->devtype) {
	case I2C_RCAR_GEN1:
		cdf_width = 2;
		break;
	case I2C_RCAR_GEN2:
		cdf_width = 3;
		break;
	default:
		dev_err(dev, "device type error\n");
		return -EIO;
	}

	/*
	 * calculate SCL clock
	 * see
	 *	ICCCR
	 *
	 * ick	= clkp / (1 + CDF)
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * ick  : I2C internal clock < 20 MHz
	 * ticf : I2C SCL falling time  =  35 ns here
	 * tr   : I2C SCL rising  time  = 200 ns here
	 * intd : LSI internal delay    =  50 ns here
	 * clkp : peripheral_clk
	 * F[]  : integer up-valuation
	 */
	rate = clk_get_rate(priv->clk);
	cdf = rate / 20000000;
	if (cdf >= 1 << cdf_width) {
		dev_err(dev, "Input clock %lu too high\n", rate);
		return -EIO;
	}
	ick = rate / (cdf + 1);

	/*
	 * it is impossible to calculate large scale
	 * number on u32. separate it
	 *
	 * F[(ticf + tr + intd) * ick]
	 *  = F[(35 + 200 + 50)ns * ick]
	 *  = F[285 * ick / 1000000000]
	 *  = F[(ick / 1000000) * 285 / 1000]
	 */
	round = (ick + 500000) / 1000000 * 285;
	round = (round + 500) / 1000;

	/*
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * Calculation result (= SCL) should be less than
	 * bus_speed for hardware safety
	 *
	 * We could use something along the lines of
	 *	div = ick / (bus_speed + 1) + 1;
	 *	scgd = (div - 20 - round + 7) / 8;
	 *	scl = ick / (20 + (scgd * 8) + round);
	 * (not fully verified) but that would get pretty involved
	 */
	for (scgd = 0; scgd < 0x40; scgd++) {
		scl = ick / (20 + (scgd * 8) + round);
		if (scl <= bus_speed)
			goto scgd_find;
	}
	dev_err(dev, "it is impossible to calculate best SCL\n");
	return -EIO;

scgd_find:
	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
		scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);

	/*
	 * keep icccr value
	 */
	priv->icccr = scgd << cdf_width | cdf;

	return 0;
}

static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
{
	int read = !!rcar_i2c_is_recv(priv);

	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
	rcar_i2c_write(priv, ICMSR, 0);
	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
	rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);

	return 0;
}

/*
 *		interrupt functions
 */
static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDE))
		return 0;

	/*
	 * If address transfer phase finished,
	 * goto data phase.
	 */
	if (msr & MAT)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	if (priv->pos < msg->len) {
		/*
		 * Prepare next data to ICRXTX register.
		 * This data will go to _SHIFT_ register.
		 *
		 *    *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */
		rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
		priv->pos++;

	} else {
		/*
		 * The last data was pushed to ICRXTX on _PREV_ empty irq.
		 * It is on _SHIFT_ register, and will sent to I2C bus.
		 *
		 *		  *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */

		if (priv->flags & ID_LAST_MSG)
			/*
			 * If current msg is the _LAST_ msg,
			 * prepare stop condition here.
			 * ID_DONE will be set on STOP irq.
			 */
			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		else
			/*
			 * If current msg is _NOT_ last msg,
			 * it doesn't call stop phase.
			 * thus, there is no STOP irq.
			 * return ID_DONE here.
			 */
			return ID_DONE;
	}

	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);

	return 0;
}

static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDR))
		return 0;

	if (msr & MAT) {
		/*
		 * Address transfer phase finished,
		 * but, there is no data at this point.
		 * Do nothing.
		 */
	} else if (priv->pos < msg->len) {
		/*
		 * get received data
		 */
		msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
		priv->pos++;
	}

	/*
	 * If next received data is the _LAST_,
	 * go to STOP phase,
	 * otherwise, go to DATA phase.
	 */
	if (priv->pos + 1 >= msg->len)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
	else
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);

	return 0;
}

static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
{
	struct rcar_i2c_priv *priv = ptr;
	u32 msr;

	msr = rcar_i2c_read(priv, ICMSR);

	/* Arbitration lost */
	if (msr & MAL) {
		rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
		goto out;
	}

	/* Stop */
	if (msr & MST) {
		rcar_i2c_flags_set(priv, ID_DONE);
		goto out;
	}

	/* Nack */
	if (msr & MNR) {
		/* go to stop phase */
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
		rcar_i2c_flags_set(priv, ID_NACK);
		goto out;
	}

	if (rcar_i2c_is_recv(priv))
		rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	else
		rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));

out:
	if (rcar_i2c_flags_has(priv, ID_DONE)) {
		rcar_i2c_write(priv, ICMIER, 0);
		rcar_i2c_write(priv, ICMSR, 0);
		wake_up(&priv->wait);
	}

	return IRQ_HANDLED;
}

static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
				struct i2c_msg *msgs,
				int num)
{
	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	struct device *dev = rcar_i2c_priv_to_dev(priv);
	int i, ret, timeout;

	pm_runtime_get_sync(dev);

	rcar_i2c_init(priv);
	/* start clock */
	rcar_i2c_write(priv, ICCCR, priv->icccr);

	ret = rcar_i2c_bus_barrier(priv);
	if (ret < 0)
		goto out;

	for (i = 0; i < num; i++) {
		/* This HW can't send STOP after address phase */
		if (msgs[i].len == 0) {
			ret = -EOPNOTSUPP;
			break;
		}

		/* init each data */
		priv->msg	= &msgs[i];
		priv->pos	= 0;
		priv->flags	= 0;
		if (priv->msg == &msgs[num - 1])
			rcar_i2c_flags_set(priv, ID_LAST_MSG);

		ret = rcar_i2c_prepare_msg(priv);

		if (ret < 0)
			break;

		timeout = wait_event_timeout(priv->wait,
					     rcar_i2c_flags_has(priv, ID_DONE),
					     5 * HZ);
		if (!timeout) {
			ret = -ETIMEDOUT;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_NACK)) {
			ret = -ENXIO;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
			ret = -EAGAIN;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
			ret = -EIO;
			break;
		}

		ret = i + 1; /* The number of transfer */
	}
out:
	pm_runtime_put(dev);

	if (ret < 0 && ret != -ENXIO)
		dev_err(dev, "error %d : %x\n", ret, priv->flags);

	return ret;
}

static u32 rcar_i2c_func(struct i2c_adapter *adap)
{
	/* This HW can't do SMBUS_QUICK and NOSTART */
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
}

static const struct i2c_algorithm rcar_i2c_algo = {
	.master_xfer	= rcar_i2c_master_xfer,
	.functionality	= rcar_i2c_func,
};

static const struct of_device_id rcar_i2c_dt_ids[] = {
	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);

static int rcar_i2c_probe(struct platform_device *pdev)
{
	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct rcar_i2c_priv *priv;
	struct i2c_adapter *adap;
	struct resource *res;
	struct device *dev = &pdev->dev;
	u32 bus_speed;
	int irq, ret;

	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "cannot get clock\n");
		return PTR_ERR(priv->clk);
	}

	bus_speed = 100000; /* default 100 kHz */
	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
	if (ret < 0 && pdata && pdata->bus_speed)
		bus_speed = pdata->bus_speed;

	if (pdev->dev.of_node)
		priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
						      dev)->data;
	else
		priv->devtype = platform_get_device_id(pdev)->driver_data;

	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	if (ret < 0)
		return ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->io = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->io))
		return PTR_ERR(priv->io);

	irq = platform_get_irq(pdev, 0);
	init_waitqueue_head(&priv->wait);

	adap = &priv->adap;
	adap->nr = pdev->id;
	adap->algo = &rcar_i2c_algo;
	adap->class = I2C_CLASS_DEPRECATED;
	adap->retries = 3;
	adap->dev.parent = dev;
	adap->dev.of_node = dev->of_node;
	i2c_set_adapdata(adap, priv);
	strlcpy(adap->name, pdev->name, sizeof(adap->name));

	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
			       dev_name(dev), priv);
	if (ret < 0) {
		dev_err(dev, "cannot get irq %d\n", irq);
		return ret;
	}

	ret = i2c_add_numbered_adapter(adap);
	if (ret < 0) {
		dev_err(dev, "reg adap failed: %d\n", ret);
		return ret;
	}

	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, priv);

	dev_info(dev, "probed\n");

	return 0;
}

static int rcar_i2c_remove(struct platform_device *pdev)
{
	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;

	i2c_del_adapter(&priv->adap);
	pm_runtime_disable(dev);

	return 0;
}

static struct platform_device_id rcar_i2c_id_table[] = {
	{ "i2c-rcar",		I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen1",	I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen2",	I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);

static struct platform_driver rcar_i2c_driver = {
	.driver	= {
		.name	= "i2c-rcar",
		.owner	= THIS_MODULE,
		.of_match_table = rcar_i2c_dt_ids,
	},
	.probe		= rcar_i2c_probe,
	.remove		= rcar_i2c_remove,
	.id_table	= rcar_i2c_id_table,
};

module_platform_driver(rcar_i2c_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Commit	Line	Data
6ccbe607	1	/*
3d99beab	2	* Driver for the Renesas RCar I2C unit
6ccbe607	3	*
3d99beab WS	4	* Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
	5	*
	6	* Copyright (C) 2012-14 Renesas Solutions Corp.
6ccbe607 KM	7	* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	8	*
	9	* This file is based on the drivers/i2c/busses/i2c-sh7760.c
	10	* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
	11	*
	12	* This file used out-of-tree driver i2c-rcar.c
	13	* Copyright (C) 2011-2012 Renesas Electronics Corporation
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License as published by
3d99beab	17	* the Free Software Foundation; version 2 of the License.
6ccbe607 KM	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
6ccbe607 KM	23	*/
	24	#include <linux/clk.h>
	25	#include <linux/delay.h>
	26	#include <linux/err.h>
6ccbe607 KM	27	#include <linux/interrupt.h>
	28	#include <linux/io.h>
	29	#include <linux/i2c.h>
	30	#include <linux/i2c/i2c-rcar.h>
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
7679c0e1	33	#include <linux/of_device.h>
6ccbe607 KM	34	#include <linux/platform_device.h>
	35	#include <linux/pm_runtime.h>
	36	#include <linux/slab.h>
6ccbe607 KM	37
	38	/* register offsets */
	39	#define ICSCR 0x00 /* slave ctrl */
	40	#define ICMCR 0x04 /* master ctrl */
	41	#define ICSSR 0x08 /* slave status */
	42	#define ICMSR 0x0C /* master status */
	43	#define ICSIER 0x10 /* slave irq enable */
	44	#define ICMIER 0x14 /* master irq enable */
	45	#define ICCCR 0x18 /* clock dividers */
	46	#define ICSAR 0x1C /* slave address */
	47	#define ICMAR 0x20 /* master address */
	48	#define ICRXTX 0x24 /* data port */
	49
	50	/* ICMCR */
	51	#define MDBS (1 << 7) /* non-fifo mode switch */
	52	#define FSCL (1 << 6) /* override SCL pin */
	53	#define FSDA (1 << 5) /* override SDA pin */
	54	#define OBPC (1 << 4) /* override pins */
	55	#define MIE (1 << 3) /* master if enable */
	56	#define TSBE (1 << 2)
	57	#define FSB (1 << 1) /* force stop bit */
	58	#define ESG (1 << 0) /* en startbit gen */
	59
3e3aabac	60	/* ICMSR (also for ICMIE) */
6ccbe607 KM	61	#define MNR (1 << 6) /* nack received */
	62	#define MAL (1 << 5) /* arbitration lost */
	63	#define MST (1 << 4) /* sent a stop */
	64	#define MDE (1 << 3)
	65	#define MDT (1 << 2)
	66	#define MDR (1 << 1)
	67	#define MAT (1 << 0) /* slave addr xfer done */
	68
6ccbe607	69
4f443a8a WS	70	#define RCAR_BUS_PHASE_START (MDBS \| MIE \| ESG)
	71	#define RCAR_BUS_PHASE_DATA (MDBS \| MIE)
	72	#define RCAR_BUS_PHASE_STOP (MDBS \| MIE \| FSB)
6ccbe607	73
3e3aabac WS	74	#define RCAR_IRQ_SEND (MNR \| MAL \| MST \| MAT \| MDE)
	75	#define RCAR_IRQ_RECV (MNR \| MAL \| MST \| MAT \| MDR)
	76	#define RCAR_IRQ_STOP (MST)
6ccbe607	77
3c95de67 WS	78	#define RCAR_IRQ_ACK_SEND (~(MAT \| MDE))
	79	#define RCAR_IRQ_ACK_RECV (~(MAT \| MDR))
	80
6ccbe607 KM	81	#define ID_LAST_MSG (1 << 0)
	82	#define ID_IOERROR (1 << 1)
	83	#define ID_DONE (1 << 2)
	84	#define ID_ARBLOST (1 << 3)
	85	#define ID_NACK (1 << 4)
	86
b720423a	87	enum rcar_i2c_type {
043a3f11 KM	88	I2C_RCAR_GEN1,
043a3f11 KM	89	I2C_RCAR_GEN2,
b720423a NVD	90	};
b720423a NVD	91
6ccbe607 KM	92	struct rcar_i2c_priv {
	93	void __iomem *io;
	94	struct i2c_adapter adap;
	95	struct i2c_msg *msg;
bc8120f1	96	struct clk *clk;
6ccbe607	97
6ccbe607 KM	98	wait_queue_head_t wait;
	99
	100	int pos;
6ccbe607 KM	101	u32 icccr;
6ccbe607 KM	102	u32 flags;
51371cdc	103	enum rcar_i2c_type devtype;
6ccbe607 KM	104	};
	105
	106	#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
	107	#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
	108
	109	#define rcar_i2c_flags_set(p, f) ((p)->flags \|= (f))
	110	#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
	111
	112	#define LOOP_TIMEOUT 1024
	113
51371cdc	114
6ccbe607 KM	115	static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
	116	{
	117	writel(val, priv->io + reg);
	118	}
	119
	120	static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
	121	{
	122	return readl(priv->io + reg);
	123	}
	124
	125	static void rcar_i2c_init(struct rcar_i2c_priv *priv)
	126	{
	127	/*
	128	* reset slave mode.
	129	* slave mode is not used on this driver
	130	*/
	131	rcar_i2c_write(priv, ICSIER, 0);
	132	rcar_i2c_write(priv, ICSAR, 0);
	133	rcar_i2c_write(priv, ICSCR, 0);
	134	rcar_i2c_write(priv, ICSSR, 0);
	135
	136	/* reset master mode */
	137	rcar_i2c_write(priv, ICMIER, 0);
	138	rcar_i2c_write(priv, ICMCR, 0);
	139	rcar_i2c_write(priv, ICMSR, 0);
	140	rcar_i2c_write(priv, ICMAR, 0);
	141	}
	142
6ccbe607 KM	143	static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
	144	{
	145	int i;
	146
	147	for (i = 0; i < LOOP_TIMEOUT; i++) {
	148	/* make sure that bus is not busy */
	149	if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
	150	return 0;
	151	udelay(1);
	152	}
	153
	154	return -EBUSY;
	155	}
	156
6ccbe607 KM	157	static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
	158	u32 bus_speed,
	159	struct device *dev)
	160	{
6ccbe607 KM	161	u32 scgd, cdf;
	162	u32 round, ick;
	163	u32 scl;
b720423a	164	u32 cdf_width;
8d049403	165	unsigned long rate;
6ccbe607	166
b720423a	167	switch (priv->devtype) {
043a3f11	168	case I2C_RCAR_GEN1:
b720423a NVD	169	cdf_width = 2;
b720423a NVD	170	break;
043a3f11	171	case I2C_RCAR_GEN2:
b720423a NVD	172	cdf_width = 3;
	173	break;
	174	default:
	175	dev_err(dev, "device type error\n");
	176	return -EIO;
	177	}
	178
6ccbe607 KM	179	/*
	180	* calculate SCL clock
	181	* see
	182	* ICCCR
	183	*
	184	* ick = clkp / (1 + CDF)
	185	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	186	*
	187	* ick : I2C internal clock < 20 MHz
	188	* ticf : I2C SCL falling time = 35 ns here
	189	* tr : I2C SCL rising time = 200 ns here
	190	* intd : LSI internal delay = 50 ns here
	191	* clkp : peripheral_clk
	192	* F[] : integer up-valuation
	193	*/
bc8120f1	194	rate = clk_get_rate(priv->clk);
8d049403 GL	195	cdf = rate / 20000000;
	196	if (cdf >= 1 << cdf_width) {
	197	dev_err(dev, "Input clock %lu too high\n", rate);
	198	return -EIO;
6ccbe607	199	}
8d049403	200	ick = rate / (cdf + 1);
6ccbe607	201
6ccbe607 KM	202	/*
	203	* it is impossible to calculate large scale
	204	* number on u32. separate it
	205	*
	206	* F[(ticf + tr + intd) * ick]
	207	* = F[(35 + 200 + 50)ns * ick]
	208	* = F[285 * ick / 1000000000]
	209	* = F[(ick / 1000000) * 285 / 1000]
	210	*/
	211	round = (ick + 500000) / 1000000 * 285;
	212	round = (round + 500) / 1000;
	213
	214	/*
	215	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	216	*
	217	* Calculation result (= SCL) should be less than
	218	* bus_speed for hardware safety
8d049403 GL	219	*
	220	* We could use something along the lines of
	221	* div = ick / (bus_speed + 1) + 1;
	222	* scgd = (div - 20 - round + 7) / 8;
	223	* scl = ick / (20 + (scgd * 8) + round);
	224	* (not fully verified) but that would get pretty involved
6ccbe607 KM	225	*/
	226	for (scgd = 0; scgd < 0x40; scgd++) {
	227	scl = ick / (20 + (scgd * 8) + round);
	228	if (scl <= bus_speed)
	229	goto scgd_find;
	230	}
	231	dev_err(dev, "it is impossible to calculate best SCL\n");
	232	return -EIO;
	233
	234	scgd_find:
	235	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
bc8120f1	236	scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
6ccbe607 KM	237
	238	/*
	239	* keep icccr value
	240	*/
14d32f17	241	priv->icccr = scgd << cdf_width \| cdf;
6ccbe607 KM	242
	243	return 0;
	244	}
	245
386babf8	246	static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
6ccbe607	247	{
386babf8	248	int read = !!rcar_i2c_is_recv(priv);
6ccbe607	249
386babf8	250	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) \| read);
3c95de67	251	rcar_i2c_write(priv, ICMSR, 0);
4f443a8a	252	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
386babf8	253	rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
6ccbe607 KM	254
	255	return 0;
	256	}
	257
6ccbe607 KM	258	/*
	259	* interrupt functions
	260	*/
	261	static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
	262	{
	263	struct i2c_msg *msg = priv->msg;
	264
	265	/*
	266	* FIXME
	267	* sometimes, unknown interrupt happened.
	268	* Do nothing
	269	*/
	270	if (!(msr & MDE))
	271	return 0;
	272
	273	/*
	274	* If address transfer phase finished,
	275	* goto data phase.
	276	*/
	277	if (msr & MAT)
4f443a8a	278	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607 KM	279
	280	if (priv->pos < msg->len) {
	281	/*
	282	* Prepare next data to ICRXTX register.
	283	* This data will go to _SHIFT_ register.
	284	*
	285	* *
	286	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	287	*/
	288	rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
	289	priv->pos++;
	290
	291	} else {
	292	/*
	293	* The last data was pushed to ICRXTX on _PREV_ empty irq.
	294	* It is on _SHIFT_ register, and will sent to I2C bus.
	295	*
	296	* *
	297	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	298	*/
	299
	300	if (priv->flags & ID_LAST_MSG)
	301	/*
	302	* If current msg is the _LAST_ msg,
	303	* prepare stop condition here.
	304	* ID_DONE will be set on STOP irq.
	305	*/
4f443a8a	306	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607 KM	307	else
	308	/*
	309	* If current msg is _NOT_ last msg,
	310	* it doesn't call stop phase.
	311	* thus, there is no STOP irq.
	312	* return ID_DONE here.
	313	*/
	314	return ID_DONE;
	315	}
	316
3c95de67	317	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
6ccbe607 KM	318
	319	return 0;
	320	}
	321
	322	static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
	323	{
	324	struct i2c_msg *msg = priv->msg;
	325
	326	/*
	327	* FIXME
	328	* sometimes, unknown interrupt happened.
	329	* Do nothing
	330	*/
	331	if (!(msr & MDR))
	332	return 0;
	333
	334	if (msr & MAT) {
	335	/*
	336	* Address transfer phase finished,
	337	* but, there is no data at this point.
	338	* Do nothing.
	339	*/
	340	} else if (priv->pos < msg->len) {
	341	/*
	342	* get received data
	343	*/
	344	msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
	345	priv->pos++;
	346	}
	347
	348	/*
	349	* If next received data is the _LAST_,
	350	* go to STOP phase,
	351	* otherwise, go to DATA phase.
	352	*/
	353	if (priv->pos + 1 >= msg->len)
4f443a8a	354	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607	355	else
4f443a8a	356	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607	357
3c95de67	358	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
6ccbe607 KM	359
	360	return 0;
	361	}
	362
	363	static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
	364	{
	365	struct rcar_i2c_priv *priv = ptr;
6ccbe607 KM	366	u32 msr;
6ccbe607 KM	367
1c176d53	368	msr = rcar_i2c_read(priv, ICMSR);
6ccbe607	369
51371cdc	370	/* Arbitration lost */
6ccbe607	371	if (msr & MAL) {
6ccbe607 KM	372	rcar_i2c_flags_set(priv, (ID_DONE \| ID_ARBLOST));
	373	goto out;
	374	}
	375
51371cdc	376	/* Stop */
6ccbe607	377	if (msr & MST) {
6ccbe607 KM	378	rcar_i2c_flags_set(priv, ID_DONE);
	379	goto out;
	380	}
	381
51371cdc	382	/* Nack */
6ccbe607	383	if (msr & MNR) {
6ccbe607	384	/* go to stop phase */
4f443a8a	385	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
f2382249	386	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
6ccbe607 KM	387	rcar_i2c_flags_set(priv, ID_NACK);
	388	goto out;
	389	}
	390
6ccbe607 KM	391	if (rcar_i2c_is_recv(priv))
	392	rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	393	else
	394	rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
	395
	396	out:
	397	if (rcar_i2c_flags_has(priv, ID_DONE)) {
f2382249	398	rcar_i2c_write(priv, ICMIER, 0);
3c95de67	399	rcar_i2c_write(priv, ICMSR, 0);
6ccbe607 KM	400	wake_up(&priv->wait);
	401	}
	402
6ccbe607 KM	403	return IRQ_HANDLED;
	404	}
	405
	406	static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
	407	struct i2c_msg *msgs,
	408	int num)
	409	{
	410	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	411	struct device *dev = rcar_i2c_priv_to_dev(priv);
6ccbe607 KM	412	int i, ret, timeout;
	413
	414	pm_runtime_get_sync(dev);
	415
6ccbe607	416	rcar_i2c_init(priv);
1c176d53 WS	417	/* start clock */
1c176d53 WS	418	rcar_i2c_write(priv, ICCCR, priv->icccr);
6ccbe607	419
3f7de22e WS	420	ret = rcar_i2c_bus_barrier(priv);
	421	if (ret < 0)
	422	goto out;
	423
6ccbe607	424	for (i = 0; i < num; i++) {
d7653964 WS	425	/* This HW can't send STOP after address phase */
	426	if (msgs[i].len == 0) {
	427	ret = -EOPNOTSUPP;
	428	break;
	429	}
	430
6ccbe607 KM	431	/* init each data */
	432	priv->msg = &msgs[i];
	433	priv->pos = 0;
	434	priv->flags = 0;
	435	if (priv->msg == &msgs[num - 1])
	436	rcar_i2c_flags_set(priv, ID_LAST_MSG);
	437
386babf8	438	ret = rcar_i2c_prepare_msg(priv);
6ccbe607	439
6ccbe607 KM	440	if (ret < 0)
	441	break;
	442
6ccbe607 KM	443	timeout = wait_event_timeout(priv->wait,
	444	rcar_i2c_flags_has(priv, ID_DONE),
	445	5 * HZ);
	446	if (!timeout) {
	447	ret = -ETIMEDOUT;
	448	break;
	449	}
	450
6ccbe607	451	if (rcar_i2c_flags_has(priv, ID_NACK)) {
6ff4b105	452	ret = -ENXIO;
6ccbe607 KM	453	break;
	454	}
	455
	456	if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
	457	ret = -EAGAIN;
	458	break;
	459	}
	460
	461	if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
	462	ret = -EIO;
	463	break;
	464	}
	465
	466	ret = i + 1; /* The number of transfer */
	467	}
3f7de22e	468	out:
6ccbe607 KM	469	pm_runtime_put(dev);
6ccbe607 KM	470
6ff4b105	471	if (ret < 0 && ret != -ENXIO)
6ccbe607 KM	472	dev_err(dev, "error %d : %x\n", ret, priv->flags);
	473
	474	return ret;
	475	}
	476
	477	static u32 rcar_i2c_func(struct i2c_adapter *adap)
	478	{
d7653964 WS	479	/* This HW can't do SMBUS_QUICK and NOSTART */
d7653964 WS	480	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
6ccbe607 KM	481	}
	482
	483	static const struct i2c_algorithm rcar_i2c_algo = {
	484	.master_xfer = rcar_i2c_master_xfer,
	485	.functionality = rcar_i2c_func,
	486	};
	487
7679c0e1	488	static const struct of_device_id rcar_i2c_dt_ids[] = {
043a3f11 KM	489	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	490	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	491	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	492	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
e8936455	493	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
819a3951 WS	494	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	495	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	496	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
7679c0e1 GL	497	{},
	498	};
	499	MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
	500
0b255e92	501	static int rcar_i2c_probe(struct platform_device *pdev)
6ccbe607	502	{
6d4028c6	503	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
6ccbe607 KM	504	struct rcar_i2c_priv *priv;
	505	struct i2c_adapter *adap;
	506	struct resource *res;
	507	struct device *dev = &pdev->dev;
	508	u32 bus_speed;
93e953d3	509	int irq, ret;
6ccbe607	510
6ccbe607	511	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
46797a2a	512	if (!priv)
6ccbe607	513	return -ENOMEM;
6ccbe607	514
bc8120f1 BD	515	priv->clk = devm_clk_get(dev, NULL);
	516	if (IS_ERR(priv->clk)) {
	517	dev_err(dev, "cannot get clock\n");
	518	return PTR_ERR(priv->clk);
	519	}
	520
6ccbe607	521	bus_speed = 100000; /* default 100 kHz */
7679c0e1 GL	522	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
7679c0e1 GL	523	if (ret < 0 && pdata && pdata->bus_speed)
6ccbe607	524	bus_speed = pdata->bus_speed;
b720423a	525
7679c0e1 GL	526	if (pdev->dev.of_node)
	527	priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
	528	dev)->data;
	529	else
	530	priv->devtype = platform_get_device_id(pdev)->driver_data;
b720423a	531
6ccbe607 KM	532	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	533	if (ret < 0)
	534	return ret;
	535
3cc2d009	536	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	537	priv->io = devm_ioremap_resource(dev, res);
	538	if (IS_ERR(priv->io))
	539	return PTR_ERR(priv->io);
6ccbe607	540
93e953d3	541	irq = platform_get_irq(pdev, 0);
6ccbe607	542	init_waitqueue_head(&priv->wait);
6ccbe607	543
929e3aba WS	544	adap = &priv->adap;
	545	adap->nr = pdev->id;
	546	adap->algo = &rcar_i2c_algo;
	547	adap->class = I2C_CLASS_DEPRECATED;
	548	adap->retries = 3;
	549	adap->dev.parent = dev;
	550	adap->dev.of_node = dev->of_node;
6ccbe607 KM	551	i2c_set_adapdata(adap, priv);
	552	strlcpy(adap->name, pdev->name, sizeof(adap->name));
	553
93e953d3	554	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
6ccbe607 KM	555	dev_name(dev), priv);
6ccbe607 KM	556	if (ret < 0) {
93e953d3	557	dev_err(dev, "cannot get irq %d\n", irq);
6ccbe607 KM	558	return ret;
	559	}
	560
	561	ret = i2c_add_numbered_adapter(adap);
	562	if (ret < 0) {
	563	dev_err(dev, "reg adap failed: %d\n", ret);
	564	return ret;
	565	}
	566
	567	pm_runtime_enable(dev);
	568	platform_set_drvdata(pdev, priv);
	569
	570	dev_info(dev, "probed\n");
	571
	572	return 0;
	573	}
	574
0b255e92	575	static int rcar_i2c_remove(struct platform_device *pdev)
6ccbe607 KM	576	{
	577	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	578	struct device *dev = &pdev->dev;
	579
	580	i2c_del_adapter(&priv->adap);
	581	pm_runtime_disable(dev);
	582
	583	return 0;
	584	}
	585
b720423a	586	static struct platform_device_id rcar_i2c_id_table[] = {
043a3f11 KM	587	{ "i2c-rcar", I2C_RCAR_GEN1 },
	588	{ "i2c-rcar_gen1", I2C_RCAR_GEN1 },
	589	{ "i2c-rcar_gen2", I2C_RCAR_GEN2 },
b720423a NVD	590	{},
	591	};
	592	MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
	593
45fd5e4a	594	static struct platform_driver rcar_i2c_driver = {
6ccbe607 KM	595	.driver = {
	596	.name = "i2c-rcar",
	597	.owner = THIS_MODULE,
7679c0e1	598	.of_match_table = rcar_i2c_dt_ids,
6ccbe607 KM	599	},
6ccbe607 KM	600	.probe = rcar_i2c_probe,
0b255e92	601	.remove = rcar_i2c_remove,
b720423a	602	.id_table = rcar_i2c_id_table,
6ccbe607 KM	603	};
6ccbe607 KM	604
45fd5e4a	605	module_platform_driver(rcar_i2c_driver);
6ccbe607	606
3d99beab	607	MODULE_LICENSE("GPL v2");
6ccbe607 KM	608	MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
6ccbe607 KM	609	MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");