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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c-id.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/interrupt.h> | |
1da177e4 LT |
31 | #include <linux/delay.h> |
32 | #include <linux/errno.h> | |
33 | #include <linux/err.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/irq.h> |
39 | #include <asm/io.h> | |
40 | ||
9498cb79 BD |
41 | #include <plat/regs-iic.h> |
42 | #include <plat/iic.h> | |
1da177e4 LT |
43 | |
44 | /* i2c controller state */ | |
45 | ||
46 | enum s3c24xx_i2c_state { | |
47 | STATE_IDLE, | |
48 | STATE_START, | |
49 | STATE_READ, | |
50 | STATE_WRITE, | |
51 | STATE_STOP | |
52 | }; | |
53 | ||
54 | struct s3c24xx_i2c { | |
55 | spinlock_t lock; | |
56 | wait_queue_head_t wait; | |
be44f01e | 57 | unsigned int suspended:1; |
1da177e4 LT |
58 | |
59 | struct i2c_msg *msg; | |
60 | unsigned int msg_num; | |
61 | unsigned int msg_idx; | |
62 | unsigned int msg_ptr; | |
63 | ||
e00a8cdf | 64 | unsigned int tx_setup; |
e0d1ec97 | 65 | unsigned int irq; |
e00a8cdf | 66 | |
1da177e4 | 67 | enum s3c24xx_i2c_state state; |
61c7cff8 | 68 | unsigned long clkrate; |
1da177e4 LT |
69 | |
70 | void __iomem *regs; | |
71 | struct clk *clk; | |
72 | struct device *dev; | |
1da177e4 LT |
73 | struct resource *ioarea; |
74 | struct i2c_adapter adap; | |
61c7cff8 BD |
75 | |
76 | #ifdef CONFIG_CPU_FREQ | |
77 | struct notifier_block freq_transition; | |
78 | #endif | |
1da177e4 LT |
79 | }; |
80 | ||
6a039cab | 81 | /* default platform data removed, dev should always carry data. */ |
1da177e4 LT |
82 | |
83 | /* s3c24xx_i2c_is2440() | |
84 | * | |
85 | * return true is this is an s3c2440 | |
86 | */ | |
87 | ||
88 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
89 | { | |
90 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
91 | ||
92 | return !strcmp(pdev->name, "s3c2440-i2c"); | |
93 | } | |
94 | ||
1da177e4 LT |
95 | /* s3c24xx_i2c_master_complete |
96 | * | |
97 | * complete the message and wake up the caller, using the given return code, | |
98 | * or zero to mean ok. | |
99 | */ | |
100 | ||
101 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
102 | { | |
103 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
104 | ||
105 | i2c->msg_ptr = 0; | |
106 | i2c->msg = NULL; | |
3d0911bf | 107 | i2c->msg_idx++; |
1da177e4 LT |
108 | i2c->msg_num = 0; |
109 | if (ret) | |
110 | i2c->msg_idx = ret; | |
111 | ||
112 | wake_up(&i2c->wait); | |
113 | } | |
114 | ||
115 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
116 | { | |
117 | unsigned long tmp; | |
3d0911bf | 118 | |
1da177e4 LT |
119 | tmp = readl(i2c->regs + S3C2410_IICCON); |
120 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
121 | } |
122 | ||
123 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
124 | { | |
125 | unsigned long tmp; | |
3d0911bf | 126 | |
1da177e4 LT |
127 | tmp = readl(i2c->regs + S3C2410_IICCON); |
128 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
129 | } |
130 | ||
131 | /* irq enable/disable functions */ | |
132 | ||
133 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
134 | { | |
135 | unsigned long tmp; | |
3d0911bf | 136 | |
1da177e4 LT |
137 | tmp = readl(i2c->regs + S3C2410_IICCON); |
138 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
139 | } | |
140 | ||
141 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
142 | { | |
143 | unsigned long tmp; | |
3d0911bf | 144 | |
1da177e4 LT |
145 | tmp = readl(i2c->regs + S3C2410_IICCON); |
146 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
147 | } | |
148 | ||
149 | ||
150 | /* s3c24xx_i2c_message_start | |
151 | * | |
3d0911bf | 152 | * put the start of a message onto the bus |
1da177e4 LT |
153 | */ |
154 | ||
3d0911bf | 155 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
156 | struct i2c_msg *msg) |
157 | { | |
158 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
159 | unsigned long stat; | |
160 | unsigned long iiccon; | |
161 | ||
162 | stat = 0; | |
163 | stat |= S3C2410_IICSTAT_TXRXEN; | |
164 | ||
165 | if (msg->flags & I2C_M_RD) { | |
166 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
167 | addr |= 1; | |
168 | } else | |
169 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
170 | ||
171 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
172 | addr ^= 1; | |
173 | ||
3d0911bf | 174 | /* todo - check for wether ack wanted or not */ |
1da177e4 LT |
175 | s3c24xx_i2c_enable_ack(i2c); |
176 | ||
177 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
178 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 179 | |
1da177e4 LT |
180 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
181 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 182 | |
e00a8cdf BD |
183 | /* delay here to ensure the data byte has gotten onto the bus |
184 | * before the transaction is started */ | |
185 | ||
186 | ndelay(i2c->tx_setup); | |
187 | ||
1da177e4 LT |
188 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
189 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
190 | |
191 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
192 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
193 | } | |
194 | ||
195 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
196 | { | |
197 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
198 | ||
199 | dev_dbg(i2c->dev, "STOP\n"); | |
200 | ||
201 | /* stop the transfer */ | |
3d0911bf | 202 | iicstat &= ~S3C2410_IICSTAT_START; |
1da177e4 | 203 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 204 | |
1da177e4 | 205 | i2c->state = STATE_STOP; |
3d0911bf | 206 | |
1da177e4 LT |
207 | s3c24xx_i2c_master_complete(i2c, ret); |
208 | s3c24xx_i2c_disable_irq(i2c); | |
209 | } | |
210 | ||
211 | /* helper functions to determine the current state in the set of | |
212 | * messages we are sending */ | |
213 | ||
214 | /* is_lastmsg() | |
215 | * | |
3d0911bf | 216 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
217 | */ |
218 | ||
219 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
220 | { | |
221 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
222 | } | |
223 | ||
224 | /* is_msglast | |
225 | * | |
226 | * returns TRUE if we this is the last byte in the current message | |
227 | */ | |
228 | ||
229 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
230 | { | |
231 | return i2c->msg_ptr == i2c->msg->len-1; | |
232 | } | |
233 | ||
234 | /* is_msgend | |
235 | * | |
236 | * returns TRUE if we reached the end of the current message | |
237 | */ | |
238 | ||
239 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
240 | { | |
241 | return i2c->msg_ptr >= i2c->msg->len; | |
242 | } | |
243 | ||
244 | /* i2s_s3c_irq_nextbyte | |
245 | * | |
246 | * process an interrupt and work out what to do | |
247 | */ | |
248 | ||
249 | static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |
250 | { | |
251 | unsigned long tmp; | |
252 | unsigned char byte; | |
253 | int ret = 0; | |
254 | ||
255 | switch (i2c->state) { | |
256 | ||
257 | case STATE_IDLE: | |
08882d20 | 258 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 LT |
259 | goto out; |
260 | break; | |
261 | ||
262 | case STATE_STOP: | |
08882d20 | 263 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 264 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
265 | goto out_ack; |
266 | ||
267 | case STATE_START: | |
268 | /* last thing we did was send a start condition on the | |
269 | * bus, or started a new i2c message | |
270 | */ | |
3d0911bf | 271 | |
63f5c289 | 272 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
273 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
274 | /* ack was not received... */ | |
275 | ||
276 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 277 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
278 | goto out_ack; |
279 | } | |
280 | ||
281 | if (i2c->msg->flags & I2C_M_RD) | |
282 | i2c->state = STATE_READ; | |
283 | else | |
284 | i2c->state = STATE_WRITE; | |
285 | ||
286 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 287 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
288 | |
289 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
290 | s3c24xx_i2c_stop(i2c, 0); | |
291 | goto out_ack; | |
292 | } | |
293 | ||
294 | if (i2c->state == STATE_READ) | |
295 | goto prepare_read; | |
296 | ||
3d0911bf | 297 | /* fall through to the write state, as we will need to |
1da177e4 LT |
298 | * send a byte as well */ |
299 | ||
300 | case STATE_WRITE: | |
301 | /* we are writing data to the device... check for the | |
302 | * end of the message, and if so, work out what to do | |
303 | */ | |
304 | ||
2709781b BD |
305 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
306 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
307 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
308 | ||
309 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
310 | goto out_ack; | |
311 | } | |
312 | } | |
313 | ||
3d0911bf | 314 | retry_write: |
2709781b | 315 | |
1da177e4 LT |
316 | if (!is_msgend(i2c)) { |
317 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
318 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
319 | |
320 | /* delay after writing the byte to allow the | |
321 | * data setup time on the bus, as writing the | |
322 | * data to the register causes the first bit | |
323 | * to appear on SDA, and SCL will change as | |
324 | * soon as the interrupt is acknowledged */ | |
325 | ||
326 | ndelay(i2c->tx_setup); | |
327 | ||
1da177e4 LT |
328 | } else if (!is_lastmsg(i2c)) { |
329 | /* we need to go to the next i2c message */ | |
330 | ||
331 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
332 | ||
333 | i2c->msg_ptr = 0; | |
3d0911bf | 334 | i2c->msg_idx++; |
1da177e4 | 335 | i2c->msg++; |
3d0911bf | 336 | |
1da177e4 LT |
337 | /* check to see if we need to do another message */ |
338 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
339 | ||
340 | if (i2c->msg->flags & I2C_M_RD) { | |
341 | /* cannot do this, the controller | |
342 | * forces us to send a new START | |
343 | * when we change direction */ | |
344 | ||
345 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
346 | } | |
347 | ||
348 | goto retry_write; | |
349 | } else { | |
1da177e4 LT |
350 | /* send the new start */ |
351 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
352 | i2c->state = STATE_START; | |
353 | } | |
354 | ||
355 | } else { | |
356 | /* send stop */ | |
357 | ||
358 | s3c24xx_i2c_stop(i2c, 0); | |
359 | } | |
360 | break; | |
361 | ||
362 | case STATE_READ: | |
3d0911bf | 363 | /* we have a byte of data in the data register, do |
1da177e4 LT |
364 | * something with it, and then work out wether we are |
365 | * going to do any more read/write | |
366 | */ | |
367 | ||
1da177e4 LT |
368 | byte = readb(i2c->regs + S3C2410_IICDS); |
369 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
370 | ||
3d0911bf | 371 | prepare_read: |
1da177e4 LT |
372 | if (is_msglast(i2c)) { |
373 | /* last byte of buffer */ | |
374 | ||
375 | if (is_lastmsg(i2c)) | |
376 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 377 | |
1da177e4 LT |
378 | } else if (is_msgend(i2c)) { |
379 | /* ok, we've read the entire buffer, see if there | |
380 | * is anything else we need to do */ | |
381 | ||
382 | if (is_lastmsg(i2c)) { | |
383 | /* last message, send stop and complete */ | |
384 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
385 | ||
386 | s3c24xx_i2c_stop(i2c, 0); | |
387 | } else { | |
388 | /* go to the next transfer */ | |
389 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
390 | ||
391 | i2c->msg_ptr = 0; | |
392 | i2c->msg_idx++; | |
393 | i2c->msg++; | |
394 | } | |
395 | } | |
396 | ||
397 | break; | |
398 | } | |
399 | ||
400 | /* acknowlegde the IRQ and get back on with the work */ | |
401 | ||
402 | out_ack: | |
3d0911bf | 403 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
404 | tmp &= ~S3C2410_IICCON_IRQPEND; |
405 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
406 | out: | |
407 | return ret; | |
408 | } | |
409 | ||
410 | /* s3c24xx_i2c_irq | |
411 | * | |
412 | * top level IRQ servicing routine | |
413 | */ | |
414 | ||
7d12e780 | 415 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
416 | { |
417 | struct s3c24xx_i2c *i2c = dev_id; | |
418 | unsigned long status; | |
419 | unsigned long tmp; | |
420 | ||
421 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
422 | ||
423 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 424 | /* deal with arbitration loss */ |
1da177e4 LT |
425 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
426 | } | |
427 | ||
428 | if (i2c->state == STATE_IDLE) { | |
429 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
430 | ||
3d0911bf | 431 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
432 | tmp &= ~S3C2410_IICCON_IRQPEND; |
433 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
434 | goto out; | |
435 | } | |
3d0911bf | 436 | |
1da177e4 LT |
437 | /* pretty much this leaves us with the fact that we've |
438 | * transmitted or received whatever byte we last sent */ | |
439 | ||
440 | i2s_s3c_irq_nextbyte(i2c, status); | |
441 | ||
442 | out: | |
443 | return IRQ_HANDLED; | |
444 | } | |
445 | ||
446 | ||
447 | /* s3c24xx_i2c_set_master | |
448 | * | |
449 | * get the i2c bus for a master transaction | |
450 | */ | |
451 | ||
452 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
453 | { | |
454 | unsigned long iicstat; | |
455 | int timeout = 400; | |
456 | ||
457 | while (timeout-- > 0) { | |
458 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 459 | |
1da177e4 LT |
460 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
461 | return 0; | |
462 | ||
463 | msleep(1); | |
464 | } | |
465 | ||
1da177e4 LT |
466 | return -ETIMEDOUT; |
467 | } | |
468 | ||
469 | /* s3c24xx_i2c_doxfer | |
470 | * | |
471 | * this starts an i2c transfer | |
472 | */ | |
473 | ||
3d0911bf BD |
474 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
475 | struct i2c_msg *msgs, int num) | |
1da177e4 LT |
476 | { |
477 | unsigned long timeout; | |
478 | int ret; | |
479 | ||
be44f01e | 480 | if (i2c->suspended) |
61c7cff8 BD |
481 | return -EIO; |
482 | ||
1da177e4 LT |
483 | ret = s3c24xx_i2c_set_master(i2c); |
484 | if (ret != 0) { | |
485 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
486 | ret = -EAGAIN; | |
487 | goto out; | |
488 | } | |
489 | ||
490 | spin_lock_irq(&i2c->lock); | |
491 | ||
492 | i2c->msg = msgs; | |
493 | i2c->msg_num = num; | |
494 | i2c->msg_ptr = 0; | |
495 | i2c->msg_idx = 0; | |
496 | i2c->state = STATE_START; | |
497 | ||
498 | s3c24xx_i2c_enable_irq(i2c); | |
499 | s3c24xx_i2c_message_start(i2c, msgs); | |
500 | spin_unlock_irq(&i2c->lock); | |
3d0911bf | 501 | |
1da177e4 LT |
502 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
503 | ||
504 | ret = i2c->msg_idx; | |
505 | ||
3d0911bf | 506 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
507 | * noisy when doing an i2cdetect */ |
508 | ||
509 | if (timeout == 0) | |
510 | dev_dbg(i2c->dev, "timeout\n"); | |
511 | else if (ret != num) | |
512 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
513 | ||
514 | /* ensure the stop has been through the bus */ | |
515 | ||
516 | msleep(1); | |
517 | ||
518 | out: | |
519 | return ret; | |
520 | } | |
521 | ||
522 | /* s3c24xx_i2c_xfer | |
523 | * | |
524 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 525 | * transferring across the i2c bus. |
1da177e4 LT |
526 | */ |
527 | ||
528 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
529 | struct i2c_msg *msgs, int num) | |
530 | { | |
531 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
532 | int retry; | |
533 | int ret; | |
534 | ||
535 | for (retry = 0; retry < adap->retries; retry++) { | |
536 | ||
537 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
538 | ||
539 | if (ret != -EAGAIN) | |
540 | return ret; | |
541 | ||
542 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
543 | ||
544 | udelay(100); | |
545 | } | |
546 | ||
547 | return -EREMOTEIO; | |
548 | } | |
549 | ||
550 | /* declare our i2c functionality */ | |
551 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
552 | { | |
553 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
554 | } | |
555 | ||
556 | /* i2c bus registration info */ | |
557 | ||
8f9082c5 | 558 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
559 | .master_xfer = s3c24xx_i2c_xfer, |
560 | .functionality = s3c24xx_i2c_func, | |
561 | }; | |
562 | ||
1da177e4 LT |
563 | /* s3c24xx_i2c_calcdivisor |
564 | * | |
565 | * return the divisor settings for a given frequency | |
566 | */ | |
567 | ||
568 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
569 | unsigned int *div1, unsigned int *divs) | |
570 | { | |
571 | unsigned int calc_divs = clkin / wanted; | |
572 | unsigned int calc_div1; | |
573 | ||
574 | if (calc_divs > (16*16)) | |
575 | calc_div1 = 512; | |
576 | else | |
577 | calc_div1 = 16; | |
578 | ||
579 | calc_divs += calc_div1-1; | |
580 | calc_divs /= calc_div1; | |
581 | ||
582 | if (calc_divs == 0) | |
583 | calc_divs = 1; | |
584 | if (calc_divs > 17) | |
585 | calc_divs = 17; | |
586 | ||
587 | *divs = calc_divs; | |
588 | *div1 = calc_div1; | |
589 | ||
590 | return clkin / (calc_divs * calc_div1); | |
591 | } | |
592 | ||
61c7cff8 | 593 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
594 | * |
595 | * work out a divisor for the user requested frequency setting, | |
596 | * either by the requested frequency, or scanning the acceptable | |
597 | * range of frequencies until something is found | |
598 | */ | |
599 | ||
61c7cff8 | 600 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 601 | { |
6a039cab | 602 | struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data; |
1da177e4 | 603 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 604 | unsigned int divs, div1; |
c564e6ae | 605 | unsigned long target_frequency; |
61c7cff8 | 606 | u32 iiccon; |
1da177e4 | 607 | int freq; |
1da177e4 | 608 | |
61c7cff8 | 609 | i2c->clkrate = clkin; |
1da177e4 | 610 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 611 | |
c564e6ae | 612 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 613 | |
c564e6ae | 614 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 615 | |
c564e6ae | 616 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 617 | |
c564e6ae | 618 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 619 | |
c564e6ae DS |
620 | if (freq > target_frequency) { |
621 | dev_err(i2c->dev, | |
622 | "Unable to achieve desired frequency %luKHz." \ | |
623 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
624 | return -EINVAL; | |
1da177e4 LT |
625 | } |
626 | ||
1da177e4 | 627 | *got = freq; |
61c7cff8 BD |
628 | |
629 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
630 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
631 | iiccon |= (divs-1); | |
632 | ||
633 | if (div1 == 512) | |
634 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
635 | ||
636 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
637 | ||
a192f715 BD |
638 | if (s3c24xx_i2c_is2440(i2c)) { |
639 | unsigned long sda_delay; | |
640 | ||
641 | if (pdata->sda_delay) { | |
642 | sda_delay = (freq / 1000) * pdata->sda_delay; | |
643 | sda_delay /= 1000000; | |
644 | sda_delay = DIV_ROUND_UP(sda_delay, 5); | |
645 | if (sda_delay > 3) | |
646 | sda_delay = 3; | |
647 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
648 | } else | |
649 | sda_delay = 0; | |
650 | ||
651 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
652 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
653 | } | |
654 | ||
61c7cff8 BD |
655 | return 0; |
656 | } | |
657 | ||
658 | #ifdef CONFIG_CPU_FREQ | |
659 | ||
660 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
661 | ||
662 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
663 | unsigned long val, void *data) | |
664 | { | |
665 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
666 | unsigned long flags; | |
667 | unsigned int got; | |
668 | int delta_f; | |
669 | int ret; | |
670 | ||
671 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
672 | ||
673 | /* if we're post-change and the input clock has slowed down | |
674 | * or at pre-change and the clock is about to speed up, then | |
675 | * adjust our clock rate. <0 is slow, >0 speedup. | |
676 | */ | |
677 | ||
678 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
679 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
680 | spin_lock_irqsave(&i2c->lock, flags); | |
681 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
682 | spin_unlock_irqrestore(&i2c->lock, flags); | |
683 | ||
684 | if (ret < 0) | |
685 | dev_err(i2c->dev, "cannot find frequency\n"); | |
686 | else | |
687 | dev_info(i2c->dev, "setting freq %d\n", got); | |
688 | } | |
689 | ||
1da177e4 LT |
690 | return 0; |
691 | } | |
692 | ||
61c7cff8 BD |
693 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
694 | { | |
695 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
696 | ||
697 | return cpufreq_register_notifier(&i2c->freq_transition, | |
698 | CPUFREQ_TRANSITION_NOTIFIER); | |
699 | } | |
700 | ||
701 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
702 | { | |
703 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
704 | CPUFREQ_TRANSITION_NOTIFIER); | |
705 | } | |
706 | ||
707 | #else | |
708 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
709 | { | |
1da177e4 LT |
710 | return 0; |
711 | } | |
712 | ||
61c7cff8 BD |
713 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
714 | { | |
715 | } | |
716 | #endif | |
717 | ||
1da177e4 LT |
718 | /* s3c24xx_i2c_init |
719 | * | |
3d0911bf | 720 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
721 | */ |
722 | ||
723 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
724 | { | |
725 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
726 | struct s3c2410_platform_i2c *pdata; | |
727 | unsigned int freq; | |
728 | ||
729 | /* get the plafrom data */ | |
730 | ||
6a039cab | 731 | pdata = i2c->dev->platform_data; |
1da177e4 LT |
732 | |
733 | /* inititalise the gpio */ | |
734 | ||
8be310a6 BD |
735 | if (pdata->cfg_gpio) |
736 | pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
1da177e4 LT |
737 | |
738 | /* write slave address */ | |
3d0911bf | 739 | |
1da177e4 LT |
740 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
741 | ||
742 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
743 | ||
61c7cff8 BD |
744 | writel(iicon, i2c->regs + S3C2410_IICCON); |
745 | ||
1da177e4 LT |
746 | /* we need to work out the divisors for the clock... */ |
747 | ||
61c7cff8 BD |
748 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
749 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
750 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
751 | return -EINVAL; | |
752 | } | |
753 | ||
754 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
755 | ||
756 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
757 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 LT |
758 | |
759 | /* check for s3c2440 i2c controller */ | |
760 | ||
a192f715 BD |
761 | if (s3c24xx_i2c_is2440(i2c)) |
762 | writel(0x0, i2c->regs + S3C2440_IICLC); | |
1da177e4 LT |
763 | |
764 | return 0; | |
765 | } | |
766 | ||
1da177e4 LT |
767 | /* s3c24xx_i2c_probe |
768 | * | |
769 | * called by the bus driver when a suitable device is found | |
770 | */ | |
771 | ||
3ae5eaec | 772 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 773 | { |
692acbd3 | 774 | struct s3c24xx_i2c *i2c; |
399dee23 | 775 | struct s3c2410_platform_i2c *pdata; |
1da177e4 LT |
776 | struct resource *res; |
777 | int ret; | |
778 | ||
6a039cab BD |
779 | pdata = pdev->dev.platform_data; |
780 | if (!pdata) { | |
781 | dev_err(&pdev->dev, "no platform data\n"); | |
782 | return -EINVAL; | |
783 | } | |
399dee23 | 784 | |
692acbd3 BD |
785 | i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
786 | if (!i2c) { | |
787 | dev_err(&pdev->dev, "no memory for state\n"); | |
788 | return -ENOMEM; | |
789 | } | |
790 | ||
791 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); | |
792 | i2c->adap.owner = THIS_MODULE; | |
793 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
794 | i2c->adap.retries = 2; | |
795 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
796 | i2c->tx_setup = 50; | |
797 | ||
798 | spin_lock_init(&i2c->lock); | |
799 | init_waitqueue_head(&i2c->wait); | |
399dee23 | 800 | |
1da177e4 LT |
801 | /* find the clock and enable it */ |
802 | ||
3ae5eaec RK |
803 | i2c->dev = &pdev->dev; |
804 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 805 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 806 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 807 | ret = -ENOENT; |
5b68790c | 808 | goto err_noclk; |
1da177e4 LT |
809 | } |
810 | ||
3ae5eaec | 811 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 812 | |
1da177e4 LT |
813 | clk_enable(i2c->clk); |
814 | ||
815 | /* map the registers */ | |
816 | ||
817 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
818 | if (res == NULL) { | |
3ae5eaec | 819 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 820 | ret = -ENOENT; |
5b68790c | 821 | goto err_clk; |
1da177e4 LT |
822 | } |
823 | ||
824 | i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1, | |
825 | pdev->name); | |
826 | ||
827 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 828 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 829 | ret = -ENXIO; |
5b68790c | 830 | goto err_clk; |
1da177e4 LT |
831 | } |
832 | ||
833 | i2c->regs = ioremap(res->start, (res->end-res->start)+1); | |
834 | ||
835 | if (i2c->regs == NULL) { | |
3ae5eaec | 836 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 837 | ret = -ENXIO; |
5b68790c | 838 | goto err_ioarea; |
1da177e4 LT |
839 | } |
840 | ||
3d0911bf BD |
841 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", |
842 | i2c->regs, i2c->ioarea, res); | |
1da177e4 LT |
843 | |
844 | /* setup info block for the i2c core */ | |
845 | ||
846 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 847 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
848 | |
849 | /* initialise the i2c controller */ | |
850 | ||
851 | ret = s3c24xx_i2c_init(i2c); | |
852 | if (ret != 0) | |
5b68790c | 853 | goto err_iomap; |
1da177e4 LT |
854 | |
855 | /* find the IRQ for this unit (note, this relies on the init call to | |
3d0911bf | 856 | * ensure no current IRQs pending |
1da177e4 LT |
857 | */ |
858 | ||
e0d1ec97 BD |
859 | i2c->irq = ret = platform_get_irq(pdev, 0); |
860 | if (ret <= 0) { | |
3ae5eaec | 861 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
5b68790c | 862 | goto err_iomap; |
1da177e4 LT |
863 | } |
864 | ||
e0d1ec97 BD |
865 | ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED, |
866 | dev_name(&pdev->dev), i2c); | |
1da177e4 LT |
867 | |
868 | if (ret != 0) { | |
e0d1ec97 | 869 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
5b68790c | 870 | goto err_iomap; |
1da177e4 LT |
871 | } |
872 | ||
61c7cff8 | 873 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 874 | if (ret < 0) { |
61c7cff8 | 875 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 876 | goto err_irq; |
1da177e4 LT |
877 | } |
878 | ||
399dee23 BD |
879 | /* Note, previous versions of the driver used i2c_add_adapter() |
880 | * to add the bus at any number. We now pass the bus number via | |
881 | * the platform data, so if unset it will now default to always | |
882 | * being bus 0. | |
883 | */ | |
884 | ||
885 | i2c->adap.nr = pdata->bus_num; | |
886 | ||
887 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 888 | if (ret < 0) { |
3ae5eaec | 889 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 890 | goto err_cpufreq; |
1da177e4 LT |
891 | } |
892 | ||
3ae5eaec | 893 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 894 | |
22e965c2 | 895 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
5b68790c | 896 | return 0; |
1da177e4 | 897 | |
61c7cff8 BD |
898 | err_cpufreq: |
899 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
900 | ||
5b68790c | 901 | err_irq: |
e0d1ec97 | 902 | free_irq(i2c->irq, i2c); |
5b68790c BD |
903 | |
904 | err_iomap: | |
905 | iounmap(i2c->regs); | |
906 | ||
907 | err_ioarea: | |
908 | release_resource(i2c->ioarea); | |
909 | kfree(i2c->ioarea); | |
910 | ||
911 | err_clk: | |
912 | clk_disable(i2c->clk); | |
913 | clk_put(i2c->clk); | |
1da177e4 | 914 | |
5b68790c | 915 | err_noclk: |
692acbd3 | 916 | kfree(i2c); |
1da177e4 LT |
917 | return ret; |
918 | } | |
919 | ||
920 | /* s3c24xx_i2c_remove | |
921 | * | |
922 | * called when device is removed from the bus | |
923 | */ | |
924 | ||
3ae5eaec | 925 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 926 | { |
3ae5eaec | 927 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 928 | |
61c7cff8 BD |
929 | s3c24xx_i2c_deregister_cpufreq(i2c); |
930 | ||
5b68790c | 931 | i2c_del_adapter(&i2c->adap); |
e0d1ec97 | 932 | free_irq(i2c->irq, i2c); |
5b68790c BD |
933 | |
934 | clk_disable(i2c->clk); | |
935 | clk_put(i2c->clk); | |
936 | ||
937 | iounmap(i2c->regs); | |
938 | ||
939 | release_resource(i2c->ioarea); | |
940 | kfree(i2c->ioarea); | |
692acbd3 | 941 | kfree(i2c); |
1da177e4 LT |
942 | |
943 | return 0; | |
944 | } | |
945 | ||
946 | #ifdef CONFIG_PM | |
be44f01e BD |
947 | static int s3c24xx_i2c_suspend_late(struct platform_device *dev, |
948 | pm_message_t msg) | |
949 | { | |
950 | struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); | |
951 | i2c->suspended = 1; | |
952 | return 0; | |
953 | } | |
954 | ||
3ae5eaec | 955 | static int s3c24xx_i2c_resume(struct platform_device *dev) |
1da177e4 | 956 | { |
3ae5eaec | 957 | struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); |
9480e307 | 958 | |
be44f01e BD |
959 | i2c->suspended = 0; |
960 | s3c24xx_i2c_init(i2c); | |
1da177e4 LT |
961 | |
962 | return 0; | |
963 | } | |
964 | ||
965 | #else | |
be44f01e | 966 | #define s3c24xx_i2c_suspend_late NULL |
1da177e4 LT |
967 | #define s3c24xx_i2c_resume NULL |
968 | #endif | |
969 | ||
970 | /* device driver for platform bus bits */ | |
971 | ||
3ae5eaec | 972 | static struct platform_driver s3c2410_i2c_driver = { |
1da177e4 LT |
973 | .probe = s3c24xx_i2c_probe, |
974 | .remove = s3c24xx_i2c_remove, | |
be44f01e | 975 | .suspend_late = s3c24xx_i2c_suspend_late, |
1da177e4 | 976 | .resume = s3c24xx_i2c_resume, |
3ae5eaec RK |
977 | .driver = { |
978 | .owner = THIS_MODULE, | |
979 | .name = "s3c2410-i2c", | |
980 | }, | |
1da177e4 LT |
981 | }; |
982 | ||
3ae5eaec | 983 | static struct platform_driver s3c2440_i2c_driver = { |
1da177e4 LT |
984 | .probe = s3c24xx_i2c_probe, |
985 | .remove = s3c24xx_i2c_remove, | |
be44f01e | 986 | .suspend_late = s3c24xx_i2c_suspend_late, |
1da177e4 | 987 | .resume = s3c24xx_i2c_resume, |
3ae5eaec RK |
988 | .driver = { |
989 | .owner = THIS_MODULE, | |
990 | .name = "s3c2440-i2c", | |
991 | }, | |
1da177e4 LT |
992 | }; |
993 | ||
994 | static int __init i2c_adap_s3c_init(void) | |
995 | { | |
996 | int ret; | |
997 | ||
3ae5eaec | 998 | ret = platform_driver_register(&s3c2410_i2c_driver); |
e32e28ed | 999 | if (ret == 0) { |
3ae5eaec | 1000 | ret = platform_driver_register(&s3c2440_i2c_driver); |
e32e28ed | 1001 | if (ret) |
3ae5eaec | 1002 | platform_driver_unregister(&s3c2410_i2c_driver); |
e32e28ed | 1003 | } |
1da177e4 LT |
1004 | |
1005 | return ret; | |
1006 | } | |
18dc83a6 | 1007 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1008 | |
1009 | static void __exit i2c_adap_s3c_exit(void) | |
1010 | { | |
3ae5eaec RK |
1011 | platform_driver_unregister(&s3c2410_i2c_driver); |
1012 | platform_driver_unregister(&s3c2440_i2c_driver); | |
1da177e4 | 1013 | } |
1da177e4 LT |
1014 | module_exit(i2c_adap_s3c_exit); |
1015 | ||
1016 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1017 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1018 | MODULE_LICENSE("GPL"); | |
add8eda7 | 1019 | MODULE_ALIAS("platform:s3c2410-i2c"); |
d150a4bb | 1020 | MODULE_ALIAS("platform:s3c2440-i2c"); |