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Merge branch 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / i2c / busses / i2c-sh_mobile.c
CommitLineData
da672773
MD		 1/*
2 * SuperH Mobile I2C Controller
3 *
2d09581b
WS		 4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
5 *
da672773
MD		 6 * Copyright (C) 2008 Magnus Damm
7 *
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
da672773
MD		 19 */
20
5bbe6879
WS		 21#include <linux/clk.h>
22#include <linux/delay.h>
2d09581b
WS		 23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
5bbe6879
WS		 25#include <linux/err.h>
26#include <linux/i2c.h>
27#include <linux/i2c/i2c-sh_mobile.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
da672773
MD		 31#include <linux/kernel.h>
32#include <linux/module.h>
5bbe6879 33#include <linux/of_device.h>
da672773 34#include <linux/platform_device.h>
f1a3b994 35#include <linux/pm_runtime.h>
5a0e3ad6 36#include <linux/slab.h>
da672773 37
4eb00c9f
MD		 38/* Transmit operation: */
39/* */
40/* 0 byte transmit */
e7890297 41/* BUS: S A8 ACK P(*) */
4eb00c9f
MD		 42/* IRQ: DTE WAIT */
43/* ICIC: */
44/* ICCR: 0x94 0x90 */
45/* ICDR: A8 */
46/* */
47/* 1 byte transmit */
e7890297 48/* BUS: S A8 ACK D8(1) ACK P(*) */
4eb00c9f
MD		 49/* IRQ: DTE WAIT WAIT */
50/* ICIC: -DTE */
51/* ICCR: 0x94 0x90 */
52/* ICDR: A8 D8(1) */
53/* */
54/* 2 byte transmit */
e7890297 55/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 56/* IRQ: DTE WAIT WAIT WAIT */
57/* ICIC: -DTE */
58/* ICCR: 0x94 0x90 */
59/* ICDR: A8 D8(1) D8(2) */
60/* */
61/* 3 bytes or more, +---------+ gets repeated */
62/* */
63/* */
64/* Receive operation: */
65/* */
66/* 0 byte receive - not supported since slave may hold SDA low */
67/* */
68/* 1 byte receive [TX] | [RX] */
e7890297 69/* BUS: S A8 ACK | D8(1) ACK P(*) */
4eb00c9f
MD		 70/* IRQ: DTE WAIT | WAIT DTE */
71/* ICIC: -DTE | +DTE */
72/* ICCR: 0x94 0x81 | 0xc0 */
73/* ICDR: A8 | D8(1) */
74/* */
75/* 2 byte receive [TX]| [RX] */
e7890297 76/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 77/* IRQ: DTE WAIT | WAIT WAIT DTE */
78/* ICIC: -DTE | +DTE */
79/* ICCR: 0x94 0x81 | 0xc0 */
80/* ICDR: A8 | D8(1) D8(2) */
81/* */
e7890297 82/* 3 byte receive [TX] | [RX] (*) */
4eb00c9f
MD		 83/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85/* ICIC: -DTE | +DTE */
86/* ICCR: 0x94 0x81 | 0xc0 */
87/* ICDR: A8 | D8(1) D8(2) D8(3) */
88/* */
89/* 4 bytes or more, this part is repeated +---------+ */
90/* */
91/* */
92/* Interrupt order and BUSY flag */
93/* ___ _ */
94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
96/* */
e7890297 97/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
4eb00c9f
MD		 98/* ___ */
99/* WAIT IRQ ________________________________/ \___________ */
100/* TACK IRQ ____________________________________/ \_______ */
101/* DTE IRQ __________________________________________/ \_ */
102/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103/* _______________________________________________ */
104/* BUSY __/ \_ */
105/* */
e7890297
GL		 106/* (*) The STOP condition is only sent by the master at the end of the last */
107/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108/* only cleared after the STOP condition, so, between messages we have to */
109/* poll for the DTE bit. */
110/* */
4eb00c9f 111
da672773
MD		 112enum sh_mobile_i2c_op {
113 OP_START = 0,
4eb00c9f
MD		 114 OP_TX_FIRST,
115 OP_TX,
da672773 116 OP_TX_STOP,
2d09581b 117 OP_TX_STOP_DATA,
da672773 118 OP_TX_TO_RX,
4eb00c9f 119 OP_RX,
da672773 120 OP_RX_STOP,
4eb00c9f 121 OP_RX_STOP_DATA,
da672773
MD		 122};
123
124struct sh_mobile_i2c_data {
125 struct device *dev;
126 void __iomem *reg;
127 struct i2c_adapter adap;
81f81153 128 unsigned long bus_speed;
ebd5ac16 129 unsigned int clks_per_count;
da672773 130 struct clk *clk;
962b6032 131 u_int8_t icic;
962b6032 132 u_int8_t flags;
23a61291
SK		 133 u_int16_t iccl;
134 u_int16_t icch;
da672773
MD		 135
136 spinlock_t lock;
137 wait_queue_head_t wait;
138 struct i2c_msg *msg;
139 int pos;
140 int sr;
e7890297 141 bool send_stop;
32e22409 142 bool stop_after_dma;
2d09581b 143
55f5f986 144 struct resource *res;
2d09581b
WS		 145 struct dma_chan *dma_tx;
146 struct dma_chan *dma_rx;
147 struct scatterlist sg;
148 enum dma_data_direction dma_direction;
da672773
MD		 149};
150
67240dfc
WS		 151struct sh_mobile_dt_config {
152 int clks_per_count;
153};
154
962b6032
MD		 155#define IIC_FLAG_HAS_ICIC67 (1 << 0)
156
23a61291
SK		 157#define STANDARD_MODE 100000
158#define FAST_MODE 400000
da672773
MD		 159
160/* Register offsets */
12a55f2d
MD		 161#define ICDR 0x00
162#define ICCR 0x04
163#define ICSR 0x08
164#define ICIC 0x0c
165#define ICCL 0x10
166#define ICCH 0x14
da672773
MD		 167
168/* Register bits */
169#define ICCR_ICE 0x80
170#define ICCR_RACK 0x40
171#define ICCR_TRS 0x10
172#define ICCR_BBSY 0x04
173#define ICCR_SCP 0x01
174
175#define ICSR_SCLM 0x80
176#define ICSR_SDAM 0x40
177#define SW_DONE 0x20
178#define ICSR_BUSY 0x10
179#define ICSR_AL 0x08
180#define ICSR_TACK 0x04
181#define ICSR_WAIT 0x02
182#define ICSR_DTE 0x01
183
962b6032
MD		 184#define ICIC_ICCLB8 0x80
185#define ICIC_ICCHB8 0x40
2d09581b
WS		 186#define ICIC_TDMAE 0x20
187#define ICIC_RDMAE 0x10
da672773
MD		 188#define ICIC_ALE 0x08
189#define ICIC_TACKE 0x04
190#define ICIC_WAITE 0x02
191#define ICIC_DTEE 0x01
192
12a55f2d
MD		 193static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
194{
962b6032
MD		 195 if (offs == ICIC)
196 data |= pd->icic;
197
12a55f2d
MD		 198 iowrite8(data, pd->reg + offs);
199}
200
201static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
202{
203 return ioread8(pd->reg + offs);
204}
205
206static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
207 unsigned char set, unsigned char clr)
208{
209 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
210}
211
ed4121e1 212static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
23a61291
SK		 213{
214 /*
215 * Conditional expression:
216 * ICCL >= COUNT_CLK * (tLOW + tf)
217 *
218 * SH-Mobile IIC hardware starts counting the LOW period of
219 * the SCL signal (tLOW) as soon as it pulls the SCL line.
220 * In order to meet the tLOW timing spec, we need to take into
221 * account the fall time of SCL signal (tf). Default tf value
222 * should be 0.3 us, for safety.
223 */
ed4121e1 224 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
23a61291
SK		 225}
226
ed4121e1 227static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
23a61291
SK		 228{
229 /*
230 * Conditional expression:
231 * ICCH >= COUNT_CLK * (tHIGH + tf)
232 *
233 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
234 * and can ignore it. SH-Mobile IIC controller starts counting
235 * the HIGH period of the SCL signal (tHIGH) after the SCL input
236 * voltage increases at VIH.
237 *
238 * Afterward it turned out calculating ICCH using only tHIGH spec
239 * will result in violation of the tHD;STA timing spec. We need
240 * to take into account the fall time of SDA signal (tf) at START
241 * condition, in order to meet both tHIGH and tHD;STA specs.
242 */
ed4121e1 243 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
23a61291
SK		 244}
245
6ed7053c 246static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
da672773 247{
23a61291
SK		 248 unsigned long i2c_clk_khz;
249 u32 tHIGH, tLOW, tf;
7663ebef 250 uint16_t max_val;
a5616bd0 251
a5616bd0 252 /* Get clock rate after clock is enabled */
f887605d 253 clk_prepare_enable(pd->clk);
23a61291 254 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
6ed7053c 255 clk_disable_unprepare(pd->clk);
ebd5ac16 256 i2c_clk_khz /= pd->clks_per_count;
23a61291
SK		 257
258 if (pd->bus_speed == STANDARD_MODE) {
259 tLOW = 47; /* tLOW = 4.7 us */
260 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
261 tf = 3; /* tf = 0.3 us */
23a61291
SK		 262 } else if (pd->bus_speed == FAST_MODE) {
263 tLOW = 13; /* tLOW = 1.3 us */
264 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
265 tf = 3; /* tf = 0.3 us */
23a61291
SK		 266 } else {
267 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
268 pd->bus_speed);
6ed7053c 269 return -EINVAL;
962b6032
MD		 270 }
271
ed4121e1 272 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
7663ebef
WS		 273 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
274
275 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
276 if (pd->iccl > max_val || pd->icch > max_val) {
277 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
278 pd->iccl, pd->icch);
279 return -EINVAL;
280 }
281
23a61291 282 /* one more bit of ICCL in ICIC */
7663ebef 283 if (pd->iccl & 0x100)
23a61291 284 pd->icic |= ICIC_ICCLB8;
a5616bd0 285 else
23a61291 286 pd->icic &= ~ICIC_ICCLB8;
a5616bd0 287
962b6032 288 /* one more bit of ICCH in ICIC */
7663ebef 289 if (pd->icch & 0x100)
23a61291
SK		 290 pd->icic |= ICIC_ICCHB8;
291 else
292 pd->icic &= ~ICIC_ICCHB8;
962b6032 293
7ca01864 294 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
6ed7053c 295 return 0;
7b0e6292
SK		 296}
297
298static void activate_ch(struct sh_mobile_i2c_data *pd)
299{
300 /* Wake up device and enable clock */
301 pm_runtime_get_sync(pd->dev);
f887605d 302 clk_prepare_enable(pd->clk);
7b0e6292 303
da672773 304 /* Enable channel and configure rx ack */
12a55f2d 305 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773
MD		 306
307 /* Mask all interrupts */
12a55f2d 308 iic_wr(pd, ICIC, 0);
da672773
MD		 309
310 /* Set the clock */
23a61291
SK		 311 iic_wr(pd, ICCL, pd->iccl & 0xff);
312 iic_wr(pd, ICCH, pd->icch & 0xff);
da672773
MD		 313}
314
315static void deactivate_ch(struct sh_mobile_i2c_data *pd)
316{
317 /* Clear/disable interrupts */
12a55f2d
MD		 318 iic_wr(pd, ICSR, 0);
319 iic_wr(pd, ICIC, 0);
da672773
MD		 320
321 /* Disable channel */
12a55f2d 322 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 323
f1a3b994 324 /* Disable clock and mark device as idle */
f887605d 325 clk_disable_unprepare(pd->clk);
f1a3b994 326 pm_runtime_put_sync(pd->dev);
da672773
MD		 327}
328
329static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
330 enum sh_mobile_i2c_op op, unsigned char data)
331{
332 unsigned char ret = 0;
333 unsigned long flags;
334
335 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
336
337 spin_lock_irqsave(&pd->lock, flags);
338
339 switch (op) {
4eb00c9f 340 case OP_START: /* issue start and trigger DTE interrupt */
a78f6a41 341 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
da672773 342 break;
4eb00c9f 343 case OP_TX_FIRST: /* disable DTE interrupt and write data */
12a55f2d
MD		 344 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
345 iic_wr(pd, ICDR, data);
da672773 346 break;
4eb00c9f 347 case OP_TX: /* write data */
12a55f2d 348 iic_wr(pd, ICDR, data);
da672773 349 break;
2d09581b 350 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
12a55f2d 351 iic_wr(pd, ICDR, data);
2d09581b
WS		 352 /* fallthrough */
353 case OP_TX_STOP: /* issue a stop */
a78f6a41
WS		 354 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
355 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
4eb00c9f
MD		 356 break;
357 case OP_TX_TO_RX: /* select read mode */
a78f6a41 358 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
da672773 359 break;
4eb00c9f 360 case OP_RX: /* just read data */
12a55f2d 361 ret = iic_rd(pd, ICDR);
da672773 362 break;
4eb00c9f 363 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
12a55f2d
MD		 364 iic_wr(pd, ICIC,
365 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
a78f6a41 366 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
4eb00c9f
MD		 367 break;
368 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
12a55f2d
MD		 369 iic_wr(pd, ICIC,
370 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
371 ret = iic_rd(pd, ICDR);
a78f6a41 372 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
da672773
MD		 373 break;
374 }
375
376 spin_unlock_irqrestore(&pd->lock, flags);
377
378 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
379 return ret;
380}
381
05cf9368 382static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 383{
05cf9368 384 return pd->pos == -1;
4eb00c9f
MD		 385}
386
05cf9368 387static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 388{
05cf9368 389 return pd->pos == pd->msg->len - 1;
4eb00c9f
MD		 390}
391
392static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
393 unsigned char *buf)
394{
395 switch (pd->pos) {
396 case -1:
397 *buf = (pd->msg->addr & 0x7f) << 1;
398 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
399 break;
400 default:
401 *buf = pd->msg->buf[pd->pos];
402 }
403}
404
405static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
406{
407 unsigned char data;
408
2d09581b
WS		 409 if (pd->pos == pd->msg->len) {
410 /* Send stop if we haven't yet (DMA case) */
32e22409 411 if (pd->send_stop && pd->stop_after_dma)
2d09581b 412 i2c_op(pd, OP_TX_STOP, 0);
4eb00c9f 413 return 1;
2d09581b 414 }
4eb00c9f
MD		 415
416 sh_mobile_i2c_get_data(pd, &data);
417
418 if (sh_mobile_i2c_is_last_byte(pd))
2d09581b 419 i2c_op(pd, OP_TX_STOP_DATA, data);
4eb00c9f
MD		 420 else if (sh_mobile_i2c_is_first_byte(pd))
421 i2c_op(pd, OP_TX_FIRST, data);
422 else
423 i2c_op(pd, OP_TX, data);
424
425 pd->pos++;
426 return 0;
427}
428
429static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
430{
431 unsigned char data;
432 int real_pos;
433
434 do {
435 if (pd->pos <= -1) {
436 sh_mobile_i2c_get_data(pd, &data);
437
438 if (sh_mobile_i2c_is_first_byte(pd))
439 i2c_op(pd, OP_TX_FIRST, data);
440 else
441 i2c_op(pd, OP_TX, data);
442 break;
443 }
444
445 if (pd->pos == 0) {
446 i2c_op(pd, OP_TX_TO_RX, 0);
447 break;
448 }
449
450 real_pos = pd->pos - 2;
451
452 if (pd->pos == pd->msg->len) {
32e22409
WS		 453 if (pd->stop_after_dma) {
454 /* Simulate PIO end condition after DMA transfer */
455 i2c_op(pd, OP_RX_STOP, 0);
456 pd->pos++;
457 break;
458 }
459
4eb00c9f
MD		 460 if (real_pos < 0) {
461 i2c_op(pd, OP_RX_STOP, 0);
462 break;
463 }
464 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
465 } else
466 data = i2c_op(pd, OP_RX, 0);
467
bff4056c
MD		 468 if (real_pos >= 0)
469 pd->msg->buf[real_pos] = data;
4eb00c9f
MD		 470 } while (0);
471
472 pd->pos++;
473 return pd->pos == (pd->msg->len + 2);
474}
475
da672773
MD		 476static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
477{
530834b1 478 struct sh_mobile_i2c_data *pd = dev_id;
4eb00c9f 479 unsigned char sr;
2d09581b 480 int wakeup = 0;
da672773 481
12a55f2d 482 sr = iic_rd(pd, ICSR);
4eb00c9f 483 pd->sr |= sr; /* remember state */
da672773
MD		 484
485 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
4eb00c9f
MD		 486 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
487 pd->pos, pd->msg->len);
da672773 488
2d09581b
WS		 489 /* Kick off TxDMA after preface was done */
490 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
491 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
492 else if (sr & (ICSR_AL | ICSR_TACK))
4eb00c9f 493 /* don't interrupt transaction - continue to issue stop */
12a55f2d 494 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
2d09581b 495 else if (pd->msg->flags & I2C_M_RD)
4eb00c9f
MD		 496 wakeup = sh_mobile_i2c_isr_rx(pd);
497 else
498 wakeup = sh_mobile_i2c_isr_tx(pd);
da672773 499
2d09581b
WS		 500 /* Kick off RxDMA after preface was done */
501 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
502 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
503
4eb00c9f 504 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
12a55f2d 505 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
da672773 506
da672773
MD		 507 if (wakeup) {
508 pd->sr |= SW_DONE;
509 wake_up(&pd->wait);
510 }
511
29fb08c3
SK		 512 /* defeat write posting to avoid spurious WAIT interrupts */
513 iic_rd(pd, ICSR);
514
da672773
MD		 515 return IRQ_HANDLED;
516}
517
8cfcae9f
WS		 518static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
519{
520 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
521 ? pd->dma_rx : pd->dma_tx;
522
523 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
524 pd->msg->len, pd->dma_direction);
525
526 pd->dma_direction = DMA_NONE;
527}
528
2d09581b
WS		 529static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
530{
531 if (pd->dma_direction == DMA_NONE)
532 return;
533 else if (pd->dma_direction == DMA_FROM_DEVICE)
534 dmaengine_terminate_all(pd->dma_rx);
535 else if (pd->dma_direction == DMA_TO_DEVICE)
536 dmaengine_terminate_all(pd->dma_tx);
537
8cfcae9f 538 sh_mobile_i2c_dma_unmap(pd);
2d09581b
WS		 539}
540
541static void sh_mobile_i2c_dma_callback(void *data)
542{
543 struct sh_mobile_i2c_data *pd = data;
544
8cfcae9f 545 sh_mobile_i2c_dma_unmap(pd);
2d09581b 546 pd->pos = pd->msg->len;
32e22409 547 pd->stop_after_dma = true;
2d09581b
WS		 548
549 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
550}
551
55f5f986
WS		 552static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
553 enum dma_transfer_direction dir, dma_addr_t port_addr)
554{
555 struct dma_chan *chan;
556 struct dma_slave_config cfg;
557 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
558 int ret;
559
560 chan = dma_request_slave_channel_reason(dev, chan_name);
561 if (IS_ERR(chan)) {
fe07adec 562 ret = PTR_ERR(chan);
55f5f986
WS		 563 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
564 return chan;
565 }
566
567 memset(&cfg, 0, sizeof(cfg));
568 cfg.direction = dir;
569 if (dir == DMA_MEM_TO_DEV) {
570 cfg.dst_addr = port_addr;
571 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
572 } else {
573 cfg.src_addr = port_addr;
574 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
575 }
576
577 ret = dmaengine_slave_config(chan, &cfg);
578 if (ret) {
579 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
580 dma_release_channel(chan);
581 return ERR_PTR(ret);
582 }
583
584 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
585 return chan;
586}
587
2d09581b
WS		 588static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
589{
590 bool read = pd->msg->flags & I2C_M_RD;
591 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
592 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
593 struct dma_async_tx_descriptor *txdesc;
594 dma_addr_t dma_addr;
595 dma_cookie_t cookie;
596
55f5f986
WS		 597 if (PTR_ERR(chan) == -EPROBE_DEFER) {
598 if (read)
599 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
600 pd->res->start + ICDR);
601 else
602 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
603 pd->res->start + ICDR);
604 }
605
e844a799 606 if (IS_ERR(chan))
2d09581b
WS		 607 return;
608
8cfcae9f 609 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
2d09581b
WS		 610 if (dma_mapping_error(pd->dev, dma_addr)) {
611 dev_dbg(pd->dev, "dma map failed, using PIO\n");
612 return;
613 }
614
615 sg_dma_len(&pd->sg) = pd->msg->len;
616 sg_dma_address(&pd->sg) = dma_addr;
617
618 pd->dma_direction = dir;
619
620 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
621 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
623 if (!txdesc) {
624 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
625 sh_mobile_i2c_cleanup_dma(pd);
626 return;
627 }
628
629 txdesc->callback = sh_mobile_i2c_dma_callback;
630 txdesc->callback_param = pd;
631
632 cookie = dmaengine_submit(txdesc);
633 if (dma_submit_error(cookie)) {
634 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
635 sh_mobile_i2c_cleanup_dma(pd);
636 return;
637 }
638
639 dma_async_issue_pending(chan);
640}
641
e7890297
GL		 642static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
643 bool do_init)
da672773 644{
4eb00c9f
MD		 645 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
646 dev_err(pd->dev, "Unsupported zero length i2c read\n");
5a72b25e 647 return -EOPNOTSUPP;
4eb00c9f
MD		 648 }
649
e7890297
GL		 650 if (do_init) {
651 /* Initialize channel registers */
652 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 653
e7890297
GL		 654 /* Enable channel and configure rx ack */
655 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773 656
e7890297
GL		 657 /* Set the clock */
658 iic_wr(pd, ICCL, pd->iccl & 0xff);
659 iic_wr(pd, ICCH, pd->icch & 0xff);
660 }
da672773
MD		 661
662 pd->msg = usr_msg;
663 pd->pos = -1;
664 pd->sr = 0;
665
2d09581b
WS		 666 if (pd->msg->len > 8)
667 sh_mobile_i2c_xfer_dma(pd);
668
4eb00c9f 669 /* Enable all interrupts to begin with */
12a55f2d 670 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
da672773
MD		 671 return 0;
672}
673
e7890297
GL		 674static int poll_dte(struct sh_mobile_i2c_data *pd)
675{
676 int i;
677
678 for (i = 1000; i; i--) {
679 u_int8_t val = iic_rd(pd, ICSR);
680
681 if (val & ICSR_DTE)
682 break;
683
684 if (val & ICSR_TACK)
5a72b25e 685 return -ENXIO;
e7890297
GL		 686
687 udelay(10);
688 }
689
5a72b25e 690 return i ? 0 : -ETIMEDOUT;
e7890297
GL		 691}
692
4b382318
GL		 693static int poll_busy(struct sh_mobile_i2c_data *pd)
694{
695 int i;
696
697 for (i = 1000; i; i--) {
698 u_int8_t val = iic_rd(pd, ICSR);
699
700 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
701
702 /* the interrupt handler may wake us up before the
703 * transfer is finished, so poll the hardware
704 * until we're done.
705 */
706 if (!(val & ICSR_BUSY)) {
707 /* handle missing acknowledge and arbitration lost */
5a72b25e
WS		 708 val |= pd->sr;
709 if (val & ICSR_TACK)
710 return -ENXIO;
711 if (val & ICSR_AL)
712 return -EAGAIN;
4b382318
GL		 713 break;
714 }
715
716 udelay(10);
717 }
718
5a72b25e 719 return i ? 0 : -ETIMEDOUT;
4b382318
GL		 720}
721
da672773
MD		 722static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
723 struct i2c_msg *msgs,
724 int num)
725{
726 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
727 struct i2c_msg *msg;
728 int err = 0;
4b382318 729 int i, k;
da672773
MD		 730
731 activate_ch(pd);
732
733 /* Process all messages */
734 for (i = 0; i < num; i++) {
e7890297 735 bool do_start = pd->send_stop || !i;
da672773 736 msg = &msgs[i];
e7890297 737 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
32e22409 738 pd->stop_after_dma = false;
da672773 739
e7890297 740 err = start_ch(pd, msg, do_start);
da672773
MD		 741 if (err)
742 break;
743
e7890297
GL		 744 if (do_start)
745 i2c_op(pd, OP_START, 0);
da672773
MD		 746
747 /* The interrupt handler takes care of the rest... */
748 k = wait_event_timeout(pd->wait,
749 pd->sr & (ICSR_TACK | SW_DONE),
750 5 * HZ);
5687265b 751 if (!k) {
da672773 752 dev_err(pd->dev, "Transfer request timed out\n");
2d09581b
WS		 753 if (pd->dma_direction != DMA_NONE)
754 sh_mobile_i2c_cleanup_dma(pd);
755
5687265b
GL		 756 err = -ETIMEDOUT;
757 break;
758 }
da672773 759
e7890297
GL		 760 if (pd->send_stop)
761 err = poll_busy(pd);
762 else
763 err = poll_dte(pd);
4b382318 764 if (err < 0)
da672773 765 break;
da672773
MD		 766 }
767
768 deactivate_ch(pd);
769
770 if (!err)
771 err = num;
772 return err;
773}
774
775static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
776{
e7890297 777 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
da672773
MD		 778}
779
780static struct i2c_algorithm sh_mobile_i2c_algorithm = {
781 .functionality = sh_mobile_i2c_func,
782 .master_xfer = sh_mobile_i2c_xfer,
783};
784
67240dfc
WS		 785static const struct sh_mobile_dt_config default_dt_config = {
786 .clks_per_count = 1,
787};
788
78df445e 789static const struct sh_mobile_dt_config fast_clock_dt_config = {
67240dfc
WS		 790 .clks_per_count = 2,
791};
792
793static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
794 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
78df445e
GU		 795 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
796 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
797 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
798 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
799 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
800 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
801 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
67240dfc
WS		 802 {},
803};
804MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
805
2d09581b
WS		 806static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
807{
e844a799 808 if (!IS_ERR(pd->dma_tx)) {
2d09581b 809 dma_release_channel(pd->dma_tx);
e844a799 810 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
2d09581b
WS		 811 }
812
e844a799 813 if (!IS_ERR(pd->dma_rx)) {
2d09581b 814 dma_release_channel(pd->dma_rx);
e844a799 815 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
2d09581b
WS		 816 }
817}
818
530834b1 819static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
da672773
MD		 820{
821 struct resource *res;
7fe8a999
WS		 822 resource_size_t n;
823 int k = 0, ret;
da672773
MD		 824
825 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
7fe8a999
WS		 826 for (n = res->start; n <= res->end; n++) {
827 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
530834b1 828 0, dev_name(&dev->dev), pd);
7fe8a999
WS		 829 if (ret) {
830 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
831 return ret;
82b20d8b 832 }
da672773
MD		 833 }
834 k++;
835 }
836
7fe8a999 837 return k > 0 ? 0 : -ENOENT;
da672773
MD		 838}
839
840static int sh_mobile_i2c_probe(struct platform_device *dev)
841{
6d4028c6 842 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
da672773
MD		 843 struct sh_mobile_i2c_data *pd;
844 struct i2c_adapter *adap;
845 struct resource *res;
da672773 846 int ret;
88c289ec 847 u32 bus_speed;
da672773 848
4fd31c2e
WS		 849 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
850 if (!pd)
da672773 851 return -ENOMEM;
da672773 852
4fd31c2e 853 pd->clk = devm_clk_get(&dev->dev, NULL);
da672773 854 if (IS_ERR(pd->clk)) {
1082d5d2 855 dev_err(&dev->dev, "cannot get clock\n");
4fd31c2e 856 return PTR_ERR(pd->clk);
da672773
MD		 857 }
858
530834b1 859 ret = sh_mobile_i2c_hook_irqs(dev, pd);
7fe8a999 860 if (ret)
4fd31c2e 861 return ret;
da672773
MD		 862
863 pd->dev = &dev->dev;
864 platform_set_drvdata(dev, pd);
865
866 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
da672773 867
55f5f986 868 pd->res = res;
4fd31c2e 869 pd->reg = devm_ioremap_resource(&dev->dev, res);
7fe8a999
WS		 870 if (IS_ERR(pd->reg))
871 return PTR_ERR(pd->reg);
da672773 872
23a61291 873 /* Use platform data bus speed or STANDARD_MODE */
88c289ec
WS		 874 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
875 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
876
ebd5ac16 877 pd->clks_per_count = 1;
67240dfc
WS		 878
879 if (dev->dev.of_node) {
880 const struct of_device_id *match;
881
882 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
883 if (match) {
884 const struct sh_mobile_dt_config *config;
885
886 config = match->data;
887 pd->clks_per_count = config->clks_per_count;
888 }
889 } else {
890 if (pdata && pdata->bus_speed)
891 pd->bus_speed = pdata->bus_speed;
892 if (pdata && pdata->clks_per_count)
893 pd->clks_per_count = pdata->clks_per_count;
894 }
81f81153 895
962b6032
MD		 896 /* The IIC blocks on SH-Mobile ARM processors
897 * come with two new bits in ICIC.
898 */
4fd31c2e 899 if (resource_size(res) > 0x17)
962b6032
MD		 900 pd->flags |= IIC_FLAG_HAS_ICIC67;
901
6ed7053c
WS		 902 ret = sh_mobile_i2c_init(pd);
903 if (ret)
904 return ret;
7b0e6292 905
2d09581b
WS		 906 /* Init DMA */
907 sg_init_table(&pd->sg, 1);
908 pd->dma_direction = DMA_NONE;
55f5f986 909 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
2d09581b 910
f1a3b994
MD		 911 /* Enable Runtime PM for this device.
912 *
913 * Also tell the Runtime PM core to ignore children
914 * for this device since it is valid for us to suspend
915 * this I2C master driver even though the slave devices
916 * on the I2C bus may not be suspended.
917 *
918 * The state of the I2C hardware bus is unaffected by
919 * the Runtime PM state.
920 */
921 pm_suspend_ignore_children(&dev->dev, true);
922 pm_runtime_enable(&dev->dev);
923
da672773
MD		 924 /* setup the private data */
925 adap = &pd->adap;
926 i2c_set_adapdata(adap, pd);
927
928 adap->owner = THIS_MODULE;
929 adap->algo = &sh_mobile_i2c_algorithm;
930 adap->dev.parent = &dev->dev;
931 adap->retries = 5;
932 adap->nr = dev->id;
ad337074 933 adap->dev.of_node = dev->dev.of_node;
da672773
MD		 934
935 strlcpy(adap->name, dev->name, sizeof(adap->name));
936
a5616bd0
MD		 937 spin_lock_init(&pd->lock);
938 init_waitqueue_head(&pd->wait);
da672773
MD		 939
940 ret = i2c_add_numbered_adapter(adap);
941 if (ret < 0) {
2d09581b 942 sh_mobile_i2c_release_dma(pd);
da672773 943 dev_err(&dev->dev, "cannot add numbered adapter\n");
7fe8a999 944 return ret;
da672773
MD		 945 }
946
55f5f986 947 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
ad337074 948
da672773 949 return 0;
da672773
MD		 950}
951
952static int sh_mobile_i2c_remove(struct platform_device *dev)
953{
954 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
955
956 i2c_del_adapter(&pd->adap);
2d09581b 957 sh_mobile_i2c_release_dma(pd);
f1a3b994 958 pm_runtime_disable(&dev->dev);
da672773
MD		 959 return 0;
960}
961
f1a3b994
MD		 962static int sh_mobile_i2c_runtime_nop(struct device *dev)
963{
964 /* Runtime PM callback shared between ->runtime_suspend()
965 * and ->runtime_resume(). Simply returns success.
966 *
967 * This driver re-initializes all registers after
968 * pm_runtime_get_sync() anyway so there is no need
969 * to save and restore registers here.
970 */
971 return 0;
972}
973
47145210 974static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
f1a3b994
MD		 975 .runtime_suspend = sh_mobile_i2c_runtime_nop,
976 .runtime_resume = sh_mobile_i2c_runtime_nop,
977};
978
da672773
MD		 979static struct platform_driver sh_mobile_i2c_driver = {
980 .driver = {
981 .name = "i2c-sh_mobile",
f1a3b994 982 .pm = &sh_mobile_i2c_dev_pm_ops,
ad337074 983 .of_match_table = sh_mobile_i2c_dt_ids,
da672773
MD		 984 },
985 .probe = sh_mobile_i2c_probe,
986 .remove = sh_mobile_i2c_remove,
987};
988
989static int __init sh_mobile_i2c_adap_init(void)
990{
991 return platform_driver_register(&sh_mobile_i2c_driver);
992}
2d09581b 993subsys_initcall(sh_mobile_i2c_adap_init);
da672773
MD		 994
995static void __exit sh_mobile_i2c_adap_exit(void)
996{
997 platform_driver_unregister(&sh_mobile_i2c_driver);
998}
da672773
MD		 999module_exit(sh_mobile_i2c_adap_exit);
1000
1001MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
2d09581b 1002MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
da672773 1003MODULE_LICENSE("GPL v2");
7ef0c12a 1004MODULE_ALIAS("platform:i2c-sh_mobile");
Linux kernel - Deliverables
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