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i2c: imx: simplify i2c_imx_dma_write() a little
[deliverable/linux.git] / drivers / i2c / busses / i2c-sh_mobile.c
CommitLineData
da672773
MD		 1/*
2 * SuperH Mobile I2C Controller
3 *
2d09581b
WS		 4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
5 *
da672773
MD		 6 * Copyright (C) 2008 Magnus Damm
7 *
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
da672773
MD		 19 */
20
5bbe6879
WS		 21#include <linux/clk.h>
22#include <linux/delay.h>
2d09581b
WS		 23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
5bbe6879
WS		 25#include <linux/err.h>
26#include <linux/i2c.h>
27#include <linux/i2c/i2c-sh_mobile.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
da672773
MD		 31#include <linux/kernel.h>
32#include <linux/module.h>
5bbe6879 33#include <linux/of_device.h>
da672773 34#include <linux/platform_device.h>
f1a3b994 35#include <linux/pm_runtime.h>
5a0e3ad6 36#include <linux/slab.h>
da672773 37
4eb00c9f
MD		 38/* Transmit operation: */
39/* */
40/* 0 byte transmit */
e7890297 41/* BUS: S A8 ACK P(*) */
4eb00c9f
MD		 42/* IRQ: DTE WAIT */
43/* ICIC: */
44/* ICCR: 0x94 0x90 */
45/* ICDR: A8 */
46/* */
47/* 1 byte transmit */
e7890297 48/* BUS: S A8 ACK D8(1) ACK P(*) */
4eb00c9f
MD		 49/* IRQ: DTE WAIT WAIT */
50/* ICIC: -DTE */
51/* ICCR: 0x94 0x90 */
52/* ICDR: A8 D8(1) */
53/* */
54/* 2 byte transmit */
e7890297 55/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 56/* IRQ: DTE WAIT WAIT WAIT */
57/* ICIC: -DTE */
58/* ICCR: 0x94 0x90 */
59/* ICDR: A8 D8(1) D8(2) */
60/* */
61/* 3 bytes or more, +---------+ gets repeated */
62/* */
63/* */
64/* Receive operation: */
65/* */
66/* 0 byte receive - not supported since slave may hold SDA low */
67/* */
68/* 1 byte receive [TX] | [RX] */
e7890297 69/* BUS: S A8 ACK | D8(1) ACK P(*) */
4eb00c9f
MD		 70/* IRQ: DTE WAIT | WAIT DTE */
71/* ICIC: -DTE | +DTE */
72/* ICCR: 0x94 0x81 | 0xc0 */
73/* ICDR: A8 | D8(1) */
74/* */
75/* 2 byte receive [TX]| [RX] */
e7890297 76/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 77/* IRQ: DTE WAIT | WAIT WAIT DTE */
78/* ICIC: -DTE | +DTE */
79/* ICCR: 0x94 0x81 | 0xc0 */
80/* ICDR: A8 | D8(1) D8(2) */
81/* */
e7890297 82/* 3 byte receive [TX] | [RX] (*) */
4eb00c9f
MD		 83/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85/* ICIC: -DTE | +DTE */
86/* ICCR: 0x94 0x81 | 0xc0 */
87/* ICDR: A8 | D8(1) D8(2) D8(3) */
88/* */
89/* 4 bytes or more, this part is repeated +---------+ */
90/* */
91/* */
92/* Interrupt order and BUSY flag */
93/* ___ _ */
94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
96/* */
e7890297 97/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
4eb00c9f
MD		 98/* ___ */
99/* WAIT IRQ ________________________________/ \___________ */
100/* TACK IRQ ____________________________________/ \_______ */
101/* DTE IRQ __________________________________________/ \_ */
102/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103/* _______________________________________________ */
104/* BUSY __/ \_ */
105/* */
e7890297
GL		 106/* (*) The STOP condition is only sent by the master at the end of the last */
107/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108/* only cleared after the STOP condition, so, between messages we have to */
109/* poll for the DTE bit. */
110/* */
4eb00c9f 111
da672773
MD		 112enum sh_mobile_i2c_op {
113 OP_START = 0,
4eb00c9f
MD		 114 OP_TX_FIRST,
115 OP_TX,
da672773 116 OP_TX_STOP,
2d09581b 117 OP_TX_STOP_DATA,
da672773 118 OP_TX_TO_RX,
4eb00c9f 119 OP_RX,
da672773 120 OP_RX_STOP,
4eb00c9f 121 OP_RX_STOP_DATA,
da672773
MD		 122};
123
124struct sh_mobile_i2c_data {
125 struct device *dev;
126 void __iomem *reg;
127 struct i2c_adapter adap;
81f81153 128 unsigned long bus_speed;
ebd5ac16 129 unsigned int clks_per_count;
da672773 130 struct clk *clk;
962b6032 131 u_int8_t icic;
962b6032 132 u_int8_t flags;
23a61291
SK		 133 u_int16_t iccl;
134 u_int16_t icch;
da672773
MD		 135
136 spinlock_t lock;
137 wait_queue_head_t wait;
138 struct i2c_msg *msg;
139 int pos;
140 int sr;
e7890297 141 bool send_stop;
2d09581b
WS		 142
143 struct dma_chan *dma_tx;
144 struct dma_chan *dma_rx;
145 struct scatterlist sg;
146 enum dma_data_direction dma_direction;
da672773
MD		 147};
148
67240dfc
WS		 149struct sh_mobile_dt_config {
150 int clks_per_count;
151};
152
962b6032
MD		 153#define IIC_FLAG_HAS_ICIC67 (1 << 0)
154
23a61291
SK		 155#define STANDARD_MODE 100000
156#define FAST_MODE 400000
da672773
MD		 157
158/* Register offsets */
12a55f2d
MD		 159#define ICDR 0x00
160#define ICCR 0x04
161#define ICSR 0x08
162#define ICIC 0x0c
163#define ICCL 0x10
164#define ICCH 0x14
da672773
MD		 165
166/* Register bits */
167#define ICCR_ICE 0x80
168#define ICCR_RACK 0x40
169#define ICCR_TRS 0x10
170#define ICCR_BBSY 0x04
171#define ICCR_SCP 0x01
172
173#define ICSR_SCLM 0x80
174#define ICSR_SDAM 0x40
175#define SW_DONE 0x20
176#define ICSR_BUSY 0x10
177#define ICSR_AL 0x08
178#define ICSR_TACK 0x04
179#define ICSR_WAIT 0x02
180#define ICSR_DTE 0x01
181
962b6032
MD		 182#define ICIC_ICCLB8 0x80
183#define ICIC_ICCHB8 0x40
2d09581b
WS		 184#define ICIC_TDMAE 0x20
185#define ICIC_RDMAE 0x10
da672773
MD		 186#define ICIC_ALE 0x08
187#define ICIC_TACKE 0x04
188#define ICIC_WAITE 0x02
189#define ICIC_DTEE 0x01
190
12a55f2d
MD		 191static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
192{
962b6032
MD		 193 if (offs == ICIC)
194 data |= pd->icic;
195
12a55f2d
MD		 196 iowrite8(data, pd->reg + offs);
197}
198
199static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
200{
201 return ioread8(pd->reg + offs);
202}
203
204static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
205 unsigned char set, unsigned char clr)
206{
207 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
208}
209
ed4121e1 210static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
23a61291
SK		 211{
212 /*
213 * Conditional expression:
214 * ICCL >= COUNT_CLK * (tLOW + tf)
215 *
216 * SH-Mobile IIC hardware starts counting the LOW period of
217 * the SCL signal (tLOW) as soon as it pulls the SCL line.
218 * In order to meet the tLOW timing spec, we need to take into
219 * account the fall time of SCL signal (tf). Default tf value
220 * should be 0.3 us, for safety.
221 */
ed4121e1 222 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
23a61291
SK		 223}
224
ed4121e1 225static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
23a61291
SK		 226{
227 /*
228 * Conditional expression:
229 * ICCH >= COUNT_CLK * (tHIGH + tf)
230 *
231 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
232 * and can ignore it. SH-Mobile IIC controller starts counting
233 * the HIGH period of the SCL signal (tHIGH) after the SCL input
234 * voltage increases at VIH.
235 *
236 * Afterward it turned out calculating ICCH using only tHIGH spec
237 * will result in violation of the tHD;STA timing spec. We need
238 * to take into account the fall time of SDA signal (tf) at START
239 * condition, in order to meet both tHIGH and tHD;STA specs.
240 */
ed4121e1 241 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
23a61291
SK		 242}
243
6ed7053c 244static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
da672773 245{
23a61291
SK		 246 unsigned long i2c_clk_khz;
247 u32 tHIGH, tLOW, tf;
7663ebef 248 uint16_t max_val;
a5616bd0 249
a5616bd0 250 /* Get clock rate after clock is enabled */
f887605d 251 clk_prepare_enable(pd->clk);
23a61291 252 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
6ed7053c 253 clk_disable_unprepare(pd->clk);
ebd5ac16 254 i2c_clk_khz /= pd->clks_per_count;
23a61291
SK		 255
256 if (pd->bus_speed == STANDARD_MODE) {
257 tLOW = 47; /* tLOW = 4.7 us */
258 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
259 tf = 3; /* tf = 0.3 us */
23a61291
SK		 260 } else if (pd->bus_speed == FAST_MODE) {
261 tLOW = 13; /* tLOW = 1.3 us */
262 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
263 tf = 3; /* tf = 0.3 us */
23a61291
SK		 264 } else {
265 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
266 pd->bus_speed);
6ed7053c 267 return -EINVAL;
962b6032
MD		 268 }
269
ed4121e1 270 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
7663ebef
WS		 271 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
272
273 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
274 if (pd->iccl > max_val || pd->icch > max_val) {
275 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
276 pd->iccl, pd->icch);
277 return -EINVAL;
278 }
279
23a61291 280 /* one more bit of ICCL in ICIC */
7663ebef 281 if (pd->iccl & 0x100)
23a61291 282 pd->icic |= ICIC_ICCLB8;
a5616bd0 283 else
23a61291 284 pd->icic &= ~ICIC_ICCLB8;
a5616bd0 285
962b6032 286 /* one more bit of ICCH in ICIC */
7663ebef 287 if (pd->icch & 0x100)
23a61291
SK		 288 pd->icic |= ICIC_ICCHB8;
289 else
290 pd->icic &= ~ICIC_ICCHB8;
962b6032 291
7ca01864 292 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
6ed7053c 293 return 0;
7b0e6292
SK		 294}
295
296static void activate_ch(struct sh_mobile_i2c_data *pd)
297{
298 /* Wake up device and enable clock */
299 pm_runtime_get_sync(pd->dev);
f887605d 300 clk_prepare_enable(pd->clk);
7b0e6292 301
da672773 302 /* Enable channel and configure rx ack */
12a55f2d 303 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773
MD		 304
305 /* Mask all interrupts */
12a55f2d 306 iic_wr(pd, ICIC, 0);
da672773
MD		 307
308 /* Set the clock */
23a61291
SK		 309 iic_wr(pd, ICCL, pd->iccl & 0xff);
310 iic_wr(pd, ICCH, pd->icch & 0xff);
da672773
MD		 311}
312
313static void deactivate_ch(struct sh_mobile_i2c_data *pd)
314{
315 /* Clear/disable interrupts */
12a55f2d
MD		 316 iic_wr(pd, ICSR, 0);
317 iic_wr(pd, ICIC, 0);
da672773
MD		 318
319 /* Disable channel */
12a55f2d 320 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 321
f1a3b994 322 /* Disable clock and mark device as idle */
f887605d 323 clk_disable_unprepare(pd->clk);
f1a3b994 324 pm_runtime_put_sync(pd->dev);
da672773
MD		 325}
326
327static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
328 enum sh_mobile_i2c_op op, unsigned char data)
329{
330 unsigned char ret = 0;
331 unsigned long flags;
332
333 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
334
335 spin_lock_irqsave(&pd->lock, flags);
336
337 switch (op) {
4eb00c9f 338 case OP_START: /* issue start and trigger DTE interrupt */
a78f6a41 339 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
da672773 340 break;
4eb00c9f 341 case OP_TX_FIRST: /* disable DTE interrupt and write data */
12a55f2d
MD		 342 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
343 iic_wr(pd, ICDR, data);
da672773 344 break;
4eb00c9f 345 case OP_TX: /* write data */
12a55f2d 346 iic_wr(pd, ICDR, data);
da672773 347 break;
2d09581b 348 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
12a55f2d 349 iic_wr(pd, ICDR, data);
2d09581b
WS		 350 /* fallthrough */
351 case OP_TX_STOP: /* issue a stop */
a78f6a41
WS		 352 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
353 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
4eb00c9f
MD		 354 break;
355 case OP_TX_TO_RX: /* select read mode */
a78f6a41 356 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
da672773 357 break;
4eb00c9f 358 case OP_RX: /* just read data */
12a55f2d 359 ret = iic_rd(pd, ICDR);
da672773 360 break;
4eb00c9f 361 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
12a55f2d
MD		 362 iic_wr(pd, ICIC,
363 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
a78f6a41 364 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
4eb00c9f
MD		 365 break;
366 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
12a55f2d
MD		 367 iic_wr(pd, ICIC,
368 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
369 ret = iic_rd(pd, ICDR);
a78f6a41 370 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
da672773
MD		 371 break;
372 }
373
374 spin_unlock_irqrestore(&pd->lock, flags);
375
376 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
377 return ret;
378}
379
05cf9368 380static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 381{
05cf9368 382 return pd->pos == -1;
4eb00c9f
MD		 383}
384
05cf9368 385static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 386{
05cf9368 387 return pd->pos == pd->msg->len - 1;
4eb00c9f
MD		 388}
389
390static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
391 unsigned char *buf)
392{
393 switch (pd->pos) {
394 case -1:
395 *buf = (pd->msg->addr & 0x7f) << 1;
396 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
397 break;
398 default:
399 *buf = pd->msg->buf[pd->pos];
400 }
401}
402
403static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
404{
405 unsigned char data;
406
2d09581b
WS		 407 if (pd->pos == pd->msg->len) {
408 /* Send stop if we haven't yet (DMA case) */
409 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
410 i2c_op(pd, OP_TX_STOP, 0);
4eb00c9f 411 return 1;
2d09581b 412 }
4eb00c9f
MD		 413
414 sh_mobile_i2c_get_data(pd, &data);
415
416 if (sh_mobile_i2c_is_last_byte(pd))
2d09581b 417 i2c_op(pd, OP_TX_STOP_DATA, data);
4eb00c9f
MD		 418 else if (sh_mobile_i2c_is_first_byte(pd))
419 i2c_op(pd, OP_TX_FIRST, data);
420 else
421 i2c_op(pd, OP_TX, data);
422
423 pd->pos++;
424 return 0;
425}
426
427static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
428{
429 unsigned char data;
430 int real_pos;
431
432 do {
433 if (pd->pos <= -1) {
434 sh_mobile_i2c_get_data(pd, &data);
435
436 if (sh_mobile_i2c_is_first_byte(pd))
437 i2c_op(pd, OP_TX_FIRST, data);
438 else
439 i2c_op(pd, OP_TX, data);
440 break;
441 }
442
443 if (pd->pos == 0) {
444 i2c_op(pd, OP_TX_TO_RX, 0);
445 break;
446 }
447
448 real_pos = pd->pos - 2;
449
450 if (pd->pos == pd->msg->len) {
451 if (real_pos < 0) {
452 i2c_op(pd, OP_RX_STOP, 0);
453 break;
454 }
455 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
456 } else
457 data = i2c_op(pd, OP_RX, 0);
458
bff4056c
MD		 459 if (real_pos >= 0)
460 pd->msg->buf[real_pos] = data;
4eb00c9f
MD		 461 } while (0);
462
463 pd->pos++;
464 return pd->pos == (pd->msg->len + 2);
465}
466
da672773
MD		 467static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
468{
469 struct platform_device *dev = dev_id;
470 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
4eb00c9f 471 unsigned char sr;
2d09581b 472 int wakeup = 0;
da672773 473
12a55f2d 474 sr = iic_rd(pd, ICSR);
4eb00c9f 475 pd->sr |= sr; /* remember state */
da672773
MD		 476
477 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
4eb00c9f
MD		 478 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
479 pd->pos, pd->msg->len);
da672773 480
2d09581b
WS		 481 /* Kick off TxDMA after preface was done */
482 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
483 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
484 else if (sr & (ICSR_AL | ICSR_TACK))
4eb00c9f 485 /* don't interrupt transaction - continue to issue stop */
12a55f2d 486 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
2d09581b 487 else if (pd->msg->flags & I2C_M_RD)
4eb00c9f
MD		 488 wakeup = sh_mobile_i2c_isr_rx(pd);
489 else
490 wakeup = sh_mobile_i2c_isr_tx(pd);
da672773 491
2d09581b
WS		 492 /* Kick off RxDMA after preface was done */
493 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
494 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
495
4eb00c9f 496 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
12a55f2d 497 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
da672773 498
da672773
MD		 499 if (wakeup) {
500 pd->sr |= SW_DONE;
501 wake_up(&pd->wait);
502 }
503
29fb08c3
SK		 504 /* defeat write posting to avoid spurious WAIT interrupts */
505 iic_rd(pd, ICSR);
506
da672773
MD		 507 return IRQ_HANDLED;
508}
509
2d09581b
WS		 510static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
511{
512 if (pd->dma_direction == DMA_NONE)
513 return;
514 else if (pd->dma_direction == DMA_FROM_DEVICE)
515 dmaengine_terminate_all(pd->dma_rx);
516 else if (pd->dma_direction == DMA_TO_DEVICE)
517 dmaengine_terminate_all(pd->dma_tx);
518
519 dma_unmap_single(pd->dev, sg_dma_address(&pd->sg),
520 pd->msg->len, pd->dma_direction);
521
522 pd->dma_direction = DMA_NONE;
523}
524
525static void sh_mobile_i2c_dma_callback(void *data)
526{
527 struct sh_mobile_i2c_data *pd = data;
528
529 dma_unmap_single(pd->dev, sg_dma_address(&pd->sg),
530 pd->msg->len, pd->dma_direction);
531
532 pd->dma_direction = DMA_NONE;
533 pd->pos = pd->msg->len;
534
535 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
536}
537
538static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
539{
540 bool read = pd->msg->flags & I2C_M_RD;
541 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
542 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
543 struct dma_async_tx_descriptor *txdesc;
544 dma_addr_t dma_addr;
545 dma_cookie_t cookie;
546
547 if (!chan)
548 return;
549
550 dma_addr = dma_map_single(pd->dev, pd->msg->buf, pd->msg->len, dir);
551 if (dma_mapping_error(pd->dev, dma_addr)) {
552 dev_dbg(pd->dev, "dma map failed, using PIO\n");
553 return;
554 }
555
556 sg_dma_len(&pd->sg) = pd->msg->len;
557 sg_dma_address(&pd->sg) = dma_addr;
558
559 pd->dma_direction = dir;
560
561 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
562 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
563 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
564 if (!txdesc) {
565 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
566 sh_mobile_i2c_cleanup_dma(pd);
567 return;
568 }
569
570 txdesc->callback = sh_mobile_i2c_dma_callback;
571 txdesc->callback_param = pd;
572
573 cookie = dmaengine_submit(txdesc);
574 if (dma_submit_error(cookie)) {
575 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
576 sh_mobile_i2c_cleanup_dma(pd);
577 return;
578 }
579
580 dma_async_issue_pending(chan);
581}
582
e7890297
GL		 583static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
584 bool do_init)
da672773 585{
4eb00c9f
MD		 586 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
587 dev_err(pd->dev, "Unsupported zero length i2c read\n");
5a72b25e 588 return -EOPNOTSUPP;
4eb00c9f
MD		 589 }
590
e7890297
GL		 591 if (do_init) {
592 /* Initialize channel registers */
593 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 594
e7890297
GL		 595 /* Enable channel and configure rx ack */
596 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773 597
e7890297
GL		 598 /* Set the clock */
599 iic_wr(pd, ICCL, pd->iccl & 0xff);
600 iic_wr(pd, ICCH, pd->icch & 0xff);
601 }
da672773
MD		 602
603 pd->msg = usr_msg;
604 pd->pos = -1;
605 pd->sr = 0;
606
2d09581b
WS		 607 if (pd->msg->len > 8)
608 sh_mobile_i2c_xfer_dma(pd);
609
4eb00c9f 610 /* Enable all interrupts to begin with */
12a55f2d 611 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
da672773
MD		 612 return 0;
613}
614
e7890297
GL		 615static int poll_dte(struct sh_mobile_i2c_data *pd)
616{
617 int i;
618
619 for (i = 1000; i; i--) {
620 u_int8_t val = iic_rd(pd, ICSR);
621
622 if (val & ICSR_DTE)
623 break;
624
625 if (val & ICSR_TACK)
5a72b25e 626 return -ENXIO;
e7890297
GL		 627
628 udelay(10);
629 }
630
5a72b25e 631 return i ? 0 : -ETIMEDOUT;
e7890297
GL		 632}
633
4b382318
GL		 634static int poll_busy(struct sh_mobile_i2c_data *pd)
635{
636 int i;
637
638 for (i = 1000; i; i--) {
639 u_int8_t val = iic_rd(pd, ICSR);
640
641 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
642
643 /* the interrupt handler may wake us up before the
644 * transfer is finished, so poll the hardware
645 * until we're done.
646 */
647 if (!(val & ICSR_BUSY)) {
648 /* handle missing acknowledge and arbitration lost */
5a72b25e
WS		 649 val |= pd->sr;
650 if (val & ICSR_TACK)
651 return -ENXIO;
652 if (val & ICSR_AL)
653 return -EAGAIN;
4b382318
GL		 654 break;
655 }
656
657 udelay(10);
658 }
659
5a72b25e 660 return i ? 0 : -ETIMEDOUT;
4b382318
GL		 661}
662
da672773
MD		 663static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
664 struct i2c_msg *msgs,
665 int num)
666{
667 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
668 struct i2c_msg *msg;
669 int err = 0;
4b382318 670 int i, k;
da672773
MD		 671
672 activate_ch(pd);
673
674 /* Process all messages */
675 for (i = 0; i < num; i++) {
e7890297 676 bool do_start = pd->send_stop || !i;
da672773 677 msg = &msgs[i];
e7890297 678 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
da672773 679
e7890297 680 err = start_ch(pd, msg, do_start);
da672773
MD		 681 if (err)
682 break;
683
e7890297
GL		 684 if (do_start)
685 i2c_op(pd, OP_START, 0);
da672773
MD		 686
687 /* The interrupt handler takes care of the rest... */
688 k = wait_event_timeout(pd->wait,
689 pd->sr & (ICSR_TACK | SW_DONE),
690 5 * HZ);
5687265b 691 if (!k) {
da672773 692 dev_err(pd->dev, "Transfer request timed out\n");
2d09581b
WS		 693 if (pd->dma_direction != DMA_NONE)
694 sh_mobile_i2c_cleanup_dma(pd);
695
5687265b
GL		 696 err = -ETIMEDOUT;
697 break;
698 }
da672773 699
e7890297
GL		 700 if (pd->send_stop)
701 err = poll_busy(pd);
702 else
703 err = poll_dte(pd);
4b382318 704 if (err < 0)
da672773 705 break;
da672773
MD		 706 }
707
708 deactivate_ch(pd);
709
710 if (!err)
711 err = num;
712 return err;
713}
714
715static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
716{
e7890297 717 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
da672773
MD		 718}
719
720static struct i2c_algorithm sh_mobile_i2c_algorithm = {
721 .functionality = sh_mobile_i2c_func,
722 .master_xfer = sh_mobile_i2c_xfer,
723};
724
67240dfc
WS		 725static const struct sh_mobile_dt_config default_dt_config = {
726 .clks_per_count = 1,
727};
728
78df445e 729static const struct sh_mobile_dt_config fast_clock_dt_config = {
67240dfc
WS		 730 .clks_per_count = 2,
731};
732
733static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
734 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
78df445e
GU		 735 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
736 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
737 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
738 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
739 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
740 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
741 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
67240dfc
WS		 742 {},
743};
744MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
745
2d09581b
WS		 746static int sh_mobile_i2c_request_dma_chan(struct device *dev, enum dma_transfer_direction dir,
747 dma_addr_t port_addr, struct dma_chan **chan_ptr)
748{
749 dma_cap_mask_t mask;
750 struct dma_chan *chan;
751 struct dma_slave_config cfg;
752 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
753 int ret;
754
755 dma_cap_zero(mask);
756 dma_cap_set(DMA_SLAVE, mask);
757 *chan_ptr = NULL;
758
759 chan = dma_request_slave_channel_reason(dev, chan_name);
760 if (IS_ERR(chan)) {
761 ret = PTR_ERR(chan);
762 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
763 return ret;
764 }
765
766 memset(&cfg, 0, sizeof(cfg));
767 cfg.direction = dir;
768 if (dir == DMA_MEM_TO_DEV) {
769 cfg.dst_addr = port_addr;
770 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
771 } else {
772 cfg.src_addr = port_addr;
773 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
774 }
775
776 ret = dmaengine_slave_config(chan, &cfg);
777 if (ret) {
778 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
779 dma_release_channel(chan);
780 return ret;
781 }
782
783 *chan_ptr = chan;
784
785 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
786 return 0;
787}
788
789static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
790{
791 if (pd->dma_tx) {
792 dma_release_channel(pd->dma_tx);
793 pd->dma_tx = NULL;
794 }
795
796 if (pd->dma_rx) {
797 dma_release_channel(pd->dma_rx);
798 pd->dma_rx = NULL;
799 }
800}
801
7fe8a999 802static int sh_mobile_i2c_hook_irqs(struct platform_device *dev)
da672773
MD		 803{
804 struct resource *res;
7fe8a999
WS		 805 resource_size_t n;
806 int k = 0, ret;
da672773
MD		 807
808 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
7fe8a999
WS		 809 for (n = res->start; n <= res->end; n++) {
810 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
811 0, dev_name(&dev->dev), dev);
812 if (ret) {
813 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
814 return ret;
82b20d8b 815 }
da672773
MD		 816 }
817 k++;
818 }
819
7fe8a999 820 return k > 0 ? 0 : -ENOENT;
da672773
MD		 821}
822
823static int sh_mobile_i2c_probe(struct platform_device *dev)
824{
6d4028c6 825 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
da672773
MD		 826 struct sh_mobile_i2c_data *pd;
827 struct i2c_adapter *adap;
828 struct resource *res;
da672773 829 int ret;
88c289ec 830 u32 bus_speed;
da672773 831
4fd31c2e
WS		 832 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
833 if (!pd)
da672773 834 return -ENOMEM;
da672773 835
4fd31c2e 836 pd->clk = devm_clk_get(&dev->dev, NULL);
da672773 837 if (IS_ERR(pd->clk)) {
1082d5d2 838 dev_err(&dev->dev, "cannot get clock\n");
4fd31c2e 839 return PTR_ERR(pd->clk);
da672773
MD		 840 }
841
7fe8a999
WS		 842 ret = sh_mobile_i2c_hook_irqs(dev);
843 if (ret)
4fd31c2e 844 return ret;
da672773
MD		 845
846 pd->dev = &dev->dev;
847 platform_set_drvdata(dev, pd);
848
849 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
da672773 850
4fd31c2e 851 pd->reg = devm_ioremap_resource(&dev->dev, res);
7fe8a999
WS		 852 if (IS_ERR(pd->reg))
853 return PTR_ERR(pd->reg);
da672773 854
23a61291 855 /* Use platform data bus speed or STANDARD_MODE */
88c289ec
WS		 856 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
857 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
858
ebd5ac16 859 pd->clks_per_count = 1;
67240dfc
WS		 860
861 if (dev->dev.of_node) {
862 const struct of_device_id *match;
863
864 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
865 if (match) {
866 const struct sh_mobile_dt_config *config;
867
868 config = match->data;
869 pd->clks_per_count = config->clks_per_count;
870 }
871 } else {
872 if (pdata && pdata->bus_speed)
873 pd->bus_speed = pdata->bus_speed;
874 if (pdata && pdata->clks_per_count)
875 pd->clks_per_count = pdata->clks_per_count;
876 }
81f81153 877
962b6032
MD		 878 /* The IIC blocks on SH-Mobile ARM processors
879 * come with two new bits in ICIC.
880 */
4fd31c2e 881 if (resource_size(res) > 0x17)
962b6032
MD		 882 pd->flags |= IIC_FLAG_HAS_ICIC67;
883
6ed7053c
WS		 884 ret = sh_mobile_i2c_init(pd);
885 if (ret)
886 return ret;
7b0e6292 887
2d09581b
WS		 888 /* Init DMA */
889 sg_init_table(&pd->sg, 1);
890 pd->dma_direction = DMA_NONE;
891 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
892 res->start + ICDR, &pd->dma_rx);
893 if (ret == -EPROBE_DEFER)
894 return ret;
895
896 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
897 res->start + ICDR, &pd->dma_tx);
898 if (ret == -EPROBE_DEFER) {
899 sh_mobile_i2c_release_dma(pd);
900 return ret;
901 }
902
f1a3b994
MD		 903 /* Enable Runtime PM for this device.
904 *
905 * Also tell the Runtime PM core to ignore children
906 * for this device since it is valid for us to suspend
907 * this I2C master driver even though the slave devices
908 * on the I2C bus may not be suspended.
909 *
910 * The state of the I2C hardware bus is unaffected by
911 * the Runtime PM state.
912 */
913 pm_suspend_ignore_children(&dev->dev, true);
914 pm_runtime_enable(&dev->dev);
915
da672773
MD		 916 /* setup the private data */
917 adap = &pd->adap;
918 i2c_set_adapdata(adap, pd);
919
920 adap->owner = THIS_MODULE;
921 adap->algo = &sh_mobile_i2c_algorithm;
922 adap->dev.parent = &dev->dev;
923 adap->retries = 5;
924 adap->nr = dev->id;
ad337074 925 adap->dev.of_node = dev->dev.of_node;
da672773
MD		 926
927 strlcpy(adap->name, dev->name, sizeof(adap->name));
928
a5616bd0
MD		 929 spin_lock_init(&pd->lock);
930 init_waitqueue_head(&pd->wait);
da672773
MD		 931
932 ret = i2c_add_numbered_adapter(adap);
933 if (ret < 0) {
2d09581b 934 sh_mobile_i2c_release_dma(pd);
da672773 935 dev_err(&dev->dev, "cannot add numbered adapter\n");
7fe8a999 936 return ret;
da672773
MD		 937 }
938
7ca01864
WS		 939 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n",
940 adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n');
ad337074 941
da672773 942 return 0;
da672773
MD		 943}
944
945static int sh_mobile_i2c_remove(struct platform_device *dev)
946{
947 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
948
949 i2c_del_adapter(&pd->adap);
2d09581b 950 sh_mobile_i2c_release_dma(pd);
f1a3b994 951 pm_runtime_disable(&dev->dev);
da672773
MD		 952 return 0;
953}
954
f1a3b994
MD		 955static int sh_mobile_i2c_runtime_nop(struct device *dev)
956{
957 /* Runtime PM callback shared between ->runtime_suspend()
958 * and ->runtime_resume(). Simply returns success.
959 *
960 * This driver re-initializes all registers after
961 * pm_runtime_get_sync() anyway so there is no need
962 * to save and restore registers here.
963 */
964 return 0;
965}
966
47145210 967static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
f1a3b994
MD		 968 .runtime_suspend = sh_mobile_i2c_runtime_nop,
969 .runtime_resume = sh_mobile_i2c_runtime_nop,
970};
971
da672773
MD		 972static struct platform_driver sh_mobile_i2c_driver = {
973 .driver = {
974 .name = "i2c-sh_mobile",
975 .owner = THIS_MODULE,
f1a3b994 976 .pm = &sh_mobile_i2c_dev_pm_ops,
ad337074 977 .of_match_table = sh_mobile_i2c_dt_ids,
da672773
MD		 978 },
979 .probe = sh_mobile_i2c_probe,
980 .remove = sh_mobile_i2c_remove,
981};
982
983static int __init sh_mobile_i2c_adap_init(void)
984{
985 return platform_driver_register(&sh_mobile_i2c_driver);
986}
2d09581b 987subsys_initcall(sh_mobile_i2c_adap_init);
da672773
MD		 988
989static void __exit sh_mobile_i2c_adap_exit(void)
990{
991 platform_driver_unregister(&sh_mobile_i2c_driver);
992}
da672773
MD		 993module_exit(sh_mobile_i2c_adap_exit);
994
995MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
2d09581b 996MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
da672773 997MODULE_LICENSE("GPL v2");
7ef0c12a 998MODULE_ALIAS("platform:i2c-sh_mobile");
Linux kernel - Deliverables
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