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Merge tag 'pm+acpi-3.14-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafae...
[deliverable/linux.git] / drivers / i2c / busses / i2c-tegra.c
CommitLineData
db811ca0
CC		 1/*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
6ad068ed 28#include <linux/of_device.h>
93cf5d75 29#include <linux/module.h>
dda9d6a8 30#include <linux/reset.h>
db811ca0
CC		 31
32#include <asm/unaligned.h>
33
db811ca0
CC		 34#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
35#define BYTES_PER_FIFO_WORD 4
36
37#define I2C_CNFG 0x000
40abcf77 38#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
db811ca0
CC		 39#define I2C_CNFG_PACKET_MODE_EN (1<<10)
40#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
cb63c62d 41#define I2C_STATUS 0x01C
db811ca0 42#define I2C_SL_CNFG 0x020
5afa9d35 43#define I2C_SL_CNFG_NACK (1<<1)
db811ca0
CC		 44#define I2C_SL_CNFG_NEWSL (1<<2)
45#define I2C_SL_ADDR1 0x02c
5afa9d35 46#define I2C_SL_ADDR2 0x030
db811ca0
CC		 47#define I2C_TX_FIFO 0x050
48#define I2C_RX_FIFO 0x054
49#define I2C_PACKET_TRANSFER_STATUS 0x058
50#define I2C_FIFO_CONTROL 0x05c
51#define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
52#define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
53#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
54#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
55#define I2C_FIFO_STATUS 0x060
56#define I2C_FIFO_STATUS_TX_MASK 0xF0
57#define I2C_FIFO_STATUS_TX_SHIFT 4
58#define I2C_FIFO_STATUS_RX_MASK 0x0F
59#define I2C_FIFO_STATUS_RX_SHIFT 0
60#define I2C_INT_MASK 0x064
61#define I2C_INT_STATUS 0x068
62#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
63#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
64#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
65#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
66#define I2C_INT_NO_ACK (1<<3)
67#define I2C_INT_ARBITRATION_LOST (1<<2)
68#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
69#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
70#define I2C_CLK_DIVISOR 0x06c
2a2897ba
LD		 71#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
72#define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
db811ca0
CC		 73
74#define DVC_CTRL_REG1 0x000
75#define DVC_CTRL_REG1_INTR_EN (1<<10)
76#define DVC_CTRL_REG2 0x004
77#define DVC_CTRL_REG3 0x008
78#define DVC_CTRL_REG3_SW_PROG (1<<26)
79#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80#define DVC_STATUS 0x00c
81#define DVC_STATUS_I2C_DONE_INTR (1<<30)
82
83#define I2C_ERR_NONE 0x00
84#define I2C_ERR_NO_ACK 0x01
85#define I2C_ERR_ARBITRATION_LOST 0x02
cb63c62d 86#define I2C_ERR_UNKNOWN_INTERRUPT 0x04
db811ca0
CC		 87
88#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89#define PACKET_HEADER0_PACKET_ID_SHIFT 16
90#define PACKET_HEADER0_CONT_ID_SHIFT 12
91#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
92
93#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94#define I2C_HEADER_CONT_ON_NAK (1<<21)
95#define I2C_HEADER_SEND_START_BYTE (1<<20)
96#define I2C_HEADER_READ (1<<19)
97#define I2C_HEADER_10BIT_ADDR (1<<18)
98#define I2C_HEADER_IE_ENABLE (1<<17)
99#define I2C_HEADER_REPEAT_START (1<<16)
c8f5af2f 100#define I2C_HEADER_CONTINUE_XFER (1<<15)
db811ca0
CC		 101#define I2C_HEADER_MASTER_ADDR_SHIFT 12
102#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
c8f5af2f
LD		 103/*
104 * msg_end_type: The bus control which need to be send at end of transfer.
105 * @MSG_END_STOP: Send stop pulse at end of transfer.
106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
107 * @MSG_END_CONTINUE: The following on message is coming and so do not send
108 * stop or repeat start.
109 */
110enum msg_end_type {
111 MSG_END_STOP,
112 MSG_END_REPEAT_START,
113 MSG_END_CONTINUE,
114};
db811ca0 115
6ad068ed
LD		 116/**
117 * struct tegra_i2c_hw_feature : Different HW support on Tegra
118 * @has_continue_xfer_support: Continue transfer supports.
2a2897ba
LD		 119 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
120 * complete interrupt per packet basis.
121 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
122 * and earlier Socs has two clock sources i.e. div-clk and
123 * fast-clk.
124 * @clk_divisor_hs_mode: Clock divisor in HS mode.
125 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
126 * applicable if there is no fast clock source i.e. single clock
127 * source.
6ad068ed
LD		 128 */
129
130struct tegra_i2c_hw_feature {
131 bool has_continue_xfer_support;
2a2897ba
LD		 132 bool has_per_pkt_xfer_complete_irq;
133 bool has_single_clk_source;
134 int clk_divisor_hs_mode;
135 int clk_divisor_std_fast_mode;
6ad068ed
LD		 136};
137
db811ca0
CC		 138/**
139 * struct tegra_i2c_dev - per device i2c context
140 * @dev: device reference for power management
6ad068ed 141 * @hw: Tegra i2c hw feature.
db811ca0 142 * @adapter: core i2c layer adapter information
14e92bd4
LD		 143 * @div_clk: clock reference for div clock of i2c controller.
144 * @fast_clk: clock reference for fast clock of i2c controller.
db811ca0
CC		 145 * @base: ioremapped registers cookie
146 * @cont_id: i2c controller id, used for for packet header
147 * @irq: irq number of transfer complete interrupt
148 * @is_dvc: identifies the DVC i2c controller, has a different register layout
149 * @msg_complete: transfer completion notifier
150 * @msg_err: error code for completed message
151 * @msg_buf: pointer to current message data
152 * @msg_buf_remaining: size of unsent data in the message buffer
153 * @msg_read: identifies read transfers
154 * @bus_clk_rate: current i2c bus clock rate
155 * @is_suspended: prevents i2c controller accesses after suspend is called
156 */
157struct tegra_i2c_dev {
158 struct device *dev;
6ad068ed 159 const struct tegra_i2c_hw_feature *hw;
db811ca0 160 struct i2c_adapter adapter;
14e92bd4
LD		 161 struct clk *div_clk;
162 struct clk *fast_clk;
dda9d6a8 163 struct reset_control *rst;
db811ca0
CC		 164 void __iomem *base;
165 int cont_id;
166 int irq;
cb63c62d 167 bool irq_disabled;
db811ca0
CC		 168 int is_dvc;
169 struct completion msg_complete;
170 int msg_err;
171 u8 *msg_buf;
172 size_t msg_buf_remaining;
173 int msg_read;
49a64ac5 174 u32 bus_clk_rate;
db811ca0
CC		 175 bool is_suspended;
176};
177
178static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
179{
180 writel(val, i2c_dev->base + reg);
181}
182
183static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
184{
185 return readl(i2c_dev->base + reg);
186}
187
188/*
189 * i2c_writel and i2c_readl will offset the register if necessary to talk
190 * to the I2C block inside the DVC block
191 */
192static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
193 unsigned long reg)
194{
195 if (i2c_dev->is_dvc)
196 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
197 return reg;
198}
199
200static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
201 unsigned long reg)
202{
203 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
ec7aaca2
LD		 204
205 /* Read back register to make sure that register writes completed */
206 if (reg != I2C_TX_FIFO)
207 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
db811ca0
CC		 208}
209
210static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
211{
212 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
213}
214
215static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
216 unsigned long reg, int len)
217{
218 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
219}
220
221static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
222 unsigned long reg, int len)
223{
224 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
225}
226
227static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
228{
229 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
230 int_mask &= ~mask;
231 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
232}
233
234static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
235{
236 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
237 int_mask |= mask;
238 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
239}
240
241static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
242{
243 unsigned long timeout = jiffies + HZ;
244 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
245 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
246 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
247
248 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
249 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
250 if (time_after(jiffies, timeout)) {
251 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
252 return -ETIMEDOUT;
253 }
254 msleep(1);
255 }
256 return 0;
257}
258
259static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
260{
261 u32 val;
262 int rx_fifo_avail;
263 u8 *buf = i2c_dev->msg_buf;
264 size_t buf_remaining = i2c_dev->msg_buf_remaining;
265 int words_to_transfer;
266
267 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
268 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
269 I2C_FIFO_STATUS_RX_SHIFT;
270
271 /* Rounds down to not include partial word at the end of buf */
272 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
273 if (words_to_transfer > rx_fifo_avail)
274 words_to_transfer = rx_fifo_avail;
275
276 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
277
278 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
279 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
280 rx_fifo_avail -= words_to_transfer;
281
282 /*
283 * If there is a partial word at the end of buf, handle it manually to
284 * prevent overwriting past the end of buf
285 */
286 if (rx_fifo_avail > 0 && buf_remaining > 0) {
287 BUG_ON(buf_remaining > 3);
288 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
289 memcpy(buf, &val, buf_remaining);
290 buf_remaining = 0;
291 rx_fifo_avail--;
292 }
293
294 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
295 i2c_dev->msg_buf_remaining = buf_remaining;
296 i2c_dev->msg_buf = buf;
297 return 0;
298}
299
300static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
301{
302 u32 val;
303 int tx_fifo_avail;
304 u8 *buf = i2c_dev->msg_buf;
305 size_t buf_remaining = i2c_dev->msg_buf_remaining;
306 int words_to_transfer;
307
308 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
309 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
310 I2C_FIFO_STATUS_TX_SHIFT;
311
312 /* Rounds down to not include partial word at the end of buf */
313 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
db811ca0 314
96219c3a
DA		 315 /* It's very common to have < 4 bytes, so optimize that case. */
316 if (words_to_transfer) {
317 if (words_to_transfer > tx_fifo_avail)
318 words_to_transfer = tx_fifo_avail;
319
320 /*
321 * Update state before writing to FIFO. If this casues us
322 * to finish writing all bytes (AKA buf_remaining goes to 0) we
323 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
324 * not maskable). We need to make sure that the isr sees
325 * buf_remaining as 0 and doesn't call us back re-entrantly.
326 */
327 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
328 tx_fifo_avail -= words_to_transfer;
329 i2c_dev->msg_buf_remaining = buf_remaining;
330 i2c_dev->msg_buf = buf +
331 words_to_transfer * BYTES_PER_FIFO_WORD;
332 barrier();
333
334 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
335
336 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
337 }
db811ca0
CC		 338
339 /*
340 * If there is a partial word at the end of buf, handle it manually to
341 * prevent reading past the end of buf, which could cross a page
342 * boundary and fault.
343 */
344 if (tx_fifo_avail > 0 && buf_remaining > 0) {
345 BUG_ON(buf_remaining > 3);
346 memcpy(&val, buf, buf_remaining);
96219c3a
DA		 347
348 /* Again update before writing to FIFO to make sure isr sees. */
349 i2c_dev->msg_buf_remaining = 0;
350 i2c_dev->msg_buf = NULL;
351 barrier();
352
db811ca0 353 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
db811ca0
CC		 354 }
355
db811ca0
CC		 356 return 0;
357}
358
359/*
360 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
361 * block. This block is identical to the rest of the I2C blocks, except that
362 * it only supports master mode, it has registers moved around, and it needs
363 * some extra init to get it into I2C mode. The register moves are handled
364 * by i2c_readl and i2c_writel
365 */
366static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
367{
368 u32 val = 0;
369 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
370 val |= DVC_CTRL_REG3_SW_PROG;
371 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
372 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
373
374 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
375 val |= DVC_CTRL_REG1_INTR_EN;
376 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
377}
378
fd301cc4
LD		 379static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
380{
381 int ret;
2a2897ba
LD		 382 if (!i2c_dev->hw->has_single_clk_source) {
383 ret = clk_prepare_enable(i2c_dev->fast_clk);
384 if (ret < 0) {
385 dev_err(i2c_dev->dev,
386 "Enabling fast clk failed, err %d\n", ret);
387 return ret;
388 }
fd301cc4
LD		 389 }
390 ret = clk_prepare_enable(i2c_dev->div_clk);
391 if (ret < 0) {
392 dev_err(i2c_dev->dev,
393 "Enabling div clk failed, err %d\n", ret);
394 clk_disable_unprepare(i2c_dev->fast_clk);
395 }
396 return ret;
397}
398
399static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
400{
401 clk_disable_unprepare(i2c_dev->div_clk);
2a2897ba
LD		 402 if (!i2c_dev->hw->has_single_clk_source)
403 clk_disable_unprepare(i2c_dev->fast_clk);
fd301cc4
LD		 404}
405
db811ca0
CC		 406static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
407{
408 u32 val;
409 int err = 0;
2a2897ba
LD		 410 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
411 u32 clk_divisor;
db811ca0 412
132c803f
LD		 413 err = tegra_i2c_clock_enable(i2c_dev);
414 if (err < 0) {
415 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
416 return err;
417 }
db811ca0 418
dda9d6a8 419 reset_control_assert(i2c_dev->rst);
db811ca0 420 udelay(2);
dda9d6a8 421 reset_control_deassert(i2c_dev->rst);
db811ca0
CC		 422
423 if (i2c_dev->is_dvc)
424 tegra_dvc_init(i2c_dev);
425
40abcf77
JC		 426 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
427 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
db811ca0
CC		 428 i2c_writel(i2c_dev, val, I2C_CNFG);
429 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
2a2897ba
LD		 430
431 clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
432 clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier);
433
434 /* Make sure clock divisor programmed correctly */
435 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
436 clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
437 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
438 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
db811ca0 439
65a1a0ac
KW		 440 if (!i2c_dev->is_dvc) {
441 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
5afa9d35
SW		 442 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
443 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
444 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
445 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
446
65a1a0ac
KW		 447 }
448
db811ca0
CC		 449 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
450 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
451 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
452
453 if (tegra_i2c_flush_fifos(i2c_dev))
454 err = -ETIMEDOUT;
455
fd301cc4 456 tegra_i2c_clock_disable(i2c_dev);
cb63c62d
TP		 457
458 if (i2c_dev->irq_disabled) {
459 i2c_dev->irq_disabled = 0;
460 enable_irq(i2c_dev->irq);
461 }
462
db811ca0
CC		 463 return err;
464}
465
466static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
467{
468 u32 status;
469 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
470 struct tegra_i2c_dev *i2c_dev = dev_id;
471
472 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
473
474 if (status == 0) {
cb63c62d
TP		 475 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
476 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
477 i2c_readl(i2c_dev, I2C_STATUS),
478 i2c_readl(i2c_dev, I2C_CNFG));
479 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
480
481 if (!i2c_dev->irq_disabled) {
482 disable_irq_nosync(i2c_dev->irq);
483 i2c_dev->irq_disabled = 1;
484 }
cb63c62d 485 goto err;
db811ca0
CC		 486 }
487
488 if (unlikely(status & status_err)) {
489 if (status & I2C_INT_NO_ACK)
490 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
491 if (status & I2C_INT_ARBITRATION_LOST)
492 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
db811ca0
CC		 493 goto err;
494 }
495
496 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
497 if (i2c_dev->msg_buf_remaining)
498 tegra_i2c_empty_rx_fifo(i2c_dev);
499 else
500 BUG();
501 }
502
503 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
504 if (i2c_dev->msg_buf_remaining)
505 tegra_i2c_fill_tx_fifo(i2c_dev);
506 else
507 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
508 }
509
c889e91d
LD		 510 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
511 if (i2c_dev->is_dvc)
512 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
513
96219c3a
DA		 514 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
515 BUG_ON(i2c_dev->msg_buf_remaining);
db811ca0 516 complete(&i2c_dev->msg_complete);
96219c3a 517 }
db811ca0
CC		 518 return IRQ_HANDLED;
519err:
25985edc 520 /* An error occurred, mask all interrupts */
db811ca0
CC		 521 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
522 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
523 I2C_INT_RX_FIFO_DATA_REQ);
524 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
cb63c62d
TP		 525 if (i2c_dev->is_dvc)
526 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
c889e91d
LD		 527
528 complete(&i2c_dev->msg_complete);
db811ca0
CC		 529 return IRQ_HANDLED;
530}
531
532static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
c8f5af2f 533 struct i2c_msg *msg, enum msg_end_type end_state)
db811ca0
CC		 534{
535 u32 packet_header;
536 u32 int_mask;
537 int ret;
538
539 tegra_i2c_flush_fifos(i2c_dev);
db811ca0
CC		 540
541 if (msg->len == 0)
542 return -EINVAL;
543
544 i2c_dev->msg_buf = msg->buf;
545 i2c_dev->msg_buf_remaining = msg->len;
546 i2c_dev->msg_err = I2C_ERR_NONE;
547 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
16735d02 548 reinit_completion(&i2c_dev->msg_complete);
db811ca0
CC		 549
550 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
551 PACKET_HEADER0_PROTOCOL_I2C |
552 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
553 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
554 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
555
556 packet_header = msg->len - 1;
557 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
558
353f56b5 559 packet_header = I2C_HEADER_IE_ENABLE;
c8f5af2f
LD		 560 if (end_state == MSG_END_CONTINUE)
561 packet_header |= I2C_HEADER_CONTINUE_XFER;
562 else if (end_state == MSG_END_REPEAT_START)
2078cf3b 563 packet_header |= I2C_HEADER_REPEAT_START;
353f56b5
LD		 564 if (msg->flags & I2C_M_TEN) {
565 packet_header |= msg->addr;
db811ca0 566 packet_header |= I2C_HEADER_10BIT_ADDR;
353f56b5
LD		 567 } else {
568 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
569 }
db811ca0
CC		 570 if (msg->flags & I2C_M_IGNORE_NAK)
571 packet_header |= I2C_HEADER_CONT_ON_NAK;
db811ca0
CC		 572 if (msg->flags & I2C_M_RD)
573 packet_header |= I2C_HEADER_READ;
574 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
575
576 if (!(msg->flags & I2C_M_RD))
577 tegra_i2c_fill_tx_fifo(i2c_dev);
578
579 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
2a2897ba
LD		 580 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
581 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
db811ca0
CC		 582 if (msg->flags & I2C_M_RD)
583 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
584 else if (i2c_dev->msg_buf_remaining)
585 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
586 tegra_i2c_unmask_irq(i2c_dev, int_mask);
587 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
588 i2c_readl(i2c_dev, I2C_INT_MASK));
589
590 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
591 tegra_i2c_mask_irq(i2c_dev, int_mask);
592
58823c72 593 if (ret == 0) {
db811ca0
CC		 594 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
595
596 tegra_i2c_init(i2c_dev);
597 return -ETIMEDOUT;
598 }
599
600 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
601 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
602
603 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
604 return 0;
605
f70893d0
AC		 606 /*
607 * NACK interrupt is generated before the I2C controller generates the
608 * STOP condition on the bus. So wait for 2 clock periods before resetting
609 * the controller so that STOP condition has been delivered properly.
610 */
611 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
612 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
613
db811ca0
CC		 614 tegra_i2c_init(i2c_dev);
615 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
616 if (msg->flags & I2C_M_IGNORE_NAK)
617 return 0;
618 return -EREMOTEIO;
619 }
620
621 return -EIO;
622}
623
624static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
625 int num)
626{
627 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
628 int i;
629 int ret = 0;
630
631 if (i2c_dev->is_suspended)
632 return -EBUSY;
633
132c803f
LD		 634 ret = tegra_i2c_clock_enable(i2c_dev);
635 if (ret < 0) {
636 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
637 return ret;
638 }
639
db811ca0 640 for (i = 0; i < num; i++) {
c8f5af2f
LD		 641 enum msg_end_type end_type = MSG_END_STOP;
642 if (i < (num - 1)) {
643 if (msgs[i + 1].flags & I2C_M_NOSTART)
644 end_type = MSG_END_CONTINUE;
645 else
646 end_type = MSG_END_REPEAT_START;
647 }
648 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
db811ca0
CC		 649 if (ret)
650 break;
651 }
fd301cc4 652 tegra_i2c_clock_disable(i2c_dev);
db811ca0
CC		 653 return ret ?: i;
654}
655
656static u32 tegra_i2c_func(struct i2c_adapter *adap)
657{
6ad068ed
LD		 658 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
659 u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
660 I2C_FUNC_PROTOCOL_MANGLING;
661
662 if (i2c_dev->hw->has_continue_xfer_support)
663 ret |= I2C_FUNC_NOSTART;
664 return ret;
db811ca0
CC		 665}
666
667static const struct i2c_algorithm tegra_i2c_algo = {
668 .master_xfer = tegra_i2c_xfer,
669 .functionality = tegra_i2c_func,
670};
671
6ad068ed
LD		 672static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
673 .has_continue_xfer_support = false,
2a2897ba
LD		 674 .has_per_pkt_xfer_complete_irq = false,
675 .has_single_clk_source = false,
676 .clk_divisor_hs_mode = 3,
677 .clk_divisor_std_fast_mode = 0,
6ad068ed
LD		 678};
679
680static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
681 .has_continue_xfer_support = true,
2a2897ba
LD		 682 .has_per_pkt_xfer_complete_irq = false,
683 .has_single_clk_source = false,
684 .clk_divisor_hs_mode = 3,
685 .clk_divisor_std_fast_mode = 0,
686};
687
688static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
689 .has_continue_xfer_support = true,
690 .has_per_pkt_xfer_complete_irq = true,
691 .has_single_clk_source = true,
692 .clk_divisor_hs_mode = 1,
693 .clk_divisor_std_fast_mode = 0x19,
6ad068ed
LD		 694};
695
6ad068ed 696/* Match table for of_platform binding */
0b255e92 697static const struct of_device_id tegra_i2c_of_match[] = {
2a2897ba 698 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
6ad068ed
LD		 699 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
700 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
701 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
702 {},
703};
704MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
6ad068ed 705
0b255e92 706static int tegra_i2c_probe(struct platform_device *pdev)
db811ca0
CC		 707{
708 struct tegra_i2c_dev *i2c_dev;
db811ca0 709 struct resource *res;
14e92bd4
LD		 710 struct clk *div_clk;
711 struct clk *fast_clk;
f533c61e 712 void __iomem *base;
db811ca0
CC		 713 int irq;
714 int ret = 0;
715
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809
TR		 717 base = devm_ioremap_resource(&pdev->dev, res);
718 if (IS_ERR(base))
719 return PTR_ERR(base);
db811ca0
CC		 720
721 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
722 if (!res) {
723 dev_err(&pdev->dev, "no irq resource\n");
9cbb6b2b 724 return -EINVAL;
db811ca0
CC		 725 }
726 irq = res->start;
727
14e92bd4
LD		 728 div_clk = devm_clk_get(&pdev->dev, "div-clk");
729 if (IS_ERR(div_clk)) {
db811ca0 730 dev_err(&pdev->dev, "missing controller clock");
14e92bd4 731 return PTR_ERR(div_clk);
db811ca0
CC		 732 }
733
9cbb6b2b 734 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
db811ca0 735 if (!i2c_dev) {
9cbb6b2b
LD		 736 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
737 return -ENOMEM;
db811ca0
CC		 738 }
739
740 i2c_dev->base = base;
14e92bd4 741 i2c_dev->div_clk = div_clk;
db811ca0
CC		 742 i2c_dev->adapter.algo = &tegra_i2c_algo;
743 i2c_dev->irq = irq;
744 i2c_dev->cont_id = pdev->id;
745 i2c_dev->dev = &pdev->dev;
5c470f39 746
dda9d6a8
SW		 747 i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
748 if (IS_ERR(i2c_dev->rst)) {
749 dev_err(&pdev->dev, "missing controller reset");
750 return PTR_ERR(i2c_dev->rst);
751 }
752
49a64ac5
SW		 753 ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
754 &i2c_dev->bus_clk_rate);
755 if (ret)
756 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
db811ca0 757
6ad068ed
LD		 758 i2c_dev->hw = &tegra20_i2c_hw;
759
760 if (pdev->dev.of_node) {
761 const struct of_device_id *match;
49a64ac5 762 match = of_match_device(tegra_i2c_of_match, &pdev->dev);
6ad068ed 763 i2c_dev->hw = match->data;
68fb6695
SW		 764 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
765 "nvidia,tegra20-i2c-dvc");
6ad068ed 766 } else if (pdev->id == 3) {
db811ca0 767 i2c_dev->is_dvc = 1;
6ad068ed 768 }
db811ca0
CC		 769 init_completion(&i2c_dev->msg_complete);
770
2a2897ba
LD		 771 if (!i2c_dev->hw->has_single_clk_source) {
772 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
773 if (IS_ERR(fast_clk)) {
774 dev_err(&pdev->dev, "missing fast clock");
775 return PTR_ERR(fast_clk);
776 }
777 i2c_dev->fast_clk = fast_clk;
778 }
779
db811ca0
CC		 780 platform_set_drvdata(pdev, i2c_dev);
781
782 ret = tegra_i2c_init(i2c_dev);
783 if (ret) {
784 dev_err(&pdev->dev, "Failed to initialize i2c controller");
9cbb6b2b 785 return ret;
db811ca0
CC		 786 }
787
9cbb6b2b 788 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
91b370a0 789 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
db811ca0
CC		 790 if (ret) {
791 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
9cbb6b2b 792 return ret;
db811ca0
CC		 793 }
794
db811ca0
CC		 795 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
796 i2c_dev->adapter.owner = THIS_MODULE;
797 i2c_dev->adapter.class = I2C_CLASS_HWMON;
798 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
799 sizeof(i2c_dev->adapter.name));
800 i2c_dev->adapter.algo = &tegra_i2c_algo;
801 i2c_dev->adapter.dev.parent = &pdev->dev;
802 i2c_dev->adapter.nr = pdev->id;
5c470f39 803 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
db811ca0
CC		 804
805 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
806 if (ret) {
807 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
9cbb6b2b 808 return ret;
db811ca0
CC		 809 }
810
811 return 0;
db811ca0
CC		 812}
813
0b255e92 814static int tegra_i2c_remove(struct platform_device *pdev)
db811ca0
CC		 815{
816 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
817 i2c_del_adapter(&i2c_dev->adapter);
db811ca0
CC		 818 return 0;
819}
820
371e67c9 821#ifdef CONFIG_PM_SLEEP
5db20c49 822static int tegra_i2c_suspend(struct device *dev)
db811ca0 823{
6a7b3c3c 824 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
db811ca0
CC		 825
826 i2c_lock_adapter(&i2c_dev->adapter);
827 i2c_dev->is_suspended = true;
828 i2c_unlock_adapter(&i2c_dev->adapter);
829
830 return 0;
831}
832
5db20c49 833static int tegra_i2c_resume(struct device *dev)
db811ca0 834{
6a7b3c3c 835 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
db811ca0
CC		 836 int ret;
837
838 i2c_lock_adapter(&i2c_dev->adapter);
839
840 ret = tegra_i2c_init(i2c_dev);
841
842 if (ret) {
843 i2c_unlock_adapter(&i2c_dev->adapter);
844 return ret;
845 }
846
847 i2c_dev->is_suspended = false;
848
849 i2c_unlock_adapter(&i2c_dev->adapter);
850
851 return 0;
852}
6a7b3c3c 853
5db20c49 854static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
6a7b3c3c
RW		 855#define TEGRA_I2C_PM (&tegra_i2c_pm)
856#else
857#define TEGRA_I2C_PM NULL
db811ca0
CC		 858#endif
859
860static struct platform_driver tegra_i2c_driver = {
861 .probe = tegra_i2c_probe,
0b255e92 862 .remove = tegra_i2c_remove,
db811ca0
CC		 863 .driver = {
864 .name = "tegra-i2c",
865 .owner = THIS_MODULE,
49a64ac5 866 .of_match_table = tegra_i2c_of_match,
6a7b3c3c 867 .pm = TEGRA_I2C_PM,
db811ca0
CC		 868 },
869};
870
871static int __init tegra_i2c_init_driver(void)
872{
873 return platform_driver_register(&tegra_i2c_driver);
874}
875
876static void __exit tegra_i2c_exit_driver(void)
877{
878 platform_driver_unregister(&tegra_i2c_driver);
879}
880
881subsys_initcall(tegra_i2c_init_driver);
882module_exit(tegra_i2c_exit_driver);
883
884MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
885MODULE_AUTHOR("Colin Cross");
886MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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