[deliverable/linux.git] / drivers / ide / cmd64x.c

/*
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cmd64x"

#define CMD_DEBUG 0

#if CMD_DEBUG
#define cmdprintk(x...)	printk(x)
#else
#define cmdprintk(x...)
#endif

/*
 * CMD64x specific registers definition.
 */
#define CFR		0x50
#define   CFR_INTR_CH0		0x04

#define	CMDTIM		0x52
#define	ARTTIM0		0x53
#define	DRWTIM0		0x54
#define ARTTIM1 	0x55
#define DRWTIM1		0x56
#define ARTTIM23	0x57
#define   ARTTIM23_DIS_RA2	0x04
#define   ARTTIM23_DIS_RA3	0x08
#define   ARTTIM23_INTR_CH1	0x10
#define DRWTIM2		0x58
#define BRST		0x59
#define DRWTIM3		0x5b

#define BMIDECR0	0x70
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define UDIDETCR0	0x73
#define DTPR0		0x74
#define BMIDECR1	0x78
#define BMIDECSR	0x79
#define UDIDETCR1	0x7B
#define DTPR1		0x7C

static u8 quantize_timing(int timing, int quant)
{
	return (timing + quant - 1) / quant;
}

/*
 * This routine calculates active/recovery counts and then writes them into
 * the chipset registers.
 */
static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
	u8  cycle_count, active_count, recovery_count, drwtim;
	static const u8 recovery_values[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};

	cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
		  cycle_time, active_time);

	cycle_count	= quantize_timing( cycle_time, clock_time);
	active_count	= quantize_timing(active_time, clock_time);
	recovery_count	= cycle_count - active_count;

	/*
	 * In case we've got too long recovery phase, try to lengthen
	 * the active phase
	 */
	if (recovery_count > 16) {
		active_count += recovery_count - 16;
		recovery_count = 16;
	}
	if (active_count > 16)		/* shouldn't actually happen... */
	 	active_count = 16;

	cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
		  cycle_count, active_count, recovery_count);

	/*
	 * Convert values to internal chipset representation
	 */
	recovery_count = recovery_values[recovery_count];
 	active_count  &= 0x0f;

	/* Program the active/recovery counts into the DRWTIM register */
	drwtim = (active_count << 4) | recovery_count;
	(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
	cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
}

/*
 * This routine writes into the chipset registers
 * PIO setup/active/recovery timings.
 */
static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_timing *t	= ide_timing_find_mode(XFER_PIO_0 + pio);
	unsigned int cycle_time;
	u8 setup_count, arttim = 0;

	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};

	cycle_time = ide_pio_cycle_time(drive, pio);

	program_cycle_times(drive, cycle_time, t->active);

	setup_count = quantize_timing(t->setup,
			1000 / (ide_pci_clk ? ide_pci_clk : 33));

	/*
	 * The primary channel has individual address setup timing registers
	 * for each drive and the hardware selects the slowest timing itself.
	 * The secondary channel has one common register and we have to select
	 * the slowest address setup timing ourselves.
	 */
	if (hwif->channel) {
		ide_drive_t *pair = ide_get_pair_dev(drive);

		drive->drive_data = setup_count;

		if (pair)
			setup_count = max_t(u8, setup_count, pair->drive_data);
	}

	if (setup_count > 5)		/* shouldn't actually happen... */
		setup_count = 5;
	cmdprintk("Final address setup count: %d\n", setup_count);

	/*
	 * Program the address setup clocks into the ARTTIM registers.
	 * Avoid clearing the secondary channel's interrupt bit.
	 */
	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	if (hwif->channel)
		arttim &= ~ARTTIM23_INTR_CH1;
	arttim &= ~0xc0;
	arttim |= setup_values[setup_count];
	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
	cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
}

/*
 * Attempts to set drive's PIO mode.
 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 */

static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	/*
	 * Filter out the prefetch control values
	 * to prevent PIO5 from being programmed
	 */
	if (pio == 8 || pio == 9)
		return;

	cmd64x_tune_pio(drive, pio);
}

static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= drive->dn & 0x01;
	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;

	if (speed >= XFER_SW_DMA_0) {
		(void) pci_read_config_byte(dev, pciU, &regU);
		regU &= ~(unit ? 0xCA : 0x35);
	}

	switch(speed) {
	case XFER_UDMA_5:
		regU |= unit ? 0x0A : 0x05;
		break;
	case XFER_UDMA_4:
		regU |= unit ? 0x4A : 0x15;
		break;
	case XFER_UDMA_3:
		regU |= unit ? 0x8A : 0x25;
		break;
	case XFER_UDMA_2:
		regU |= unit ? 0x42 : 0x11;
		break;
	case XFER_UDMA_1:
		regU |= unit ? 0x82 : 0x21;
		break;
	case XFER_UDMA_0:
		regU |= unit ? 0xC2 : 0x31;
		break;
	case XFER_MW_DMA_2:
		program_cycle_times(drive, 120, 70);
		break;
	case XFER_MW_DMA_1:
		program_cycle_times(drive, 150, 80);
		break;
	case XFER_MW_DMA_0:
		program_cycle_times(drive, 480, 215);
		break;
	}

	if (speed >= XFER_SW_DMA_0)
		(void) pci_write_config_byte(dev, pciU, regU);
}

static void cmd648_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8  mrdmode		= inb(base + 1);

	/* clear the interrupt bit */
	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
	     base + 1);
}

static void cmd64x_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	/* clear the interrupt bit */
	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
}

static int cmd648_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	unsigned long base	= hwif->dma_base - (hwif->channel * 8);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8 mrdmode		= inb(base + 1);

#ifdef DEBUG
	printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
	       drive->name, dma_stat, mrdmode, irq_mask);
#endif
	if (!(mrdmode & irq_mask))
		return 0;

	/* return 1 if INTR asserted */
	if (dma_stat & 4)
		return 1;

	return 0;
}

static int cmd64x_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);

#ifdef DEBUG
	printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
	       drive->name, dma_stat, irq_stat, irq_mask);
#endif
	if (!(irq_stat & irq_mask))
		return 0;

	/* return 1 if INTR asserted */
	if (dma_stat & 4)
		return 1;

	return 0;
}

/*
 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 * event order for DMA transfers.
 */

static int cmd646_1_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* get DMA status */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int init_chipset_cmd64x(struct pci_dev *dev)
{
	u8 mrdmode = 0;

	/* Set a good latency timer and cache line size value. */
	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	/* FIXME: pci_set_master() to ensure a good latency timer value */

	/*
	 * Enable interrupts, select MEMORY READ LINE for reads.
	 *
	 * NOTE: although not mentioned in the PCI0646U specs,
	 * bits 0-1 are write only and won't be read back as
	 * set or not -- PCI0646U2 specs clarify this point.
	 */
	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;
	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));

	return 0;
}

static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	switch (dev->device) {
	case PCI_DEVICE_ID_CMD_648:
	case PCI_DEVICE_ID_CMD_649:
 		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	default:
		return ATA_CBL_PATA40;
	}
}

static const struct ide_port_ops cmd64x_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd64x_clear_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_port_ops cmd648_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd648_clear_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_dma_ops cmd64x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= ide_dma_end,
	.dma_test_irq		= cmd64x_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= cmd646_1_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_dma_ops cmd648_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= ide_dma_end,
	.dma_test_irq		= cmd648_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
	{	/* 0: CMD643 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
		.port_ops	= &cmd64x_port_ops,
		.dma_ops	= &cmd64x_dma_ops,
		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
				  IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* no udma */
	},
	{	/* 1: CMD646 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.dma_ops	= &cmd648_dma_ops,
		.host_flags	= IDE_HFLAG_SERIALIZE |
				  IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 2: CMD648 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.dma_ops	= &cmd648_dma_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: CMD649 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.dma_ops	= &cmd648_dma_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = cmd64x_chipsets[idx];

	if (idx == 1) {
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
		if (dev->revision < 5) {
			d.udma_mask = 0x00;
			/*
			 * The original PCI0646 didn't have the primary
			 * channel enable bit, it appeared starting with
			 * PCI0646U (i.e. revision ID 3).
			 */
			if (dev->revision < 3) {
				d.enablebits[0].reg = 0;
				d.port_ops = &cmd64x_port_ops;
				if (dev->revision == 1)
					d.dma_ops = &cmd646_rev1_dma_ops;
				else
					d.dma_ops = &cmd64x_dma_ops;
			}
		}
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id cmd64x_pci_tbl[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);

static struct pci_driver cmd64x_pci_driver = {
	.name		= "CMD64x_IDE",
	.id_table	= cmd64x_pci_tbl,
	.probe		= cmd64x_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cmd64x_ide_init(void)
{
	return ide_pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_ide_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

module_init(cmd64x_ide_init);
module_exit(cmd64x_ide_exit);

MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
60e7a82f	1	/*
1da177e4	2	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4 LT	3	* Due to massive hardware bugs, UltraDMA is only supported
	4	* on the 646U2 and not on the 646U.
	5	*
	6	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	7	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	8	*
	9	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
30e5ffc3	10	* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	11	*/
1da177e4 LT	12
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/types.h>
	15	#include <linux/pci.h>
1da177e4 LT	16	#include <linux/ide.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
ced3ec8a BZ	21	#define DRV_NAME "cmd64x"
ced3ec8a BZ	22
1da177e4 LT	23	#define CMD_DEBUG 0
	24
	25	#if CMD_DEBUG
	26	#define cmdprintk(x...) printk(x)
	27	#else
	28	#define cmdprintk(x...)
	29	#endif
	30
	31	/*
	32	* CMD64x specific registers definition.
	33	*/
	34	#define CFR 0x50
e51e2528	35	#define CFR_INTR_CH0 0x04
1da177e4 LT	36
	37	#define CMDTIM 0x52
	38	#define ARTTIM0 0x53
	39	#define DRWTIM0 0x54
	40	#define ARTTIM1 0x55
	41	#define DRWTIM1 0x56
	42	#define ARTTIM23 0x57
	43	#define ARTTIM23_DIS_RA2 0x04
	44	#define ARTTIM23_DIS_RA3 0x08
	45	#define ARTTIM23_INTR_CH1 0x10
1da177e4 LT	46	#define DRWTIM2 0x58
	47	#define BRST 0x59
	48	#define DRWTIM3 0x5b
	49
	50	#define BMIDECR0 0x70
	51	#define MRDMODE 0x71
	52	#define MRDMODE_INTR_CH0 0x04
	53	#define MRDMODE_INTR_CH1 0x08
1da177e4 LT	54	#define UDIDETCR0 0x73
	55	#define DTPR0 0x74
	56	#define BMIDECR1 0x78
	57	#define BMIDECSR 0x79
1da177e4 LT	58	#define UDIDETCR1 0x7B
	59	#define DTPR1 0x7C
	60
e277a1aa SS	61	static u8 quantize_timing(int timing, int quant)
	62	{
	63	return (timing + quant - 1) / quant;
	64	}
	65
1da177e4	66	/*
60e7a82f SS	67	* This routine calculates active/recovery counts and then writes them into
60e7a82f SS	68	* the chipset registers.
1da177e4	69	*/
60e7a82f	70	static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
1da177e4	71	{
ebae41a5	72	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
30e5ee4d	73	int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
60e7a82f SS	74	u8 cycle_count, active_count, recovery_count, drwtim;
60e7a82f SS	75	static const u8 recovery_values[] =
1da177e4	76	{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60e7a82f SS	77	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
	78
	79	cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
	80	cycle_time, active_time);
	81
	82	cycle_count = quantize_timing( cycle_time, clock_time);
	83	active_count = quantize_timing(active_time, clock_time);
	84	recovery_count = cycle_count - active_count;
	85
1da177e4	86	/*
60e7a82f SS	87	* In case we've got too long recovery phase, try to lengthen
60e7a82f SS	88	* the active phase
1da177e4	89	*/
60e7a82f SS	90	if (recovery_count > 16) {
	91	active_count += recovery_count - 16;
	92	recovery_count = 16;
1da177e4	93	}
60e7a82f SS	94	if (active_count > 16) /* shouldn't actually happen... */
	95	active_count = 16;
	96
	97	cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
	98	cycle_count, active_count, recovery_count);
1da177e4 LT	99
	100	/*
	101	* Convert values to internal chipset representation
	102	*/
60e7a82f SS	103	recovery_count = recovery_values[recovery_count];
60e7a82f SS	104	active_count &= 0x0f;
1da177e4	105
60e7a82f SS	106	/* Program the active/recovery counts into the DRWTIM register */
	107	drwtim = (active_count << 4) \| recovery_count;
	108	(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
	109	cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
1da177e4 LT	110	}
	111
	112	/*
26bcb879 BZ	113	* This routine writes into the chipset registers
26bcb879 BZ	114	* PIO setup/active/recovery timings.
1da177e4	115	*/
26bcb879	116	static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
1da177e4	117	{
898ec223	118	ide_hwif_t *hwif = drive->hwif;
36501650	119	struct pci_dev *dev = to_pci_dev(hwif->dev);
86a0e12f	120	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
7dd00083	121	unsigned int cycle_time;
26bcb879 BZ	122	u8 setup_count, arttim = 0;
26bcb879 BZ	123
60e7a82f SS	124	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
60e7a82f SS	125	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
7dd00083	126
26bcb879	127	cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4	128
86a0e12f	129	program_cycle_times(drive, cycle_time, t->active);
1da177e4	130
86a0e12f	131	setup_count = quantize_timing(t->setup,
30e5ee4d	132	1000 / (ide_pci_clk ? ide_pci_clk : 33));
60e7a82f SS	133
	134	/*
	135	* The primary channel has individual address setup timing registers
	136	* for each drive and the hardware selects the slowest timing itself.
	137	* The secondary channel has one common register and we have to select
	138	* the slowest address setup timing ourselves.
	139	*/
	140	if (hwif->channel) {
5d44a150	141	ide_drive_t *pair = ide_get_pair_dev(drive);
60e7a82f SS	142
60e7a82f SS	143	drive->drive_data = setup_count;
5d44a150 BZ	144
	145	if (pair)
	146	setup_count = max_t(u8, setup_count, pair->drive_data);
1da177e4	147	}
1da177e4	148
60e7a82f SS	149	if (setup_count > 5) /* shouldn't actually happen... */
	150	setup_count = 5;
	151	cmdprintk("Final address setup count: %d\n", setup_count);
1da177e4	152
60e7a82f SS	153	/*
	154	* Program the address setup clocks into the ARTTIM registers.
	155	* Avoid clearing the secondary channel's interrupt bit.
	156	*/
	157	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	158	if (hwif->channel)
	159	arttim &= ~ARTTIM23_INTR_CH1;
	160	arttim &= ~0xc0;
	161	arttim \|= setup_values[setup_count];
	162	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
	163	cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
f92d50e6 SS	164	}
	165
	166	/*
	167	* Attempts to set drive's PIO mode.
26bcb879	168	* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
f92d50e6	169	*/
26bcb879 BZ	170
26bcb879 BZ	171	static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
f92d50e6 SS	172	{
	173	/*
	174	* Filter out the prefetch control values
	175	* to prevent PIO5 from being programmed
	176	*/
	177	if (pio == 8 \|\| pio == 9)
	178	return;
	179
26bcb879	180	cmd64x_tune_pio(drive, pio);
1da177e4 LT	181	}
1da177e4 LT	182
88b2b32b	183	static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	184	{
898ec223	185	ide_hwif_t *hwif = drive->hwif;
36501650	186	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e7a82f SS	187	u8 unit = drive->dn & 0x01;
60e7a82f SS	188	u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4	189
f92d50e6	190	if (speed >= XFER_SW_DMA_0) {
1da177e4	191	(void) pci_read_config_byte(dev, pciU, &regU);
1da177e4	192	regU &= ~(unit ? 0xCA : 0x35);
1da177e4 LT	193	}
	194
	195	switch(speed) {
60e7a82f SS	196	case XFER_UDMA_5:
	197	regU \|= unit ? 0x0A : 0x05;
	198	break;
	199	case XFER_UDMA_4:
	200	regU \|= unit ? 0x4A : 0x15;
	201	break;
	202	case XFER_UDMA_3:
	203	regU \|= unit ? 0x8A : 0x25;
	204	break;
	205	case XFER_UDMA_2:
	206	regU \|= unit ? 0x42 : 0x11;
	207	break;
	208	case XFER_UDMA_1:
	209	regU \|= unit ? 0x82 : 0x21;
	210	break;
	211	case XFER_UDMA_0:
	212	regU \|= unit ? 0xC2 : 0x31;
	213	break;
	214	case XFER_MW_DMA_2:
	215	program_cycle_times(drive, 120, 70);
	216	break;
	217	case XFER_MW_DMA_1:
	218	program_cycle_times(drive, 150, 80);
	219	break;
	220	case XFER_MW_DMA_0:
	221	program_cycle_times(drive, 480, 215);
	222	break;
1da177e4 LT	223	}
1da177e4 LT	224
60e7a82f	225	if (speed >= XFER_SW_DMA_0)
1da177e4	226	(void) pci_write_config_byte(dev, pciU, regU);
1da177e4 LT	227	}
1da177e4 LT	228
30e5ffc3	229	static void cmd648_clear_irq(ide_drive_t *drive)
1da177e4	230	{
898ec223	231	ide_hwif_t *hwif = drive->hwif;
30e5ffc3 SS	232	struct pci_dev *dev = to_pci_dev(hwif->dev);
30e5ffc3 SS	233	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	234	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	235	MRDMODE_INTR_CH0;
1c029fd6	236	u8 mrdmode = inb(base + 1);
66602c83 SS	237
66602c83 SS	238	/* clear the interrupt bit */
6183289c	239	outb((mrdmode & ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1)) \| irq_mask,
1c029fd6	240	base + 1);
1da177e4 LT	241	}
1da177e4 LT	242
30e5ffc3	243	static void cmd64x_clear_irq(ide_drive_t *drive)
1da177e4	244	{
898ec223	245	ide_hwif_t *hwif = drive->hwif;
36501650	246	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	247	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	248	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	249	CFR_INTR_CH0;
	250	u8 irq_stat = 0;
1da177e4	251
66602c83 SS	252	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	253	/* clear the interrupt bit */
	254	(void) pci_write_config_byte(dev, irq_reg, irq_stat \| irq_mask);
66602c83 SS	255	}
66602c83 SS	256
5e37bdc0	257	static int cmd648_dma_test_irq(ide_drive_t *drive)
66602c83	258	{
898ec223	259	ide_hwif_t *hwif = drive->hwif;
1c029fd6	260	unsigned long base = hwif->dma_base - (hwif->channel * 8);
66602c83 SS	261	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	262	MRDMODE_INTR_CH0;
cab7f8ed	263	u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1c029fd6	264	u8 mrdmode = inb(base + 1);
66602c83 SS	265
	266	#ifdef DEBUG
	267	printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
	268	drive->name, dma_stat, mrdmode, irq_mask);
	269	#endif
	270	if (!(mrdmode & irq_mask))
	271	return 0;
	272
	273	/* return 1 if INTR asserted */
	274	if (dma_stat & 4)
	275	return 1;
	276
	277	return 0;
1da177e4 LT	278	}
1da177e4 LT	279
5e37bdc0	280	static int cmd64x_dma_test_irq(ide_drive_t *drive)
1da177e4	281	{
898ec223	282	ide_hwif_t *hwif = drive->hwif;
36501650	283	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	284	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	285	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	286	CFR_INTR_CH0;
cab7f8ed	287	u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
66602c83	288	u8 irq_stat = 0;
e51e2528 SS	289
e51e2528 SS	290	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4	291
1da177e4	292	#ifdef DEBUG
66602c83 SS	293	printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
66602c83 SS	294	drive->name, dma_stat, irq_stat, irq_mask);
1da177e4	295	#endif
66602c83	296	if (!(irq_stat & irq_mask))
1da177e4 LT	297	return 0;
	298
	299	/* return 1 if INTR asserted */
66602c83	300	if (dma_stat & 4)
1da177e4 LT	301	return 1;
	302
	303	return 0;
	304	}
	305
	306	/*
	307	* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
	308	* event order for DMA transfers.
	309	*/
	310
5e37bdc0	311	static int cmd646_1_dma_end(ide_drive_t *drive)
1da177e4	312	{
898ec223	313	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	314	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	315
1da177e4	316	/* get DMA status */
cab7f8ed	317	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1da177e4	318	/* read DMA command state */
cab7f8ed	319	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	320	/* stop DMA */
cab7f8ed	321	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	322	/* clear the INTR & ERROR bits */
cab7f8ed	323	outb(dma_stat \| 6, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	324	/* verify good DMA status */
	325	return (dma_stat & 7) != 4;
	326	}
	327
2ed0ef54	328	static int init_chipset_cmd64x(struct pci_dev *dev)
1da177e4	329	{
1da177e4 LT	330	u8 mrdmode = 0;
1da177e4 LT	331
1da177e4 LT	332	/* Set a good latency timer and cache line size value. */
	333	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	334	/* FIXME: pci_set_master() to ensure a good latency timer value */
	335
83a6d4ab SS	336	/*
	337	* Enable interrupts, select MEMORY READ LINE for reads.
	338	*
	339	* NOTE: although not mentioned in the PCI0646U specs,
	340	* bits 0-1 are write only and won't be read back as
	341	* set or not -- PCI0646U2 specs clarify this point.
1da177e4	342	*/
83a6d4ab SS	343	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	344	mrdmode &= ~0x30;
	345	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode \| 0x02));
1da177e4	346
1da177e4 LT	347	return 0;
	348	}
	349
f454cbe8	350	static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
1da177e4	351	{
36501650	352	struct pci_dev *dev = to_pci_dev(hwif->dev);
83a6d4ab	353	u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4	354
83a6d4ab SS	355	switch (dev->device) {
	356	case PCI_DEVICE_ID_CMD_648:
	357	case PCI_DEVICE_ID_CMD_649:
	358	pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97	359	return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab	360	default:
49521f97	361	return ATA_CBL_PATA40;
1da177e4	362	}
1da177e4 LT	363	}
1da177e4 LT	364
ac95beed BZ	365	static const struct ide_port_ops cmd64x_port_ops = {
	366	.set_pio_mode = cmd64x_set_pio_mode,
	367	.set_dma_mode = cmd64x_set_dma_mode,
30e5ffc3 SS	368	.clear_irq = cmd64x_clear_irq,
	369	.cable_detect = cmd64x_cable_detect,
	370	};
	371
	372	static const struct ide_port_ops cmd648_port_ops = {
	373	.set_pio_mode = cmd64x_set_pio_mode,
	374	.set_dma_mode = cmd64x_set_dma_mode,
	375	.clear_irq = cmd648_clear_irq,
ac95beed BZ	376	.cable_detect = cmd64x_cable_detect,
	377	};
	378
f37afdac BZ	379	static const struct ide_dma_ops cmd64x_dma_ops = {
	380	.dma_host_set = ide_dma_host_set,
	381	.dma_setup = ide_dma_setup,
f37afdac	382	.dma_start = ide_dma_start,
30e5ffc3	383	.dma_end = ide_dma_end,
5e37bdc0	384	.dma_test_irq = cmd64x_dma_test_irq,
f37afdac	385	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	386	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	387	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	388	};
5e37bdc0 BZ	389
f37afdac BZ	390	static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	391	.dma_host_set = ide_dma_host_set,
	392	.dma_setup = ide_dma_setup,
f37afdac	393	.dma_start = ide_dma_start,
5e37bdc0	394	.dma_end = cmd646_1_dma_end,
f37afdac BZ	395	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	396	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	397	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	398	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	399	};
5e37bdc0 BZ	400
f37afdac BZ	401	static const struct ide_dma_ops cmd648_dma_ops = {
	402	.dma_host_set = ide_dma_host_set,
	403	.dma_setup = ide_dma_setup,
f37afdac	404	.dma_start = ide_dma_start,
30e5ffc3	405	.dma_end = ide_dma_end,
5e37bdc0	406	.dma_test_irq = cmd648_dma_test_irq,
f37afdac	407	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	408	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	409	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	410	};
5e37bdc0 BZ	411
85620436	412	static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
ced3ec8a BZ	413	{ /* 0: CMD643 */
ced3ec8a BZ	414	.name = DRV_NAME,
1da177e4	415	.init_chipset = init_chipset_cmd64x,
7accbffd	416	.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
ac95beed	417	.port_ops = &cmd64x_port_ops,
5e37bdc0	418	.dma_ops = &cmd64x_dma_ops,
8ac2b42a	419	.host_flags = IDE_HFLAG_CLEAR_SIMPLEX \|
5e71d9c5	420	IDE_HFLAG_ABUSE_PREFETCH,
4099d143	421	.pio_mask = ATA_PIO5,
5f8b6c34	422	.mwdma_mask = ATA_MWDMA2,
18137207	423	.udma_mask = 0x00, /* no udma */
ced3ec8a BZ	424	},
	425	{ /* 1: CMD646 */
	426	.name = DRV_NAME,
1da177e4	427	.init_chipset = init_chipset_cmd64x,
7accbffd	428	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	429	.port_ops = &cmd648_port_ops,
5e37bdc0	430	.dma_ops = &cmd648_dma_ops,
6b5cde36 BZ	431	.host_flags = IDE_HFLAG_SERIALIZE \|
6b5cde36 BZ	432	IDE_HFLAG_ABUSE_PREFETCH,
4099d143	433	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	434	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	435	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	436	},
	437	{ /* 2: CMD648 */
	438	.name = DRV_NAME,
1da177e4	439	.init_chipset = init_chipset_cmd64x,
7accbffd	440	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	441	.port_ops = &cmd648_port_ops,
5e37bdc0	442	.dma_ops = &cmd648_dma_ops,
5e71d9c5	443	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	444	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	445	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	446	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	447	},
	448	{ /* 3: CMD649 */
	449	.name = DRV_NAME,
1da177e4	450	.init_chipset = init_chipset_cmd64x,
7accbffd	451	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	452	.port_ops = &cmd648_port_ops,
5e37bdc0	453	.dma_ops = &cmd648_dma_ops,
5e71d9c5	454	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	455	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	456	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	457	.udma_mask = ATA_UDMA5,
1da177e4 LT	458	}
	459	};
	460
	461	static int __devinit cmd64x_init_one(struct pci_dev dev, const struct pci_device_id id)
	462	{
039788e1	463	struct ide_port_info d;
bfd314a3 BZ	464	u8 idx = id->driver_data;
	465
	466	d = cmd64x_chipsets[idx];
	467
5e37bdc0 BZ	468	if (idx == 1) {
	469	/*
	470	* UltraDMA only supported on PCI646U and PCI646U2, which
	471	* correspond to revisions 0x03, 0x05 and 0x07 respectively.
	472	* Actually, although the CMD tech support people won't
	473	* tell me the details, the 0x03 revision cannot support
	474	* UDMA correctly without hardware modifications, and even
	475	* then it only works with Quantum disks due to some
	476	* hold time assumptions in the 646U part which are fixed
	477	* in the 646U2.
	478	*
	479	* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
	480	*/
	481	if (dev->revision < 5) {
	482	d.udma_mask = 0x00;
	483	/*
	484	* The original PCI0646 didn't have the primary
	485	* channel enable bit, it appeared starting with
	486	* PCI0646U (i.e. revision ID 3).
	487	*/
	488	if (dev->revision < 3) {
	489	d.enablebits[0].reg = 0;
30e5ffc3	490	d.port_ops = &cmd64x_port_ops;
5e37bdc0 BZ	491	if (dev->revision == 1)
	492	d.dma_ops = &cmd646_rev1_dma_ops;
	493	else
	494	d.dma_ops = &cmd64x_dma_ops;
	495	}
	496	}
	497	}
7accbffd	498
6cdf6eb3	499	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	500	}
1da177e4 LT	501
9cbcc5e3 BZ	502	static const struct pci_device_id cmd64x_pci_tbl[] = {
	503	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	504	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	505	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	506	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
1da177e4 LT	507	{ 0, },
	508	};
	509	MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
	510
a9ab09e2	511	static struct pci_driver cmd64x_pci_driver = {
1da177e4 LT	512	.name = "CMD64x_IDE",
	513	.id_table = cmd64x_pci_tbl,
	514	.probe = cmd64x_init_one,
e2b15b47	515	.remove = ide_pci_remove,
feb22b7f BZ	516	.suspend = ide_pci_suspend,
feb22b7f BZ	517	.resume = ide_pci_resume,
1da177e4 LT	518	};
1da177e4 LT	519
82ab1eec	520	static int __init cmd64x_ide_init(void)
1da177e4	521	{
a9ab09e2	522	return ide_pci_register_driver(&cmd64x_pci_driver);
1da177e4 LT	523	}
1da177e4 LT	524
e2b15b47 BZ	525	static void __exit cmd64x_ide_exit(void)
e2b15b47 BZ	526	{
a9ab09e2	527	pci_unregister_driver(&cmd64x_pci_driver);
e2b15b47 BZ	528	}
e2b15b47 BZ	529
1da177e4	530	module_init(cmd64x_ide_init);
e2b15b47	531	module_exit(cmd64x_ide_exit);
1da177e4 LT	532
	533	MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
	534	MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
	535	MODULE_LICENSE("GPL");