Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
204f47c5 BZ |
2 | * IDE DMA support (including IDE PCI BM-DMA). |
3 | * | |
59bca8cc BZ |
4 | * Copyright (C) 1995-1998 Mark Lord |
5 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 7 | * |
1da177e4 | 8 | * May be copied or modified under the terms of the GNU General Public License |
204f47c5 BZ |
9 | * |
10 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * Special Thanks to Mark for his Six years of work. | |
1da177e4 LT |
15 | */ |
16 | ||
17 | /* | |
1da177e4 LT |
18 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for |
19 | * fixing the problem with the BIOS on some Acer motherboards. | |
20 | * | |
21 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
22 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
23 | * | |
24 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
25 | * at generic DMA -- his patches were referred to when preparing this code. | |
26 | * | |
27 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
28 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/types.h> |
32 | #include <linux/kernel.h> | |
1da177e4 | 33 | #include <linux/ide.h> |
1da177e4 | 34 | #include <linux/scatterlist.h> |
5c05ff68 | 35 | #include <linux/dma-mapping.h> |
1da177e4 | 36 | |
db3f99ef | 37 | static const struct drive_list_entry drive_whitelist[] = { |
c2d3ce8c JH |
38 | { "Micropolis 2112A" , NULL }, |
39 | { "CONNER CTMA 4000" , NULL }, | |
40 | { "CONNER CTT8000-A" , NULL }, | |
41 | { "ST34342A" , NULL }, | |
1da177e4 LT |
42 | { NULL , NULL } |
43 | }; | |
44 | ||
db3f99ef | 45 | static const struct drive_list_entry drive_blacklist[] = { |
c2d3ce8c JH |
46 | { "WDC AC11000H" , NULL }, |
47 | { "WDC AC22100H" , NULL }, | |
48 | { "WDC AC32500H" , NULL }, | |
49 | { "WDC AC33100H" , NULL }, | |
50 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
51 | { "WDC AC32100H" , "24.09P07" }, |
52 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
53 | { "Compaq CRD-8241B" , NULL }, |
54 | { "CRD-8400B" , NULL }, | |
55 | { "CRD-8480B", NULL }, | |
56 | { "CRD-8482B", NULL }, | |
57 | { "CRD-84" , NULL }, | |
58 | { "SanDisk SDP3B" , NULL }, | |
59 | { "SanDisk SDP3B-64" , NULL }, | |
60 | { "SANYO CD-ROM CRD" , NULL }, | |
61 | { "HITACHI CDR-8" , NULL }, | |
62 | { "HITACHI CDR-8335" , NULL }, | |
63 | { "HITACHI CDR-8435" , NULL }, | |
64 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
65 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
66 | { "CD-532E-A" , NULL }, | |
67 | { "E-IDE CD-ROM CR-840", NULL }, | |
68 | { "CD-ROM Drive/F5A", NULL }, | |
69 | { "WPI CDD-820", NULL }, | |
70 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
71 | { "SAMSUNG CD-ROM SC", NULL }, | |
72 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
73 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 74 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 75 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 76 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
77 | { NULL , NULL } |
78 | ||
79 | }; | |
80 | ||
1da177e4 LT |
81 | /** |
82 | * ide_dma_intr - IDE DMA interrupt handler | |
83 | * @drive: the drive the interrupt is for | |
84 | * | |
db3f99ef | 85 | * Handle an interrupt completing a read/write DMA transfer on an |
1da177e4 LT |
86 | * IDE device |
87 | */ | |
db3f99ef BZ |
88 | |
89 | ide_startstop_t ide_dma_intr(ide_drive_t *drive) | |
1da177e4 | 90 | { |
b73c7ee2 | 91 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 LT |
92 | u8 stat = 0, dma_stat = 0; |
93 | ||
b73c7ee2 | 94 | dma_stat = hwif->dma_ops->dma_end(drive); |
4453011f | 95 | ide_destroy_dmatable(drive); |
374e042c | 96 | stat = hwif->tp_ops->read_status(hwif); |
c47137a9 | 97 | |
3a7d2484 | 98 | if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) { |
1da177e4 | 99 | if (!dma_stat) { |
adb1af98 | 100 | struct ide_cmd *cmd = &hwif->cmd; |
1da177e4 | 101 | |
2230d90d BZ |
102 | if ((cmd->tf_flags & IDE_TFLAG_FS) == 0) |
103 | ide_finish_cmd(drive, cmd, stat); | |
104 | else | |
130e8867 BZ |
105 | ide_complete_rq(drive, 0, |
106 | cmd->rq->nr_sectors << 9); | |
1da177e4 LT |
107 | return ide_stopped; |
108 | } | |
db3f99ef BZ |
109 | printk(KERN_ERR "%s: %s: bad DMA status (0x%02x)\n", |
110 | drive->name, __func__, dma_stat); | |
1da177e4 LT |
111 | } |
112 | return ide_error(drive, "dma_intr", stat); | |
113 | } | |
1da177e4 | 114 | |
2dbe7e91 | 115 | int ide_dma_good_drive(ide_drive_t *drive) |
75d7d963 BZ |
116 | { |
117 | return ide_in_drive_list(drive->id, drive_whitelist); | |
118 | } | |
119 | ||
1da177e4 LT |
120 | /** |
121 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
122 | * @drive: the drive to build the DMA table for | |
22981694 | 123 | * @cmd: command |
1da177e4 | 124 | * |
5c05ff68 BZ |
125 | * Perform the DMA mapping magic necessary to access the source or |
126 | * target buffers of a request via DMA. The lower layers of the | |
1da177e4 | 127 | * kernel provide the necessary cache management so that we can |
5c05ff68 | 128 | * operate in a portable fashion. |
1da177e4 LT |
129 | */ |
130 | ||
5ae5412d | 131 | static int ide_build_sglist(ide_drive_t *drive, struct ide_cmd *cmd) |
1da177e4 | 132 | { |
db3f99ef | 133 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 134 | struct scatterlist *sg = hwif->sg_table; |
5d82720a | 135 | int i; |
1da177e4 | 136 | |
22981694 | 137 | ide_map_sg(drive, cmd); |
1da177e4 | 138 | |
22981694 | 139 | if (cmd->tf_flags & IDE_TFLAG_WRITE) |
b6308ee0 | 140 | cmd->sg_dma_direction = DMA_TO_DEVICE; |
22981694 BZ |
141 | else |
142 | cmd->sg_dma_direction = DMA_FROM_DEVICE; | |
1da177e4 | 143 | |
b6308ee0 | 144 | i = dma_map_sg(hwif->dev, sg, cmd->sg_nents, cmd->sg_dma_direction); |
e6830a86 | 145 | if (i == 0) |
22981694 | 146 | ide_map_sg(drive, cmd); |
e6830a86 | 147 | else { |
b6308ee0 BZ |
148 | cmd->orig_sg_nents = cmd->sg_nents; |
149 | cmd->sg_nents = i; | |
5d82720a FT |
150 | } |
151 | ||
152 | return i; | |
1da177e4 | 153 | } |
1da177e4 | 154 | |
1da177e4 LT |
155 | /** |
156 | * ide_destroy_dmatable - clean up DMA mapping | |
157 | * @drive: The drive to unmap | |
158 | * | |
159 | * Teardown mappings after DMA has completed. This must be called | |
160 | * after the completion of each use of ide_build_dmatable and before | |
161 | * the next use of ide_build_dmatable. Failure to do so will cause | |
162 | * an oops as only one mapping can be live for each target at a given | |
163 | * time. | |
164 | */ | |
db3f99ef BZ |
165 | |
166 | void ide_destroy_dmatable(ide_drive_t *drive) | |
1da177e4 | 167 | { |
36501650 | 168 | ide_hwif_t *hwif = drive->hwif; |
b6308ee0 | 169 | struct ide_cmd *cmd = &hwif->cmd; |
1da177e4 | 170 | |
b6308ee0 BZ |
171 | dma_unmap_sg(hwif->dev, hwif->sg_table, cmd->orig_sg_nents, |
172 | cmd->sg_dma_direction); | |
1da177e4 | 173 | } |
1da177e4 LT |
174 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); |
175 | ||
1da177e4 | 176 | /** |
7469aaf6 | 177 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
178 | * @drive: drive to control |
179 | * | |
db3f99ef | 180 | * Turn off the current DMA on this IDE controller. |
1da177e4 LT |
181 | */ |
182 | ||
7469aaf6 | 183 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 184 | { |
97100fc8 | 185 | drive->dev_flags &= ~IDE_DFLAG_USING_DMA; |
1da177e4 LT |
186 | ide_toggle_bounce(drive, 0); |
187 | ||
5e37bdc0 | 188 | drive->hwif->dma_ops->dma_host_set(drive, 0); |
1da177e4 | 189 | } |
7469aaf6 | 190 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
191 | |
192 | /** | |
7469aaf6 | 193 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
194 | * @drive: drive to disable DMA on |
195 | * | |
196 | * Disable IDE DMA for a device on this IDE controller. | |
197 | * Inform the user that DMA has been disabled. | |
198 | */ | |
199 | ||
7469aaf6 | 200 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
201 | { |
202 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 203 | ide_dma_off_quietly(drive); |
1da177e4 | 204 | } |
7469aaf6 | 205 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 206 | |
1da177e4 | 207 | /** |
4a546e04 | 208 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
209 | * @drive: drive to enable DMA on |
210 | * | |
211 | * Enable IDE DMA for a device on this IDE controller. | |
212 | */ | |
4a546e04 BZ |
213 | |
214 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 215 | { |
97100fc8 | 216 | drive->dev_flags |= IDE_DFLAG_USING_DMA; |
1da177e4 LT |
217 | ide_toggle_bounce(drive, 1); |
218 | ||
5e37bdc0 | 219 | drive->hwif->dma_ops->dma_host_set(drive, 1); |
1da177e4 LT |
220 | } |
221 | ||
db3f99ef | 222 | int __ide_dma_bad_drive(ide_drive_t *drive) |
1da177e4 | 223 | { |
4dde4492 | 224 | u16 *id = drive->id; |
1da177e4 | 225 | |
65e5f2e3 | 226 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
227 | if (blacklist) { |
228 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
4dde4492 | 229 | drive->name, (char *)&id[ATA_ID_PROD]); |
1da177e4 LT |
230 | return blacklist; |
231 | } | |
232 | return 0; | |
233 | } | |
1da177e4 LT |
234 | EXPORT_SYMBOL(__ide_dma_bad_drive); |
235 | ||
2d5eaa6d BZ |
236 | static const u8 xfer_mode_bases[] = { |
237 | XFER_UDMA_0, | |
238 | XFER_MW_DMA_0, | |
239 | XFER_SW_DMA_0, | |
240 | }; | |
241 | ||
7670df73 | 242 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d | 243 | { |
4dde4492 | 244 | u16 *id = drive->id; |
2d5eaa6d | 245 | ide_hwif_t *hwif = drive->hwif; |
ac95beed | 246 | const struct ide_port_ops *port_ops = hwif->port_ops; |
2d5eaa6d BZ |
247 | unsigned int mask = 0; |
248 | ||
db3f99ef | 249 | switch (base) { |
2d5eaa6d | 250 | case XFER_UDMA_0: |
4dde4492 | 251 | if ((id[ATA_ID_FIELD_VALID] & 4) == 0) |
2d5eaa6d BZ |
252 | break; |
253 | ||
ac95beed BZ |
254 | if (port_ops && port_ops->udma_filter) |
255 | mask = port_ops->udma_filter(drive); | |
851dd33b SS |
256 | else |
257 | mask = hwif->ultra_mask; | |
4dde4492 | 258 | mask &= id[ATA_ID_UDMA_MODES]; |
2d5eaa6d | 259 | |
7670df73 BZ |
260 | /* |
261 | * avoid false cable warning from eighty_ninty_three() | |
262 | */ | |
263 | if (req_mode > XFER_UDMA_2) { | |
264 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
265 | mask &= 0x07; | |
266 | } | |
2d5eaa6d BZ |
267 | break; |
268 | case XFER_MW_DMA_0: | |
4dde4492 | 269 | if ((id[ATA_ID_FIELD_VALID] & 2) == 0) |
b4e44369 | 270 | break; |
ac95beed BZ |
271 | if (port_ops && port_ops->mdma_filter) |
272 | mask = port_ops->mdma_filter(drive); | |
b4e44369 SS |
273 | else |
274 | mask = hwif->mwdma_mask; | |
4dde4492 | 275 | mask &= id[ATA_ID_MWDMA_MODES]; |
2d5eaa6d BZ |
276 | break; |
277 | case XFER_SW_DMA_0: | |
4dde4492 BZ |
278 | if (id[ATA_ID_FIELD_VALID] & 2) { |
279 | mask = id[ATA_ID_SWDMA_MODES] & hwif->swdma_mask; | |
48fb2688 BZ |
280 | } else if (id[ATA_ID_OLD_DMA_MODES] >> 8) { |
281 | u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8; | |
15a4f943 BZ |
282 | |
283 | /* | |
284 | * if the mode is valid convert it to the mask | |
285 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
286 | */ | |
287 | if (mode <= 2) | |
288 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
289 | } | |
2d5eaa6d BZ |
290 | break; |
291 | default: | |
292 | BUG(); | |
293 | break; | |
294 | } | |
295 | ||
296 | return mask; | |
297 | } | |
298 | ||
299 | /** | |
7670df73 | 300 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 301 | * @drive: IDE device |
7670df73 BZ |
302 | * @req_mode: requested mode |
303 | * | |
304 | * Checks the drive/host capabilities and finds the speed to use for | |
305 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 306 | * |
7670df73 BZ |
307 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
308 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
309 | */ |
310 | ||
7670df73 | 311 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
312 | { |
313 | ide_hwif_t *hwif = drive->hwif; | |
314 | unsigned int mask; | |
315 | int x, i; | |
316 | u8 mode = 0; | |
317 | ||
33c1002e BZ |
318 | if (drive->media != ide_disk) { |
319 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
320 | return 0; | |
321 | } | |
2d5eaa6d BZ |
322 | |
323 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
324 | if (req_mode < xfer_mode_bases[i]) |
325 | continue; | |
326 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
327 | x = fls(mask) - 1; |
328 | if (x >= 0) { | |
329 | mode = xfer_mode_bases[i] + x; | |
330 | break; | |
331 | } | |
332 | } | |
333 | ||
75d7d963 BZ |
334 | if (hwif->chipset == ide_acorn && mode == 0) { |
335 | /* | |
336 | * is this correct? | |
337 | */ | |
4dde4492 BZ |
338 | if (ide_dma_good_drive(drive) && |
339 | drive->id[ATA_ID_EIDE_DMA_TIME] < 150) | |
75d7d963 BZ |
340 | mode = XFER_MW_DMA_1; |
341 | } | |
342 | ||
3ab7efe8 BZ |
343 | mode = min(mode, req_mode); |
344 | ||
345 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 346 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 347 | |
3ab7efe8 | 348 | return mode; |
2d5eaa6d | 349 | } |
7670df73 | 350 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 351 | |
0ae2e178 | 352 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 353 | { |
8704de8f | 354 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
355 | u8 speed; |
356 | ||
97100fc8 BZ |
357 | if (ata_id_has_dma(drive->id) == 0 || |
358 | (drive->dev_flags & IDE_DFLAG_NODMA)) | |
122ab088 BZ |
359 | return 0; |
360 | ||
361 | /* consult the list of known "bad" drives */ | |
362 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
363 | return 0; |
364 | ||
3ab7efe8 BZ |
365 | if (ide_id_dma_bug(drive)) |
366 | return 0; | |
367 | ||
8704de8f | 368 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
369 | return config_drive_for_dma(drive); |
370 | ||
29e744d0 BZ |
371 | speed = ide_max_dma_mode(drive); |
372 | ||
951784b6 BZ |
373 | if (!speed) |
374 | return 0; | |
29e744d0 | 375 | |
88b2b32b | 376 | if (ide_set_dma_mode(drive, speed)) |
4728d546 | 377 | return 0; |
29e744d0 | 378 | |
4728d546 | 379 | return 1; |
29e744d0 BZ |
380 | } |
381 | ||
0ae2e178 BZ |
382 | static int ide_dma_check(ide_drive_t *drive) |
383 | { | |
384 | ide_hwif_t *hwif = drive->hwif; | |
0ae2e178 | 385 | |
ba4b2e60 | 386 | if (ide_tune_dma(drive)) |
0ae2e178 BZ |
387 | return 0; |
388 | ||
389 | /* TODO: always do PIO fallback */ | |
390 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
391 | return -1; | |
392 | ||
393 | ide_set_max_pio(drive); | |
394 | ||
ba4b2e60 | 395 | return -1; |
0ae2e178 BZ |
396 | } |
397 | ||
3ab7efe8 | 398 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 399 | { |
4dde4492 | 400 | u16 *id = drive->id; |
1da177e4 | 401 | |
4dde4492 BZ |
402 | if (id[ATA_ID_FIELD_VALID] & 4) { |
403 | if ((id[ATA_ID_UDMA_MODES] >> 8) && | |
404 | (id[ATA_ID_MWDMA_MODES] >> 8)) | |
3ab7efe8 | 405 | goto err_out; |
4dde4492 BZ |
406 | } else if (id[ATA_ID_FIELD_VALID] & 2) { |
407 | if ((id[ATA_ID_MWDMA_MODES] >> 8) && | |
408 | (id[ATA_ID_SWDMA_MODES] >> 8)) | |
3ab7efe8 | 409 | goto err_out; |
1da177e4 | 410 | } |
3ab7efe8 BZ |
411 | return 0; |
412 | err_out: | |
413 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
414 | return 1; | |
1da177e4 LT |
415 | } |
416 | ||
3608b5d7 BZ |
417 | int ide_set_dma(ide_drive_t *drive) |
418 | { | |
3608b5d7 BZ |
419 | int rc; |
420 | ||
7b905994 BZ |
421 | /* |
422 | * Force DMAing for the beginning of the check. | |
423 | * Some chipsets appear to do interesting | |
424 | * things, if not checked and cleared. | |
425 | * PARANOIA!!! | |
426 | */ | |
4a546e04 | 427 | ide_dma_off_quietly(drive); |
3608b5d7 | 428 | |
7b905994 BZ |
429 | rc = ide_dma_check(drive); |
430 | if (rc) | |
431 | return rc; | |
3608b5d7 | 432 | |
4a546e04 BZ |
433 | ide_dma_on(drive); |
434 | ||
435 | return 0; | |
3608b5d7 BZ |
436 | } |
437 | ||
578cfa0d BZ |
438 | void ide_check_dma_crc(ide_drive_t *drive) |
439 | { | |
440 | u8 mode; | |
441 | ||
442 | ide_dma_off_quietly(drive); | |
443 | drive->crc_count = 0; | |
444 | mode = drive->current_speed; | |
445 | /* | |
446 | * Don't try non Ultra-DMA modes without iCRC's. Force the | |
447 | * device to PIO and make the user enable SWDMA/MWDMA modes. | |
448 | */ | |
449 | if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) | |
450 | mode--; | |
451 | else | |
452 | mode = XFER_PIO_4; | |
453 | ide_set_xfer_rate(drive, mode); | |
454 | if (drive->current_speed >= XFER_SW_DMA_0) | |
455 | ide_dma_on(drive); | |
456 | } | |
457 | ||
de23ec9c | 458 | void ide_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 459 | { |
de23ec9c | 460 | printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name); |
1da177e4 | 461 | } |
de23ec9c | 462 | EXPORT_SYMBOL_GPL(ide_dma_lost_irq); |
1da177e4 | 463 | |
65ca5377 BZ |
464 | /* |
465 | * un-busy the port etc, and clear any pending DMA status. we want to | |
466 | * retry the current request in pio mode instead of risking tossing it | |
467 | * all away | |
468 | */ | |
469 | ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error) | |
470 | { | |
471 | ide_hwif_t *hwif = drive->hwif; | |
35c9b4da | 472 | const struct ide_dma_ops *dma_ops = hwif->dma_ops; |
65ca5377 BZ |
473 | struct request *rq; |
474 | ide_startstop_t ret = ide_stopped; | |
475 | ||
476 | /* | |
477 | * end current dma transaction | |
478 | */ | |
479 | ||
480 | if (error < 0) { | |
481 | printk(KERN_WARNING "%s: DMA timeout error\n", drive->name); | |
35c9b4da | 482 | (void)dma_ops->dma_end(drive); |
4453011f | 483 | ide_destroy_dmatable(drive); |
65ca5377 BZ |
484 | ret = ide_error(drive, "dma timeout error", |
485 | hwif->tp_ops->read_status(hwif)); | |
486 | } else { | |
487 | printk(KERN_WARNING "%s: DMA timeout retry\n", drive->name); | |
35c9b4da BZ |
488 | if (dma_ops->dma_clear) |
489 | dma_ops->dma_clear(drive); | |
1cee52de BZ |
490 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
491 | if (dma_ops->dma_test_irq(drive) == 0) { | |
492 | ide_dump_status(drive, "DMA timeout", | |
493 | hwif->tp_ops->read_status(hwif)); | |
494 | (void)dma_ops->dma_end(drive); | |
4453011f | 495 | ide_destroy_dmatable(drive); |
1cee52de | 496 | } |
65ca5377 BZ |
497 | } |
498 | ||
499 | /* | |
500 | * disable dma for now, but remember that we did so because of | |
501 | * a timeout -- we'll reenable after we finish this next request | |
502 | * (or rather the first chunk of it) in pio. | |
503 | */ | |
504 | drive->dev_flags |= IDE_DFLAG_DMA_PIO_RETRY; | |
505 | drive->retry_pio++; | |
506 | ide_dma_off_quietly(drive); | |
507 | ||
508 | /* | |
509 | * un-busy drive etc and make sure request is sane | |
510 | */ | |
511 | ||
512 | rq = hwif->rq; | |
513 | if (!rq) | |
514 | goto out; | |
515 | ||
516 | hwif->rq = NULL; | |
517 | ||
518 | rq->errors = 0; | |
519 | ||
520 | if (!rq->bio) | |
521 | goto out; | |
522 | ||
523 | rq->sector = rq->bio->bi_sector; | |
524 | rq->current_nr_sectors = bio_iovec(rq->bio)->bv_len >> 9; | |
525 | rq->hard_cur_sectors = rq->current_nr_sectors; | |
526 | rq->buffer = bio_data(rq->bio); | |
527 | out: | |
528 | return ret; | |
529 | } | |
530 | ||
0d1bad21 | 531 | void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
532 | { |
533 | if (hwif->dmatable_cpu) { | |
2bbd57ca | 534 | int prd_size = hwif->prd_max_nents * hwif->prd_ent_size; |
36501650 | 535 | |
2bbd57ca BZ |
536 | dma_free_coherent(hwif->dev, prd_size, |
537 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
1da177e4 LT |
538 | hwif->dmatable_cpu = NULL; |
539 | } | |
1da177e4 | 540 | } |
2bbd57ca | 541 | EXPORT_SYMBOL_GPL(ide_release_dma_engine); |
1da177e4 | 542 | |
b8e73fba | 543 | int ide_allocate_dma_engine(ide_hwif_t *hwif) |
1da177e4 | 544 | { |
2bbd57ca | 545 | int prd_size; |
36501650 | 546 | |
2bbd57ca BZ |
547 | if (hwif->prd_max_nents == 0) |
548 | hwif->prd_max_nents = PRD_ENTRIES; | |
549 | if (hwif->prd_ent_size == 0) | |
550 | hwif->prd_ent_size = PRD_BYTES; | |
1da177e4 | 551 | |
2bbd57ca | 552 | prd_size = hwif->prd_max_nents * hwif->prd_ent_size; |
1da177e4 | 553 | |
2bbd57ca BZ |
554 | hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev, prd_size, |
555 | &hwif->dmatable_dma, | |
556 | GFP_ATOMIC); | |
557 | if (hwif->dmatable_cpu == NULL) { | |
558 | printk(KERN_ERR "%s: unable to allocate PRD table\n", | |
5e59c236 | 559 | hwif->name); |
2bbd57ca BZ |
560 | return -ENOMEM; |
561 | } | |
1da177e4 | 562 | |
2bbd57ca | 563 | return 0; |
1da177e4 | 564 | } |
b8e73fba | 565 | EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); |
5ae5412d BZ |
566 | |
567 | int ide_dma_prepare(ide_drive_t *drive, struct ide_cmd *cmd) | |
568 | { | |
569 | if ((drive->dev_flags & IDE_DFLAG_USING_DMA) == 0 || | |
570 | ide_build_sglist(drive, cmd) == 0 || | |
571 | drive->hwif->dma_ops->dma_setup(drive, cmd)) | |
572 | return 1; | |
573 | return 0; | |
574 | } |