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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 | |
3 | * | |
4 | * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Special Thanks to Mark for his Six years of work. | |
10 | * | |
11 | * Copyright (c) 1995-1998 Mark Lord | |
12 | * May be copied or modified under the terms of the GNU General Public License | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This module provides support for the bus-master IDE DMA functions | |
17 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
18 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
19 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
20 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
21 | * | |
22 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
23 | * | |
24 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
25 | * | |
26 | * By default, DMA support is prepared for use, but is currently enabled only | |
27 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
28 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
29 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
30 | * (eg. MC2112A) but are not enabled by default. | |
31 | * | |
32 | * Use "hdparm -i" to view modes supported by a given drive. | |
33 | * | |
34 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
35 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
36 | * | |
37 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
38 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
39 | * This error recovery mechanism works and has been extremely well exercised. | |
40 | * | |
41 | * IDE drives, depending on their vintage, may support several different modes | |
42 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
43 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
44 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
45 | * normally power-up with their "best" PIO/DMA modes enabled. | |
46 | * | |
47 | * Testing has been done with a rather extensive number of drives, | |
48 | * with Quantum & Western Digital models generally outperforming the pack, | |
49 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
50 | * showing more lackluster throughput. | |
51 | * | |
52 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
53 | * | |
54 | * Some people have reported trouble with Intel Zappa motherboards. | |
55 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
56 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
57 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
58 | * | |
59 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
60 | * fixing the problem with the BIOS on some Acer motherboards. | |
61 | * | |
62 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
63 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
64 | * | |
65 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
66 | * at generic DMA -- his patches were referred to when preparing this code. | |
67 | * | |
68 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
69 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
70 | * | |
71 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
72 | * | |
73 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
74 | * | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/kernel.h> | |
80 | #include <linux/timer.h> | |
81 | #include <linux/mm.h> | |
82 | #include <linux/interrupt.h> | |
83 | #include <linux/pci.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/ide.h> | |
86 | #include <linux/delay.h> | |
87 | #include <linux/scatterlist.h> | |
88 | ||
89 | #include <asm/io.h> | |
90 | #include <asm/irq.h> | |
91 | ||
1da177e4 LT |
92 | static const struct drive_list_entry drive_whitelist [] = { |
93 | ||
94 | { "Micropolis 2112A" , "ALL" }, | |
95 | { "CONNER CTMA 4000" , "ALL" }, | |
96 | { "CONNER CTT8000-A" , "ALL" }, | |
97 | { "ST34342A" , "ALL" }, | |
98 | { NULL , NULL } | |
99 | }; | |
100 | ||
101 | static const struct drive_list_entry drive_blacklist [] = { | |
102 | ||
103 | { "WDC AC11000H" , "ALL" }, | |
104 | { "WDC AC22100H" , "ALL" }, | |
105 | { "WDC AC32500H" , "ALL" }, | |
106 | { "WDC AC33100H" , "ALL" }, | |
107 | { "WDC AC31600H" , "ALL" }, | |
108 | { "WDC AC32100H" , "24.09P07" }, | |
109 | { "WDC AC23200L" , "21.10N21" }, | |
110 | { "Compaq CRD-8241B" , "ALL" }, | |
111 | { "CRD-8400B" , "ALL" }, | |
112 | { "CRD-8480B", "ALL" }, | |
113 | { "CRD-8482B", "ALL" }, | |
114 | { "CRD-84" , "ALL" }, | |
115 | { "SanDisk SDP3B" , "ALL" }, | |
116 | { "SanDisk SDP3B-64" , "ALL" }, | |
117 | { "SANYO CD-ROM CRD" , "ALL" }, | |
118 | { "HITACHI CDR-8" , "ALL" }, | |
119 | { "HITACHI CDR-8335" , "ALL" }, | |
120 | { "HITACHI CDR-8435" , "ALL" }, | |
121 | { "Toshiba CD-ROM XM-6202B" , "ALL" }, | |
5a6248ca | 122 | { "TOSHIBA CD-ROM XM-1702BC", "ALL" }, |
1da177e4 LT |
123 | { "CD-532E-A" , "ALL" }, |
124 | { "E-IDE CD-ROM CR-840", "ALL" }, | |
125 | { "CD-ROM Drive/F5A", "ALL" }, | |
126 | { "WPI CDD-820", "ALL" }, | |
127 | { "SAMSUNG CD-ROM SC-148C", "ALL" }, | |
128 | { "SAMSUNG CD-ROM SC", "ALL" }, | |
1da177e4 LT |
129 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" }, |
130 | { "_NEC DV5800A", "ALL" }, | |
5a6248ca JH |
131 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
132 | { "Seagate STT20000A", "ALL" }, | |
1da177e4 LT |
133 | { NULL , NULL } |
134 | ||
135 | }; | |
136 | ||
137 | /** | |
65e5f2e3 | 138 | * ide_in_drive_list - look for drive in black/white list |
1da177e4 LT |
139 | * @id: drive identifier |
140 | * @drive_table: list to inspect | |
141 | * | |
142 | * Look for a drive in the blacklist and the whitelist tables | |
143 | * Returns 1 if the drive is found in the table. | |
144 | */ | |
145 | ||
65e5f2e3 | 146 | int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table) |
1da177e4 LT |
147 | { |
148 | for ( ; drive_table->id_model ; drive_table++) | |
149 | if ((!strcmp(drive_table->id_model, id->model)) && | |
14e0a193 | 150 | ((strstr(id->fw_rev, drive_table->id_firmware)) || |
1da177e4 LT |
151 | (!strcmp(drive_table->id_firmware, "ALL")))) |
152 | return 1; | |
153 | return 0; | |
154 | } | |
155 | ||
156 | /** | |
157 | * ide_dma_intr - IDE DMA interrupt handler | |
158 | * @drive: the drive the interrupt is for | |
159 | * | |
160 | * Handle an interrupt completing a read/write DMA transfer on an | |
161 | * IDE device | |
162 | */ | |
163 | ||
164 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
165 | { | |
166 | u8 stat = 0, dma_stat = 0; | |
167 | ||
168 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
169 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
170 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
171 | if (!dma_stat) { | |
172 | struct request *rq = HWGROUP(drive)->rq; | |
173 | ||
174 | if (rq->rq_disk) { | |
175 | ide_driver_t *drv; | |
176 | ||
53b3531b | 177 | drv = *(ide_driver_t **)rq->rq_disk->private_data; |
1da177e4 LT |
178 | drv->end_request(drive, 1, rq->nr_sectors); |
179 | } else | |
180 | ide_end_request(drive, 1, rq->nr_sectors); | |
181 | return ide_stopped; | |
182 | } | |
183 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
184 | drive->name, dma_stat); | |
185 | } | |
186 | return ide_error(drive, "dma_intr", stat); | |
187 | } | |
188 | ||
189 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
190 | ||
191 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
192 | /** | |
193 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
194 | * @drive: the drive to build the DMA table for | |
195 | * @rq: the request holding the sg list | |
196 | * | |
197 | * Perform the PCI mapping magic necessary to access the source or | |
198 | * target buffers of a request via PCI DMA. The lower layers of the | |
199 | * kernel provide the necessary cache management so that we can | |
200 | * operate in a portable fashion | |
201 | */ | |
202 | ||
203 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
204 | { | |
205 | ide_hwif_t *hwif = HWIF(drive); | |
206 | struct scatterlist *sg = hwif->sg_table; | |
207 | ||
4aff5e23 | 208 | BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256); |
1da177e4 LT |
209 | |
210 | ide_map_sg(drive, rq); | |
211 | ||
212 | if (rq_data_dir(rq) == READ) | |
213 | hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; | |
214 | else | |
215 | hwif->sg_dma_direction = PCI_DMA_TODEVICE; | |
216 | ||
217 | return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); | |
218 | } | |
219 | ||
220 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
221 | ||
222 | /** | |
223 | * ide_build_dmatable - build IDE DMA table | |
224 | * | |
225 | * ide_build_dmatable() prepares a dma request. We map the command | |
226 | * to get the pci bus addresses of the buffers and then build up | |
227 | * the PRD table that the IDE layer wants to be fed. The code | |
228 | * knows about the 64K wrap bug in the CS5530. | |
229 | * | |
230 | * Returns the number of built PRD entries if all went okay, | |
231 | * returns 0 otherwise. | |
232 | * | |
233 | * May also be invoked from trm290.c | |
234 | */ | |
235 | ||
236 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
237 | { | |
238 | ide_hwif_t *hwif = HWIF(drive); | |
239 | unsigned int *table = hwif->dmatable_cpu; | |
240 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
241 | unsigned int count = 0; | |
242 | int i; | |
243 | struct scatterlist *sg; | |
244 | ||
245 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
246 | ||
247 | if (!i) | |
248 | return 0; | |
249 | ||
250 | sg = hwif->sg_table; | |
251 | while (i) { | |
252 | u32 cur_addr; | |
253 | u32 cur_len; | |
254 | ||
255 | cur_addr = sg_dma_address(sg); | |
256 | cur_len = sg_dma_len(sg); | |
257 | ||
258 | /* | |
259 | * Fill in the dma table, without crossing any 64kB boundaries. | |
260 | * Most hardware requires 16-bit alignment of all blocks, | |
261 | * but the trm290 requires 32-bit alignment. | |
262 | */ | |
263 | ||
264 | while (cur_len) { | |
265 | if (count++ >= PRD_ENTRIES) { | |
266 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
267 | goto use_pio_instead; | |
268 | } else { | |
269 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
270 | ||
271 | if (bcount > cur_len) | |
272 | bcount = cur_len; | |
273 | *table++ = cpu_to_le32(cur_addr); | |
274 | xcount = bcount & 0xffff; | |
275 | if (is_trm290) | |
276 | xcount = ((xcount >> 2) - 1) << 16; | |
277 | if (xcount == 0x0000) { | |
278 | /* | |
279 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
280 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
281 | * So here we break the 64KB entry into two 32KB entries instead. | |
282 | */ | |
283 | if (count++ >= PRD_ENTRIES) { | |
284 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
285 | goto use_pio_instead; | |
286 | } | |
287 | *table++ = cpu_to_le32(0x8000); | |
288 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
289 | xcount = 0x8000; | |
290 | } | |
291 | *table++ = cpu_to_le32(xcount); | |
292 | cur_addr += bcount; | |
293 | cur_len -= bcount; | |
294 | } | |
295 | } | |
296 | ||
297 | sg++; | |
298 | i--; | |
299 | } | |
300 | ||
301 | if (count) { | |
302 | if (!is_trm290) | |
303 | *--table |= cpu_to_le32(0x80000000); | |
304 | return count; | |
305 | } | |
306 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); | |
307 | use_pio_instead: | |
308 | pci_unmap_sg(hwif->pci_dev, | |
309 | hwif->sg_table, | |
310 | hwif->sg_nents, | |
311 | hwif->sg_dma_direction); | |
312 | return 0; /* revert to PIO for this request */ | |
313 | } | |
314 | ||
315 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
316 | ||
317 | /** | |
318 | * ide_destroy_dmatable - clean up DMA mapping | |
319 | * @drive: The drive to unmap | |
320 | * | |
321 | * Teardown mappings after DMA has completed. This must be called | |
322 | * after the completion of each use of ide_build_dmatable and before | |
323 | * the next use of ide_build_dmatable. Failure to do so will cause | |
324 | * an oops as only one mapping can be live for each target at a given | |
325 | * time. | |
326 | */ | |
327 | ||
328 | void ide_destroy_dmatable (ide_drive_t *drive) | |
329 | { | |
330 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
331 | struct scatterlist *sg = HWIF(drive)->sg_table; | |
332 | int nents = HWIF(drive)->sg_nents; | |
333 | ||
334 | pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); | |
335 | } | |
336 | ||
337 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
338 | ||
339 | /** | |
340 | * config_drive_for_dma - attempt to activate IDE DMA | |
341 | * @drive: the drive to place in DMA mode | |
342 | * | |
343 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
344 | * then attempt to place it into DMA mode. Drives that are known to | |
345 | * support DMA but predate the DMA properties or that are known | |
346 | * to have DMA handling bugs are also set up appropriately based | |
347 | * on the good/bad drive lists. | |
348 | */ | |
349 | ||
350 | static int config_drive_for_dma (ide_drive_t *drive) | |
351 | { | |
352 | struct hd_driveid *id = drive->id; | |
1da177e4 | 353 | |
3608b5d7 | 354 | if ((id->capability & 1) && drive->hwif->autodma) { |
1da177e4 LT |
355 | /* |
356 | * Enable DMA on any drive that has | |
357 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
358 | */ | |
359 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
3608b5d7 | 360 | return 0; |
1da177e4 LT |
361 | /* |
362 | * Enable DMA on any drive that has mode2 DMA | |
363 | * (multi or single) enabled | |
364 | */ | |
365 | if (id->field_valid & 2) /* regular DMA */ | |
366 | if ((id->dma_mword & 0x404) == 0x404 || | |
367 | (id->dma_1word & 0x404) == 0x404) | |
3608b5d7 | 368 | return 0; |
1da177e4 LT |
369 | |
370 | /* Consult the list of known "good" drives */ | |
371 | if (__ide_dma_good_drive(drive)) | |
3608b5d7 | 372 | return 0; |
1da177e4 | 373 | } |
3608b5d7 BZ |
374 | |
375 | return -1; | |
1da177e4 LT |
376 | } |
377 | ||
378 | /** | |
379 | * dma_timer_expiry - handle a DMA timeout | |
380 | * @drive: Drive that timed out | |
381 | * | |
382 | * An IDE DMA transfer timed out. In the event of an error we ask | |
383 | * the driver to resolve the problem, if a DMA transfer is still | |
384 | * in progress we continue to wait (arguably we need to add a | |
385 | * secondary 'I don't care what the drive thinks' timeout here) | |
386 | * Finally if we have an interrupt we let it complete the I/O. | |
387 | * But only one time - we clear expiry and if it's still not | |
388 | * completed after WAIT_CMD, we error and retry in PIO. | |
389 | * This can occur if an interrupt is lost or due to hang or bugs. | |
390 | */ | |
391 | ||
392 | static int dma_timer_expiry (ide_drive_t *drive) | |
393 | { | |
394 | ide_hwif_t *hwif = HWIF(drive); | |
395 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
396 | ||
397 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
398 | drive->name, dma_stat); | |
399 | ||
400 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
401 | return WAIT_CMD; | |
402 | ||
403 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
404 | ||
405 | /* 1 dmaing, 2 error, 4 intr */ | |
406 | if (dma_stat & 2) /* ERROR */ | |
407 | return -1; | |
408 | ||
409 | if (dma_stat & 1) /* DMAing */ | |
410 | return WAIT_CMD; | |
411 | ||
412 | if (dma_stat & 4) /* Got an Interrupt */ | |
413 | return WAIT_CMD; | |
414 | ||
415 | return 0; /* Status is unknown -- reset the bus */ | |
416 | } | |
417 | ||
418 | /** | |
7469aaf6 | 419 | * ide_dma_host_off - Generic DMA kill |
1da177e4 LT |
420 | * @drive: drive to control |
421 | * | |
422 | * Perform the generic IDE controller DMA off operation. This | |
423 | * works for most IDE bus mastering controllers | |
424 | */ | |
425 | ||
7469aaf6 | 426 | void ide_dma_host_off(ide_drive_t *drive) |
1da177e4 LT |
427 | { |
428 | ide_hwif_t *hwif = HWIF(drive); | |
429 | u8 unit = (drive->select.b.unit & 0x01); | |
430 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
431 | ||
432 | hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status); | |
1da177e4 LT |
433 | } |
434 | ||
7469aaf6 | 435 | EXPORT_SYMBOL(ide_dma_host_off); |
1da177e4 LT |
436 | |
437 | /** | |
7469aaf6 | 438 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
439 | * @drive: drive to control |
440 | * | |
441 | * Turn off the current DMA on this IDE controller. | |
442 | */ | |
443 | ||
7469aaf6 | 444 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
445 | { |
446 | drive->using_dma = 0; | |
447 | ide_toggle_bounce(drive, 0); | |
448 | ||
7469aaf6 | 449 | drive->hwif->dma_host_off(drive); |
1da177e4 LT |
450 | } |
451 | ||
7469aaf6 | 452 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
453 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
454 | ||
455 | /** | |
7469aaf6 | 456 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
457 | * @drive: drive to disable DMA on |
458 | * | |
459 | * Disable IDE DMA for a device on this IDE controller. | |
460 | * Inform the user that DMA has been disabled. | |
461 | */ | |
462 | ||
7469aaf6 | 463 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
464 | { |
465 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
7469aaf6 | 466 | drive->hwif->dma_off_quietly(drive); |
1da177e4 LT |
467 | } |
468 | ||
7469aaf6 | 469 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 LT |
470 | |
471 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
472 | /** | |
ccf35289 | 473 | * ide_dma_host_on - Enable DMA on a host |
1da177e4 LT |
474 | * @drive: drive to enable for DMA |
475 | * | |
476 | * Enable DMA on an IDE controller following generic bus mastering | |
477 | * IDE controller behaviour | |
478 | */ | |
ccf35289 BZ |
479 | |
480 | void ide_dma_host_on(ide_drive_t *drive) | |
1da177e4 LT |
481 | { |
482 | if (drive->using_dma) { | |
483 | ide_hwif_t *hwif = HWIF(drive); | |
484 | u8 unit = (drive->select.b.unit & 0x01); | |
485 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
486 | ||
487 | hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status); | |
1da177e4 | 488 | } |
1da177e4 LT |
489 | } |
490 | ||
ccf35289 | 491 | EXPORT_SYMBOL(ide_dma_host_on); |
1da177e4 LT |
492 | |
493 | /** | |
494 | * __ide_dma_on - Enable DMA on a device | |
495 | * @drive: drive to enable DMA on | |
496 | * | |
497 | * Enable IDE DMA for a device on this IDE controller. | |
498 | */ | |
499 | ||
500 | int __ide_dma_on (ide_drive_t *drive) | |
501 | { | |
502 | /* consult the list of known "bad" drives */ | |
503 | if (__ide_dma_bad_drive(drive)) | |
504 | return 1; | |
505 | ||
506 | drive->using_dma = 1; | |
507 | ide_toggle_bounce(drive, 1); | |
508 | ||
ccf35289 | 509 | drive->hwif->dma_host_on(drive); |
1da177e4 LT |
510 | |
511 | return 0; | |
512 | } | |
513 | ||
514 | EXPORT_SYMBOL(__ide_dma_on); | |
515 | ||
516 | /** | |
517 | * __ide_dma_check - check DMA setup | |
518 | * @drive: drive to check | |
519 | * | |
520 | * Don't use - due for extermination | |
521 | */ | |
522 | ||
523 | int __ide_dma_check (ide_drive_t *drive) | |
524 | { | |
525 | return config_drive_for_dma(drive); | |
526 | } | |
527 | ||
528 | EXPORT_SYMBOL(__ide_dma_check); | |
529 | ||
530 | /** | |
531 | * ide_dma_setup - begin a DMA phase | |
532 | * @drive: target device | |
533 | * | |
534 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
535 | * and then set up the DMA transfer registers for a device | |
536 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
537 | * override this function if they need to | |
538 | * | |
539 | * Returns 0 on success. If a PIO fallback is required then 1 | |
540 | * is returned. | |
541 | */ | |
542 | ||
543 | int ide_dma_setup(ide_drive_t *drive) | |
544 | { | |
545 | ide_hwif_t *hwif = drive->hwif; | |
546 | struct request *rq = HWGROUP(drive)->rq; | |
547 | unsigned int reading; | |
548 | u8 dma_stat; | |
549 | ||
550 | if (rq_data_dir(rq)) | |
551 | reading = 0; | |
552 | else | |
553 | reading = 1 << 3; | |
554 | ||
555 | /* fall back to pio! */ | |
556 | if (!ide_build_dmatable(drive, rq)) { | |
557 | ide_map_sg(drive, rq); | |
558 | return 1; | |
559 | } | |
560 | ||
561 | /* PRD table */ | |
2ad1e558 | 562 | if (hwif->mmio) |
0ecdca26 BZ |
563 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
564 | else | |
565 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
566 | |
567 | /* specify r/w */ | |
568 | hwif->OUTB(reading, hwif->dma_command); | |
569 | ||
570 | /* read dma_status for INTR & ERROR flags */ | |
571 | dma_stat = hwif->INB(hwif->dma_status); | |
572 | ||
573 | /* clear INTR & ERROR flags */ | |
574 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
575 | drive->waiting_for_dma = 1; | |
576 | return 0; | |
577 | } | |
578 | ||
579 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
580 | ||
581 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
582 | { | |
583 | /* issue cmd to drive */ | |
584 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
585 | } | |
586 | ||
587 | void ide_dma_start(ide_drive_t *drive) | |
588 | { | |
589 | ide_hwif_t *hwif = HWIF(drive); | |
590 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
591 | ||
592 | /* Note that this is done *after* the cmd has | |
593 | * been issued to the drive, as per the BM-IDE spec. | |
594 | * The Promise Ultra33 doesn't work correctly when | |
595 | * we do this part before issuing the drive cmd. | |
596 | */ | |
597 | /* start DMA */ | |
598 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
599 | hwif->dma = 1; | |
600 | wmb(); | |
601 | } | |
602 | ||
603 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
604 | ||
605 | /* returns 1 on error, 0 otherwise */ | |
606 | int __ide_dma_end (ide_drive_t *drive) | |
607 | { | |
608 | ide_hwif_t *hwif = HWIF(drive); | |
609 | u8 dma_stat = 0, dma_cmd = 0; | |
610 | ||
611 | drive->waiting_for_dma = 0; | |
612 | /* get dma_command mode */ | |
613 | dma_cmd = hwif->INB(hwif->dma_command); | |
614 | /* stop DMA */ | |
615 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
616 | /* get DMA status */ | |
617 | dma_stat = hwif->INB(hwif->dma_status); | |
618 | /* clear the INTR & ERROR bits */ | |
619 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
620 | /* purge DMA mappings */ | |
621 | ide_destroy_dmatable(drive); | |
622 | /* verify good DMA status */ | |
623 | hwif->dma = 0; | |
624 | wmb(); | |
625 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
626 | } | |
627 | ||
628 | EXPORT_SYMBOL(__ide_dma_end); | |
629 | ||
630 | /* returns 1 if dma irq issued, 0 otherwise */ | |
631 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
632 | { | |
633 | ide_hwif_t *hwif = HWIF(drive); | |
634 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
635 | ||
636 | #if 0 /* do not set unless you know what you are doing */ | |
637 | if (dma_stat & 4) { | |
638 | u8 stat = hwif->INB(IDE_STATUS_REG); | |
639 | hwif->OUTB(hwif->dma_status, dma_stat & 0xE4); | |
640 | } | |
641 | #endif | |
642 | /* return 1 if INTR asserted */ | |
643 | if ((dma_stat & 4) == 4) | |
644 | return 1; | |
645 | if (!drive->waiting_for_dma) | |
646 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
647 | drive->name, __FUNCTION__); | |
648 | return 0; | |
649 | } | |
650 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
651 | ||
652 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
653 | { | |
654 | struct hd_driveid *id = drive->id; | |
655 | ||
65e5f2e3 | 656 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
657 | if (blacklist) { |
658 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
659 | drive->name, id->model); | |
660 | return blacklist; | |
661 | } | |
662 | return 0; | |
663 | } | |
664 | ||
665 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
666 | ||
667 | int __ide_dma_good_drive (ide_drive_t *drive) | |
668 | { | |
669 | struct hd_driveid *id = drive->id; | |
65e5f2e3 | 670 | return ide_in_drive_list(id, drive_whitelist); |
1da177e4 LT |
671 | } |
672 | ||
673 | EXPORT_SYMBOL(__ide_dma_good_drive); | |
674 | ||
2d5eaa6d BZ |
675 | static const u8 xfer_mode_bases[] = { |
676 | XFER_UDMA_0, | |
677 | XFER_MW_DMA_0, | |
678 | XFER_SW_DMA_0, | |
679 | }; | |
680 | ||
681 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base) | |
682 | { | |
683 | struct hd_driveid *id = drive->id; | |
684 | ide_hwif_t *hwif = drive->hwif; | |
685 | unsigned int mask = 0; | |
686 | ||
687 | switch(base) { | |
688 | case XFER_UDMA_0: | |
689 | if ((id->field_valid & 4) == 0) | |
690 | break; | |
691 | ||
692 | mask = id->dma_ultra & hwif->ultra_mask; | |
693 | ||
694 | if (hwif->udma_filter) | |
695 | mask &= hwif->udma_filter(drive); | |
696 | ||
697 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
698 | mask &= 0x07; | |
699 | break; | |
700 | case XFER_MW_DMA_0: | |
3649c06e BZ |
701 | if (id->field_valid & 2) |
702 | mask = id->dma_mword & hwif->mwdma_mask; | |
2d5eaa6d BZ |
703 | break; |
704 | case XFER_SW_DMA_0: | |
3649c06e BZ |
705 | if (id->field_valid & 2) |
706 | mask = id->dma_1word & hwif->swdma_mask; | |
2d5eaa6d BZ |
707 | break; |
708 | default: | |
709 | BUG(); | |
710 | break; | |
711 | } | |
712 | ||
713 | return mask; | |
714 | } | |
715 | ||
716 | /** | |
717 | * ide_max_dma_mode - compute DMA speed | |
718 | * @drive: IDE device | |
719 | * | |
720 | * Checks the drive capabilities and returns the speed to use | |
721 | * for the DMA transfer. Returns 0 if the drive is incapable | |
722 | * of DMA transfers. | |
723 | */ | |
724 | ||
725 | u8 ide_max_dma_mode(ide_drive_t *drive) | |
726 | { | |
727 | ide_hwif_t *hwif = drive->hwif; | |
728 | unsigned int mask; | |
729 | int x, i; | |
730 | u8 mode = 0; | |
731 | ||
732 | if (drive->media != ide_disk && hwif->atapi_dma == 0) | |
733 | return 0; | |
734 | ||
735 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
736 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i]); | |
737 | x = fls(mask) - 1; | |
738 | if (x >= 0) { | |
739 | mode = xfer_mode_bases[i] + x; | |
740 | break; | |
741 | } | |
742 | } | |
743 | ||
744 | printk(KERN_DEBUG "%s: selected mode 0x%x\n", drive->name, mode); | |
745 | ||
746 | return mode; | |
747 | } | |
748 | ||
749 | EXPORT_SYMBOL_GPL(ide_max_dma_mode); | |
750 | ||
29e744d0 BZ |
751 | int ide_tune_dma(ide_drive_t *drive) |
752 | { | |
753 | u8 speed; | |
754 | ||
122ab088 BZ |
755 | if ((drive->id->capability & 1) == 0 || drive->autodma == 0) |
756 | return 0; | |
757 | ||
758 | /* consult the list of known "bad" drives */ | |
759 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
760 | return 0; |
761 | ||
762 | speed = ide_max_dma_mode(drive); | |
763 | ||
764 | if (!speed) | |
765 | return 0; | |
766 | ||
4728d546 BZ |
767 | if (drive->hwif->speedproc(drive, speed)) |
768 | return 0; | |
29e744d0 | 769 | |
4728d546 | 770 | return 1; |
29e744d0 BZ |
771 | } |
772 | ||
773 | EXPORT_SYMBOL_GPL(ide_tune_dma); | |
774 | ||
1da177e4 LT |
775 | void ide_dma_verbose(ide_drive_t *drive) |
776 | { | |
777 | struct hd_driveid *id = drive->id; | |
778 | ide_hwif_t *hwif = HWIF(drive); | |
779 | ||
780 | if (id->field_valid & 4) { | |
781 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
782 | goto bug_dma_off; | |
783 | if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) { | |
784 | if (((id->dma_ultra >> 11) & 0x1F) && | |
785 | eighty_ninty_three(drive)) { | |
786 | if ((id->dma_ultra >> 15) & 1) { | |
787 | printk(", UDMA(mode 7)"); | |
788 | } else if ((id->dma_ultra >> 14) & 1) { | |
789 | printk(", UDMA(133)"); | |
790 | } else if ((id->dma_ultra >> 13) & 1) { | |
791 | printk(", UDMA(100)"); | |
792 | } else if ((id->dma_ultra >> 12) & 1) { | |
793 | printk(", UDMA(66)"); | |
794 | } else if ((id->dma_ultra >> 11) & 1) { | |
795 | printk(", UDMA(44)"); | |
796 | } else | |
797 | goto mode_two; | |
798 | } else { | |
799 | mode_two: | |
800 | if ((id->dma_ultra >> 10) & 1) { | |
801 | printk(", UDMA(33)"); | |
802 | } else if ((id->dma_ultra >> 9) & 1) { | |
803 | printk(", UDMA(25)"); | |
804 | } else if ((id->dma_ultra >> 8) & 1) { | |
805 | printk(", UDMA(16)"); | |
806 | } | |
807 | } | |
808 | } else { | |
809 | printk(", (U)DMA"); /* Can be BIOS-enabled! */ | |
810 | } | |
811 | } else if (id->field_valid & 2) { | |
812 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
813 | goto bug_dma_off; | |
814 | printk(", DMA"); | |
815 | } else if (id->field_valid & 1) { | |
0a8348d0 | 816 | goto bug_dma_off; |
1da177e4 LT |
817 | } |
818 | return; | |
819 | bug_dma_off: | |
820 | printk(", BUG DMA OFF"); | |
7469aaf6 | 821 | hwif->dma_off_quietly(drive); |
1da177e4 LT |
822 | return; |
823 | } | |
824 | ||
825 | EXPORT_SYMBOL(ide_dma_verbose); | |
826 | ||
3608b5d7 BZ |
827 | int ide_set_dma(ide_drive_t *drive) |
828 | { | |
829 | ide_hwif_t *hwif = drive->hwif; | |
830 | int rc; | |
831 | ||
832 | rc = hwif->ide_dma_check(drive); | |
833 | ||
834 | switch(rc) { | |
835 | case -1: /* DMA needs to be disabled */ | |
7469aaf6 | 836 | hwif->dma_off_quietly(drive); |
6f5050a9 | 837 | return -1; |
3608b5d7 BZ |
838 | case 0: /* DMA needs to be enabled */ |
839 | return hwif->ide_dma_on(drive); | |
840 | case 1: /* DMA setting cannot be changed */ | |
841 | break; | |
842 | default: | |
843 | BUG(); | |
844 | break; | |
845 | } | |
846 | ||
847 | return rc; | |
848 | } | |
849 | ||
850 | EXPORT_SYMBOL_GPL(ide_set_dma); | |
851 | ||
1da177e4 LT |
852 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
853 | int __ide_dma_lostirq (ide_drive_t *drive) | |
854 | { | |
855 | printk("%s: DMA interrupt recovery\n", drive->name); | |
856 | return 1; | |
857 | } | |
858 | ||
859 | EXPORT_SYMBOL(__ide_dma_lostirq); | |
860 | ||
861 | int __ide_dma_timeout (ide_drive_t *drive) | |
862 | { | |
863 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); | |
864 | if (HWIF(drive)->ide_dma_test_irq(drive)) | |
865 | return 0; | |
866 | ||
867 | return HWIF(drive)->ide_dma_end(drive); | |
868 | } | |
869 | ||
870 | EXPORT_SYMBOL(__ide_dma_timeout); | |
871 | ||
872 | /* | |
873 | * Needed for allowing full modular support of ide-driver | |
874 | */ | |
875 | static int ide_release_dma_engine(ide_hwif_t *hwif) | |
876 | { | |
877 | if (hwif->dmatable_cpu) { | |
878 | pci_free_consistent(hwif->pci_dev, | |
879 | PRD_ENTRIES * PRD_BYTES, | |
880 | hwif->dmatable_cpu, | |
881 | hwif->dmatable_dma); | |
882 | hwif->dmatable_cpu = NULL; | |
883 | } | |
884 | return 1; | |
885 | } | |
886 | ||
887 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
888 | { | |
1da177e4 | 889 | release_region(hwif->dma_base, 8); |
020e322d SS |
890 | if (hwif->extra_ports) |
891 | release_region(hwif->extra_base, hwif->extra_ports); | |
1da177e4 LT |
892 | return 1; |
893 | } | |
894 | ||
895 | /* | |
896 | * Needed for allowing full modular support of ide-driver | |
897 | */ | |
dc844e05 | 898 | int ide_release_dma(ide_hwif_t *hwif) |
1da177e4 | 899 | { |
dc844e05 SS |
900 | ide_release_dma_engine(hwif); |
901 | ||
2ad1e558 | 902 | if (hwif->mmio) |
1da177e4 | 903 | return 1; |
dc844e05 SS |
904 | else |
905 | return ide_release_iomio_dma(hwif); | |
1da177e4 LT |
906 | } |
907 | ||
908 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
909 | { | |
910 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, | |
911 | PRD_ENTRIES * PRD_BYTES, | |
912 | &hwif->dmatable_dma); | |
913 | ||
914 | if (hwif->dmatable_cpu) | |
915 | return 0; | |
916 | ||
dc844e05 SS |
917 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
918 | hwif->cds->name); | |
1da177e4 | 919 | |
1da177e4 LT |
920 | return 1; |
921 | } | |
922 | ||
923 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
924 | { | |
925 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
926 | ||
020e322d | 927 | hwif->dma_base = base; |
1da177e4 LT |
928 | |
929 | if(hwif->mate) | |
930 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; | |
931 | else | |
932 | hwif->dma_master = base; | |
933 | return 0; | |
934 | } | |
935 | ||
936 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
937 | { | |
938 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
020e322d SS |
939 | hwif->name, base, base + ports - 1); |
940 | ||
1da177e4 LT |
941 | if (!request_region(base, ports, hwif->name)) { |
942 | printk(" -- Error, ports in use.\n"); | |
943 | return 1; | |
944 | } | |
020e322d | 945 | |
1da177e4 | 946 | hwif->dma_base = base; |
020e322d SS |
947 | |
948 | if (hwif->cds->extra) { | |
949 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
950 | ||
951 | if (!hwif->mate || !hwif->mate->extra_ports) { | |
952 | if (!request_region(hwif->extra_base, | |
953 | hwif->cds->extra, hwif->cds->name)) { | |
954 | printk(" -- Error, extra ports in use.\n"); | |
955 | release_region(base, ports); | |
956 | return 1; | |
957 | } | |
958 | hwif->extra_ports = hwif->cds->extra; | |
959 | } | |
1da177e4 | 960 | } |
020e322d | 961 | |
1da177e4 | 962 | if(hwif->mate) |
3f63c5e8 | 963 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base; |
1da177e4 LT |
964 | else |
965 | hwif->dma_master = base; | |
1da177e4 LT |
966 | return 0; |
967 | } | |
968 | ||
969 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
970 | { | |
2ad1e558 | 971 | if (hwif->mmio) |
1da177e4 | 972 | return ide_mapped_mmio_dma(hwif, base,ports); |
2ad1e558 | 973 | |
1da177e4 LT |
974 | return ide_iomio_dma(hwif, base, ports); |
975 | } | |
976 | ||
977 | /* | |
978 | * This can be called for a dynamically installed interface. Don't __init it | |
979 | */ | |
980 | void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports) | |
981 | { | |
982 | if (ide_dma_iobase(hwif, dma_base, num_ports)) | |
983 | return; | |
984 | ||
985 | if (ide_allocate_dma_engine(hwif)) { | |
986 | ide_release_dma(hwif); | |
987 | return; | |
988 | } | |
989 | ||
990 | if (!(hwif->dma_command)) | |
991 | hwif->dma_command = hwif->dma_base; | |
992 | if (!(hwif->dma_vendor1)) | |
993 | hwif->dma_vendor1 = (hwif->dma_base + 1); | |
994 | if (!(hwif->dma_status)) | |
995 | hwif->dma_status = (hwif->dma_base + 2); | |
996 | if (!(hwif->dma_vendor3)) | |
997 | hwif->dma_vendor3 = (hwif->dma_base + 3); | |
998 | if (!(hwif->dma_prdtable)) | |
999 | hwif->dma_prdtable = (hwif->dma_base + 4); | |
1000 | ||
7469aaf6 BZ |
1001 | if (!hwif->dma_off_quietly) |
1002 | hwif->dma_off_quietly = &ide_dma_off_quietly; | |
1003 | if (!hwif->dma_host_off) | |
1004 | hwif->dma_host_off = &ide_dma_host_off; | |
1da177e4 LT |
1005 | if (!hwif->ide_dma_on) |
1006 | hwif->ide_dma_on = &__ide_dma_on; | |
ccf35289 BZ |
1007 | if (!hwif->dma_host_on) |
1008 | hwif->dma_host_on = &ide_dma_host_on; | |
1da177e4 LT |
1009 | if (!hwif->ide_dma_check) |
1010 | hwif->ide_dma_check = &__ide_dma_check; | |
1011 | if (!hwif->dma_setup) | |
1012 | hwif->dma_setup = &ide_dma_setup; | |
1013 | if (!hwif->dma_exec_cmd) | |
1014 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
1015 | if (!hwif->dma_start) | |
1016 | hwif->dma_start = &ide_dma_start; | |
1017 | if (!hwif->ide_dma_end) | |
1018 | hwif->ide_dma_end = &__ide_dma_end; | |
1019 | if (!hwif->ide_dma_test_irq) | |
1020 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
1021 | if (!hwif->ide_dma_timeout) | |
1022 | hwif->ide_dma_timeout = &__ide_dma_timeout; | |
1023 | if (!hwif->ide_dma_lostirq) | |
1024 | hwif->ide_dma_lostirq = &__ide_dma_lostirq; | |
1025 | ||
1026 | if (hwif->chipset != ide_trm290) { | |
1027 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
1028 | printk(", BIOS settings: %s:%s, %s:%s", | |
1029 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", | |
1030 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); | |
1031 | } | |
1032 | printk("\n"); | |
1033 | ||
125e1874 | 1034 | BUG_ON(!hwif->dma_master); |
1da177e4 LT |
1035 | } |
1036 | ||
1037 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
1038 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |