Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
204f47c5 BZ |
2 | * IDE DMA support (including IDE PCI BM-DMA). |
3 | * | |
59bca8cc BZ |
4 | * Copyright (C) 1995-1998 Mark Lord |
5 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 7 | * |
1da177e4 | 8 | * May be copied or modified under the terms of the GNU General Public License |
204f47c5 BZ |
9 | * |
10 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * Special Thanks to Mark for his Six years of work. | |
1da177e4 LT |
15 | */ |
16 | ||
17 | /* | |
1da177e4 LT |
18 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for |
19 | * fixing the problem with the BIOS on some Acer motherboards. | |
20 | * | |
21 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
22 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
23 | * | |
24 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
25 | * at generic DMA -- his patches were referred to when preparing this code. | |
26 | * | |
27 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
28 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/types.h> |
32 | #include <linux/kernel.h> | |
1da177e4 | 33 | #include <linux/ide.h> |
1da177e4 | 34 | #include <linux/scatterlist.h> |
5c05ff68 | 35 | #include <linux/dma-mapping.h> |
db3f99ef | 36 | #include <linux/io.h> |
1da177e4 | 37 | |
db3f99ef | 38 | static const struct drive_list_entry drive_whitelist[] = { |
c2d3ce8c JH |
39 | { "Micropolis 2112A" , NULL }, |
40 | { "CONNER CTMA 4000" , NULL }, | |
41 | { "CONNER CTT8000-A" , NULL }, | |
42 | { "ST34342A" , NULL }, | |
1da177e4 LT |
43 | { NULL , NULL } |
44 | }; | |
45 | ||
db3f99ef | 46 | static const struct drive_list_entry drive_blacklist[] = { |
c2d3ce8c JH |
47 | { "WDC AC11000H" , NULL }, |
48 | { "WDC AC22100H" , NULL }, | |
49 | { "WDC AC32500H" , NULL }, | |
50 | { "WDC AC33100H" , NULL }, | |
51 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
52 | { "WDC AC32100H" , "24.09P07" }, |
53 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
54 | { "Compaq CRD-8241B" , NULL }, |
55 | { "CRD-8400B" , NULL }, | |
56 | { "CRD-8480B", NULL }, | |
57 | { "CRD-8482B", NULL }, | |
58 | { "CRD-84" , NULL }, | |
59 | { "SanDisk SDP3B" , NULL }, | |
60 | { "SanDisk SDP3B-64" , NULL }, | |
61 | { "SANYO CD-ROM CRD" , NULL }, | |
62 | { "HITACHI CDR-8" , NULL }, | |
63 | { "HITACHI CDR-8335" , NULL }, | |
64 | { "HITACHI CDR-8435" , NULL }, | |
65 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
66 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
67 | { "CD-532E-A" , NULL }, | |
68 | { "E-IDE CD-ROM CR-840", NULL }, | |
69 | { "CD-ROM Drive/F5A", NULL }, | |
70 | { "WPI CDD-820", NULL }, | |
71 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
72 | { "SAMSUNG CD-ROM SC", NULL }, | |
73 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
74 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 75 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 76 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 77 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
78 | { NULL , NULL } |
79 | ||
80 | }; | |
81 | ||
1da177e4 LT |
82 | /** |
83 | * ide_dma_intr - IDE DMA interrupt handler | |
84 | * @drive: the drive the interrupt is for | |
85 | * | |
db3f99ef | 86 | * Handle an interrupt completing a read/write DMA transfer on an |
1da177e4 LT |
87 | * IDE device |
88 | */ | |
db3f99ef BZ |
89 | |
90 | ide_startstop_t ide_dma_intr(ide_drive_t *drive) | |
1da177e4 | 91 | { |
b73c7ee2 | 92 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 LT |
93 | u8 stat = 0, dma_stat = 0; |
94 | ||
b73c7ee2 | 95 | dma_stat = hwif->dma_ops->dma_end(drive); |
374e042c | 96 | stat = hwif->tp_ops->read_status(hwif); |
c47137a9 | 97 | |
3a7d2484 | 98 | if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) { |
1da177e4 | 99 | if (!dma_stat) { |
db3f99ef | 100 | struct request *rq = hwif->hwgroup->rq; |
1da177e4 | 101 | |
4d7a984b | 102 | task_end_request(drive, rq, stat); |
1da177e4 LT |
103 | return ide_stopped; |
104 | } | |
db3f99ef BZ |
105 | printk(KERN_ERR "%s: %s: bad DMA status (0x%02x)\n", |
106 | drive->name, __func__, dma_stat); | |
1da177e4 LT |
107 | } |
108 | return ide_error(drive, "dma_intr", stat); | |
109 | } | |
1da177e4 LT |
110 | EXPORT_SYMBOL_GPL(ide_dma_intr); |
111 | ||
75d7d963 BZ |
112 | static int ide_dma_good_drive(ide_drive_t *drive) |
113 | { | |
114 | return ide_in_drive_list(drive->id, drive_whitelist); | |
115 | } | |
116 | ||
1da177e4 LT |
117 | /** |
118 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
119 | * @drive: the drive to build the DMA table for | |
120 | * @rq: the request holding the sg list | |
121 | * | |
5c05ff68 BZ |
122 | * Perform the DMA mapping magic necessary to access the source or |
123 | * target buffers of a request via DMA. The lower layers of the | |
1da177e4 | 124 | * kernel provide the necessary cache management so that we can |
5c05ff68 | 125 | * operate in a portable fashion. |
1da177e4 LT |
126 | */ |
127 | ||
128 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
129 | { | |
db3f99ef | 130 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 LT |
131 | struct scatterlist *sg = hwif->sg_table; |
132 | ||
1da177e4 LT |
133 | ide_map_sg(drive, rq); |
134 | ||
135 | if (rq_data_dir(rq) == READ) | |
5c05ff68 | 136 | hwif->sg_dma_direction = DMA_FROM_DEVICE; |
1da177e4 | 137 | else |
5c05ff68 | 138 | hwif->sg_dma_direction = DMA_TO_DEVICE; |
1da177e4 | 139 | |
5c05ff68 BZ |
140 | return dma_map_sg(hwif->dev, sg, hwif->sg_nents, |
141 | hwif->sg_dma_direction); | |
1da177e4 | 142 | } |
1da177e4 LT |
143 | EXPORT_SYMBOL_GPL(ide_build_sglist); |
144 | ||
8e882ba1 | 145 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
146 | /** |
147 | * ide_build_dmatable - build IDE DMA table | |
148 | * | |
149 | * ide_build_dmatable() prepares a dma request. We map the command | |
150 | * to get the pci bus addresses of the buffers and then build up | |
14c123f3 BZ |
151 | * the PRD table that the IDE layer wants to be fed. |
152 | * | |
153 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
154 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
155 | * So we break the 64KB entry into two 32KB entries instead. | |
1da177e4 LT |
156 | * |
157 | * Returns the number of built PRD entries if all went okay, | |
158 | * returns 0 otherwise. | |
159 | * | |
160 | * May also be invoked from trm290.c | |
161 | */ | |
db3f99ef BZ |
162 | |
163 | int ide_build_dmatable(ide_drive_t *drive, struct request *rq) | |
1da177e4 | 164 | { |
db3f99ef | 165 | ide_hwif_t *hwif = drive->hwif; |
7fa897b9 | 166 | __le32 *table = (__le32 *)hwif->dmatable_cpu; |
1da177e4 LT |
167 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; |
168 | unsigned int count = 0; | |
169 | int i; | |
170 | struct scatterlist *sg; | |
171 | ||
14c123f3 BZ |
172 | hwif->sg_nents = ide_build_sglist(drive, rq); |
173 | if (hwif->sg_nents == 0) | |
1da177e4 LT |
174 | return 0; |
175 | ||
14c123f3 BZ |
176 | for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) { |
177 | u32 cur_addr, cur_len, xcount, bcount; | |
1da177e4 LT |
178 | |
179 | cur_addr = sg_dma_address(sg); | |
180 | cur_len = sg_dma_len(sg); | |
181 | ||
182 | /* | |
183 | * Fill in the dma table, without crossing any 64kB boundaries. | |
184 | * Most hardware requires 16-bit alignment of all blocks, | |
185 | * but the trm290 requires 32-bit alignment. | |
186 | */ | |
187 | ||
188 | while (cur_len) { | |
14c123f3 | 189 | if (count++ >= PRD_ENTRIES) |
1da177e4 | 190 | goto use_pio_instead; |
14c123f3 BZ |
191 | |
192 | bcount = 0x10000 - (cur_addr & 0xffff); | |
193 | if (bcount > cur_len) | |
194 | bcount = cur_len; | |
195 | *table++ = cpu_to_le32(cur_addr); | |
196 | xcount = bcount & 0xffff; | |
197 | if (is_trm290) | |
198 | xcount = ((xcount >> 2) - 1) << 16; | |
199 | if (xcount == 0x0000) { | |
200 | if (count++ >= PRD_ENTRIES) | |
201 | goto use_pio_instead; | |
202 | *table++ = cpu_to_le32(0x8000); | |
203 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
204 | xcount = 0x8000; | |
1da177e4 | 205 | } |
14c123f3 BZ |
206 | *table++ = cpu_to_le32(xcount); |
207 | cur_addr += bcount; | |
208 | cur_len -= bcount; | |
1da177e4 | 209 | } |
1da177e4 LT |
210 | } |
211 | ||
212 | if (count) { | |
213 | if (!is_trm290) | |
214 | *--table |= cpu_to_le32(0x80000000); | |
215 | return count; | |
216 | } | |
f6fb786d | 217 | |
1da177e4 | 218 | use_pio_instead: |
14c123f3 BZ |
219 | printk(KERN_ERR "%s: %s\n", drive->name, |
220 | count ? "DMA table too small" : "empty DMA table?"); | |
221 | ||
f6fb786d BZ |
222 | ide_destroy_dmatable(drive); |
223 | ||
1da177e4 LT |
224 | return 0; /* revert to PIO for this request */ |
225 | } | |
1da177e4 | 226 | EXPORT_SYMBOL_GPL(ide_build_dmatable); |
062f9f02 | 227 | #endif |
1da177e4 LT |
228 | |
229 | /** | |
230 | * ide_destroy_dmatable - clean up DMA mapping | |
231 | * @drive: The drive to unmap | |
232 | * | |
233 | * Teardown mappings after DMA has completed. This must be called | |
234 | * after the completion of each use of ide_build_dmatable and before | |
235 | * the next use of ide_build_dmatable. Failure to do so will cause | |
236 | * an oops as only one mapping can be live for each target at a given | |
237 | * time. | |
238 | */ | |
db3f99ef BZ |
239 | |
240 | void ide_destroy_dmatable(ide_drive_t *drive) | |
1da177e4 | 241 | { |
36501650 | 242 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 243 | |
5c05ff68 | 244 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, |
36501650 | 245 | hwif->sg_dma_direction); |
1da177e4 | 246 | } |
1da177e4 LT |
247 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); |
248 | ||
8e882ba1 | 249 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
250 | /** |
251 | * config_drive_for_dma - attempt to activate IDE DMA | |
252 | * @drive: the drive to place in DMA mode | |
253 | * | |
254 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
255 | * then attempt to place it into DMA mode. Drives that are known to | |
256 | * support DMA but predate the DMA properties or that are known | |
257 | * to have DMA handling bugs are also set up appropriately based | |
258 | * on the good/bad drive lists. | |
259 | */ | |
db3f99ef BZ |
260 | |
261 | static int config_drive_for_dma(ide_drive_t *drive) | |
1da177e4 | 262 | { |
1116fae5 | 263 | ide_hwif_t *hwif = drive->hwif; |
4dde4492 | 264 | u16 *id = drive->id; |
1da177e4 | 265 | |
33c1002e BZ |
266 | if (drive->media != ide_disk) { |
267 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
bcbf6ee3 | 268 | return 0; |
33c1002e | 269 | } |
1116fae5 | 270 | |
0ae2e178 BZ |
271 | /* |
272 | * Enable DMA on any drive that has | |
273 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
274 | */ | |
4dde4492 BZ |
275 | if ((id[ATA_ID_FIELD_VALID] & 4) && |
276 | ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f)) | |
0ae2e178 BZ |
277 | return 1; |
278 | ||
279 | /* | |
280 | * Enable DMA on any drive that has mode2 DMA | |
281 | * (multi or single) enabled | |
282 | */ | |
4dde4492 BZ |
283 | if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */ |
284 | if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 || | |
285 | (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404) | |
0ae2e178 | 286 | return 1; |
3608b5d7 | 287 | |
0ae2e178 BZ |
288 | /* Consult the list of known "good" drives */ |
289 | if (ide_dma_good_drive(drive)) | |
290 | return 1; | |
291 | ||
292 | return 0; | |
1da177e4 LT |
293 | } |
294 | ||
295 | /** | |
296 | * dma_timer_expiry - handle a DMA timeout | |
297 | * @drive: Drive that timed out | |
298 | * | |
299 | * An IDE DMA transfer timed out. In the event of an error we ask | |
300 | * the driver to resolve the problem, if a DMA transfer is still | |
db3f99ef | 301 | * in progress we continue to wait (arguably we need to add a |
1da177e4 LT |
302 | * secondary 'I don't care what the drive thinks' timeout here) |
303 | * Finally if we have an interrupt we let it complete the I/O. | |
304 | * But only one time - we clear expiry and if it's still not | |
305 | * completed after WAIT_CMD, we error and retry in PIO. | |
306 | * This can occur if an interrupt is lost or due to hang or bugs. | |
307 | */ | |
db3f99ef BZ |
308 | |
309 | static int dma_timer_expiry(ide_drive_t *drive) | |
1da177e4 | 310 | { |
db3f99ef BZ |
311 | ide_hwif_t *hwif = drive->hwif; |
312 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); | |
1da177e4 | 313 | |
db3f99ef BZ |
314 | printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n", |
315 | drive->name, __func__, dma_stat); | |
1da177e4 LT |
316 | |
317 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
318 | return WAIT_CMD; | |
319 | ||
db3f99ef | 320 | hwif->hwgroup->expiry = NULL; /* one free ride for now */ |
1da177e4 LT |
321 | |
322 | /* 1 dmaing, 2 error, 4 intr */ | |
323 | if (dma_stat & 2) /* ERROR */ | |
324 | return -1; | |
325 | ||
326 | if (dma_stat & 1) /* DMAing */ | |
327 | return WAIT_CMD; | |
328 | ||
329 | if (dma_stat & 4) /* Got an Interrupt */ | |
330 | return WAIT_CMD; | |
331 | ||
332 | return 0; /* Status is unknown -- reset the bus */ | |
333 | } | |
334 | ||
335 | /** | |
15ce926a | 336 | * ide_dma_host_set - Enable/disable DMA on a host |
1da177e4 LT |
337 | * @drive: drive to control |
338 | * | |
15ce926a BZ |
339 | * Enable/disable DMA on an IDE controller following generic |
340 | * bus-mastering IDE controller behaviour. | |
1da177e4 LT |
341 | */ |
342 | ||
15ce926a | 343 | void ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 344 | { |
db3f99ef BZ |
345 | ide_hwif_t *hwif = drive->hwif; |
346 | u8 unit = drive->dn & 1; | |
347 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); | |
1da177e4 | 348 | |
15ce926a BZ |
349 | if (on) |
350 | dma_stat |= (1 << (5 + unit)); | |
351 | else | |
352 | dma_stat &= ~(1 << (5 + unit)); | |
353 | ||
ab86f91e | 354 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
cab7f8ed BZ |
355 | writeb(dma_stat, |
356 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 357 | else |
cab7f8ed | 358 | outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 | 359 | } |
15ce926a | 360 | EXPORT_SYMBOL_GPL(ide_dma_host_set); |
8e882ba1 | 361 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 LT |
362 | |
363 | /** | |
7469aaf6 | 364 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
365 | * @drive: drive to control |
366 | * | |
db3f99ef | 367 | * Turn off the current DMA on this IDE controller. |
1da177e4 LT |
368 | */ |
369 | ||
7469aaf6 | 370 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 371 | { |
97100fc8 | 372 | drive->dev_flags &= ~IDE_DFLAG_USING_DMA; |
1da177e4 LT |
373 | ide_toggle_bounce(drive, 0); |
374 | ||
5e37bdc0 | 375 | drive->hwif->dma_ops->dma_host_set(drive, 0); |
1da177e4 | 376 | } |
7469aaf6 | 377 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
378 | |
379 | /** | |
7469aaf6 | 380 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
381 | * @drive: drive to disable DMA on |
382 | * | |
383 | * Disable IDE DMA for a device on this IDE controller. | |
384 | * Inform the user that DMA has been disabled. | |
385 | */ | |
386 | ||
7469aaf6 | 387 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
388 | { |
389 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 390 | ide_dma_off_quietly(drive); |
1da177e4 | 391 | } |
7469aaf6 | 392 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 393 | |
1da177e4 | 394 | /** |
4a546e04 | 395 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
396 | * @drive: drive to enable DMA on |
397 | * | |
398 | * Enable IDE DMA for a device on this IDE controller. | |
399 | */ | |
4a546e04 BZ |
400 | |
401 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 402 | { |
97100fc8 | 403 | drive->dev_flags |= IDE_DFLAG_USING_DMA; |
1da177e4 LT |
404 | ide_toggle_bounce(drive, 1); |
405 | ||
5e37bdc0 | 406 | drive->hwif->dma_ops->dma_host_set(drive, 1); |
1da177e4 LT |
407 | } |
408 | ||
8e882ba1 | 409 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
410 | /** |
411 | * ide_dma_setup - begin a DMA phase | |
412 | * @drive: target device | |
413 | * | |
414 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
415 | * and then set up the DMA transfer registers for a device | |
416 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
417 | * override this function if they need to | |
418 | * | |
419 | * Returns 0 on success. If a PIO fallback is required then 1 | |
db3f99ef | 420 | * is returned. |
1da177e4 LT |
421 | */ |
422 | ||
423 | int ide_dma_setup(ide_drive_t *drive) | |
424 | { | |
425 | ide_hwif_t *hwif = drive->hwif; | |
db3f99ef | 426 | struct request *rq = hwif->hwgroup->rq; |
1da177e4 | 427 | unsigned int reading; |
ab86f91e | 428 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
1da177e4 LT |
429 | u8 dma_stat; |
430 | ||
431 | if (rq_data_dir(rq)) | |
432 | reading = 0; | |
433 | else | |
434 | reading = 1 << 3; | |
435 | ||
436 | /* fall back to pio! */ | |
437 | if (!ide_build_dmatable(drive, rq)) { | |
438 | ide_map_sg(drive, rq); | |
439 | return 1; | |
440 | } | |
441 | ||
442 | /* PRD table */ | |
13572144 | 443 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
55224bc8 BZ |
444 | writel(hwif->dmatable_dma, |
445 | (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS)); | |
0ecdca26 | 446 | else |
55224bc8 | 447 | outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS); |
1da177e4 LT |
448 | |
449 | /* specify r/w */ | |
ab86f91e | 450 | if (mmio) |
cab7f8ed | 451 | writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 452 | else |
cab7f8ed | 453 | outb(reading, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 454 | |
b2f951aa | 455 | /* read DMA status for INTR & ERROR flags */ |
374e042c | 456 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
1da177e4 LT |
457 | |
458 | /* clear INTR & ERROR flags */ | |
ab86f91e | 459 | if (mmio) |
cab7f8ed BZ |
460 | writeb(dma_stat | 6, |
461 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 462 | else |
cab7f8ed | 463 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
ab86f91e | 464 | |
1da177e4 LT |
465 | drive->waiting_for_dma = 1; |
466 | return 0; | |
467 | } | |
1da177e4 LT |
468 | EXPORT_SYMBOL_GPL(ide_dma_setup); |
469 | ||
f37afdac | 470 | void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1da177e4 LT |
471 | { |
472 | /* issue cmd to drive */ | |
db3f99ef BZ |
473 | ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD, |
474 | dma_timer_expiry); | |
1da177e4 | 475 | } |
f37afdac | 476 | EXPORT_SYMBOL_GPL(ide_dma_exec_cmd); |
1da177e4 LT |
477 | |
478 | void ide_dma_start(ide_drive_t *drive) | |
479 | { | |
ab86f91e BZ |
480 | ide_hwif_t *hwif = drive->hwif; |
481 | u8 dma_cmd; | |
1da177e4 LT |
482 | |
483 | /* Note that this is done *after* the cmd has | |
484 | * been issued to the drive, as per the BM-IDE spec. | |
485 | * The Promise Ultra33 doesn't work correctly when | |
486 | * we do this part before issuing the drive cmd. | |
487 | */ | |
ab86f91e | 488 | if (hwif->host_flags & IDE_HFLAG_MMIO) { |
cab7f8ed | 489 | dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 490 | /* start DMA */ |
cab7f8ed BZ |
491 | writeb(dma_cmd | 1, |
492 | (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); | |
ab86f91e | 493 | } else { |
cab7f8ed BZ |
494 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
495 | outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD); | |
ab86f91e BZ |
496 | } |
497 | ||
1da177e4 LT |
498 | wmb(); |
499 | } | |
1da177e4 LT |
500 | EXPORT_SYMBOL_GPL(ide_dma_start); |
501 | ||
502 | /* returns 1 on error, 0 otherwise */ | |
653bcf52 | 503 | int ide_dma_end(ide_drive_t *drive) |
1da177e4 | 504 | { |
ab86f91e BZ |
505 | ide_hwif_t *hwif = drive->hwif; |
506 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; | |
1da177e4 LT |
507 | u8 dma_stat = 0, dma_cmd = 0; |
508 | ||
509 | drive->waiting_for_dma = 0; | |
ab86f91e BZ |
510 | |
511 | if (mmio) { | |
512 | /* get DMA command mode */ | |
cab7f8ed | 513 | dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 514 | /* stop DMA */ |
cab7f8ed BZ |
515 | writeb(dma_cmd & ~1, |
516 | (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); | |
ab86f91e | 517 | } else { |
cab7f8ed BZ |
518 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
519 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); | |
ab86f91e BZ |
520 | } |
521 | ||
1da177e4 | 522 | /* get DMA status */ |
374e042c | 523 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
ab86f91e BZ |
524 | |
525 | if (mmio) | |
526 | /* clear the INTR & ERROR bits */ | |
cab7f8ed BZ |
527 | writeb(dma_stat | 6, |
528 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 529 | else |
cab7f8ed | 530 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
ab86f91e | 531 | |
1da177e4 LT |
532 | /* purge DMA mappings */ |
533 | ide_destroy_dmatable(drive); | |
534 | /* verify good DMA status */ | |
1da177e4 LT |
535 | wmb(); |
536 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
537 | } | |
653bcf52 | 538 | EXPORT_SYMBOL_GPL(ide_dma_end); |
1da177e4 LT |
539 | |
540 | /* returns 1 if dma irq issued, 0 otherwise */ | |
f37afdac | 541 | int ide_dma_test_irq(ide_drive_t *drive) |
1da177e4 | 542 | { |
db3f99ef BZ |
543 | ide_hwif_t *hwif = drive->hwif; |
544 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); | |
1da177e4 | 545 | |
1da177e4 LT |
546 | /* return 1 if INTR asserted */ |
547 | if ((dma_stat & 4) == 4) | |
548 | return 1; | |
c67c216d | 549 | |
1da177e4 LT |
550 | return 0; |
551 | } | |
f37afdac | 552 | EXPORT_SYMBOL_GPL(ide_dma_test_irq); |
0ae2e178 BZ |
553 | #else |
554 | static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } | |
8e882ba1 | 555 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 | 556 | |
db3f99ef | 557 | int __ide_dma_bad_drive(ide_drive_t *drive) |
1da177e4 | 558 | { |
4dde4492 | 559 | u16 *id = drive->id; |
1da177e4 | 560 | |
65e5f2e3 | 561 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
562 | if (blacklist) { |
563 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
4dde4492 | 564 | drive->name, (char *)&id[ATA_ID_PROD]); |
1da177e4 LT |
565 | return blacklist; |
566 | } | |
567 | return 0; | |
568 | } | |
1da177e4 LT |
569 | EXPORT_SYMBOL(__ide_dma_bad_drive); |
570 | ||
2d5eaa6d BZ |
571 | static const u8 xfer_mode_bases[] = { |
572 | XFER_UDMA_0, | |
573 | XFER_MW_DMA_0, | |
574 | XFER_SW_DMA_0, | |
575 | }; | |
576 | ||
7670df73 | 577 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d | 578 | { |
4dde4492 | 579 | u16 *id = drive->id; |
2d5eaa6d | 580 | ide_hwif_t *hwif = drive->hwif; |
ac95beed | 581 | const struct ide_port_ops *port_ops = hwif->port_ops; |
2d5eaa6d BZ |
582 | unsigned int mask = 0; |
583 | ||
db3f99ef | 584 | switch (base) { |
2d5eaa6d | 585 | case XFER_UDMA_0: |
4dde4492 | 586 | if ((id[ATA_ID_FIELD_VALID] & 4) == 0) |
2d5eaa6d BZ |
587 | break; |
588 | ||
ac95beed BZ |
589 | if (port_ops && port_ops->udma_filter) |
590 | mask = port_ops->udma_filter(drive); | |
851dd33b SS |
591 | else |
592 | mask = hwif->ultra_mask; | |
4dde4492 | 593 | mask &= id[ATA_ID_UDMA_MODES]; |
2d5eaa6d | 594 | |
7670df73 BZ |
595 | /* |
596 | * avoid false cable warning from eighty_ninty_three() | |
597 | */ | |
598 | if (req_mode > XFER_UDMA_2) { | |
599 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
600 | mask &= 0x07; | |
601 | } | |
2d5eaa6d BZ |
602 | break; |
603 | case XFER_MW_DMA_0: | |
4dde4492 | 604 | if ((id[ATA_ID_FIELD_VALID] & 2) == 0) |
b4e44369 | 605 | break; |
ac95beed BZ |
606 | if (port_ops && port_ops->mdma_filter) |
607 | mask = port_ops->mdma_filter(drive); | |
b4e44369 SS |
608 | else |
609 | mask = hwif->mwdma_mask; | |
4dde4492 | 610 | mask &= id[ATA_ID_MWDMA_MODES]; |
2d5eaa6d BZ |
611 | break; |
612 | case XFER_SW_DMA_0: | |
4dde4492 BZ |
613 | if (id[ATA_ID_FIELD_VALID] & 2) { |
614 | mask = id[ATA_ID_SWDMA_MODES] & hwif->swdma_mask; | |
48fb2688 BZ |
615 | } else if (id[ATA_ID_OLD_DMA_MODES] >> 8) { |
616 | u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8; | |
15a4f943 BZ |
617 | |
618 | /* | |
619 | * if the mode is valid convert it to the mask | |
620 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
621 | */ | |
622 | if (mode <= 2) | |
623 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
624 | } | |
2d5eaa6d BZ |
625 | break; |
626 | default: | |
627 | BUG(); | |
628 | break; | |
629 | } | |
630 | ||
631 | return mask; | |
632 | } | |
633 | ||
634 | /** | |
7670df73 | 635 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 636 | * @drive: IDE device |
7670df73 BZ |
637 | * @req_mode: requested mode |
638 | * | |
639 | * Checks the drive/host capabilities and finds the speed to use for | |
640 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 641 | * |
7670df73 BZ |
642 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
643 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
644 | */ |
645 | ||
7670df73 | 646 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
647 | { |
648 | ide_hwif_t *hwif = drive->hwif; | |
649 | unsigned int mask; | |
650 | int x, i; | |
651 | u8 mode = 0; | |
652 | ||
33c1002e BZ |
653 | if (drive->media != ide_disk) { |
654 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
655 | return 0; | |
656 | } | |
2d5eaa6d BZ |
657 | |
658 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
659 | if (req_mode < xfer_mode_bases[i]) |
660 | continue; | |
661 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
662 | x = fls(mask) - 1; |
663 | if (x >= 0) { | |
664 | mode = xfer_mode_bases[i] + x; | |
665 | break; | |
666 | } | |
667 | } | |
668 | ||
75d7d963 BZ |
669 | if (hwif->chipset == ide_acorn && mode == 0) { |
670 | /* | |
671 | * is this correct? | |
672 | */ | |
4dde4492 BZ |
673 | if (ide_dma_good_drive(drive) && |
674 | drive->id[ATA_ID_EIDE_DMA_TIME] < 150) | |
75d7d963 BZ |
675 | mode = XFER_MW_DMA_1; |
676 | } | |
677 | ||
3ab7efe8 BZ |
678 | mode = min(mode, req_mode); |
679 | ||
680 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 681 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 682 | |
3ab7efe8 | 683 | return mode; |
2d5eaa6d | 684 | } |
7670df73 | 685 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 686 | |
0ae2e178 | 687 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 688 | { |
8704de8f | 689 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
690 | u8 speed; |
691 | ||
97100fc8 BZ |
692 | if (ata_id_has_dma(drive->id) == 0 || |
693 | (drive->dev_flags & IDE_DFLAG_NODMA)) | |
122ab088 BZ |
694 | return 0; |
695 | ||
696 | /* consult the list of known "bad" drives */ | |
697 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
698 | return 0; |
699 | ||
3ab7efe8 BZ |
700 | if (ide_id_dma_bug(drive)) |
701 | return 0; | |
702 | ||
8704de8f | 703 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
704 | return config_drive_for_dma(drive); |
705 | ||
29e744d0 BZ |
706 | speed = ide_max_dma_mode(drive); |
707 | ||
951784b6 BZ |
708 | if (!speed) |
709 | return 0; | |
29e744d0 | 710 | |
88b2b32b | 711 | if (ide_set_dma_mode(drive, speed)) |
4728d546 | 712 | return 0; |
29e744d0 | 713 | |
4728d546 | 714 | return 1; |
29e744d0 BZ |
715 | } |
716 | ||
0ae2e178 BZ |
717 | static int ide_dma_check(ide_drive_t *drive) |
718 | { | |
719 | ide_hwif_t *hwif = drive->hwif; | |
0ae2e178 | 720 | |
ba4b2e60 | 721 | if (ide_tune_dma(drive)) |
0ae2e178 BZ |
722 | return 0; |
723 | ||
724 | /* TODO: always do PIO fallback */ | |
725 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
726 | return -1; | |
727 | ||
728 | ide_set_max_pio(drive); | |
729 | ||
ba4b2e60 | 730 | return -1; |
0ae2e178 BZ |
731 | } |
732 | ||
3ab7efe8 | 733 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 734 | { |
4dde4492 | 735 | u16 *id = drive->id; |
1da177e4 | 736 | |
4dde4492 BZ |
737 | if (id[ATA_ID_FIELD_VALID] & 4) { |
738 | if ((id[ATA_ID_UDMA_MODES] >> 8) && | |
739 | (id[ATA_ID_MWDMA_MODES] >> 8)) | |
3ab7efe8 | 740 | goto err_out; |
4dde4492 BZ |
741 | } else if (id[ATA_ID_FIELD_VALID] & 2) { |
742 | if ((id[ATA_ID_MWDMA_MODES] >> 8) && | |
743 | (id[ATA_ID_SWDMA_MODES] >> 8)) | |
3ab7efe8 | 744 | goto err_out; |
1da177e4 | 745 | } |
3ab7efe8 BZ |
746 | return 0; |
747 | err_out: | |
748 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
749 | return 1; | |
1da177e4 LT |
750 | } |
751 | ||
3608b5d7 BZ |
752 | int ide_set_dma(ide_drive_t *drive) |
753 | { | |
3608b5d7 BZ |
754 | int rc; |
755 | ||
7b905994 BZ |
756 | /* |
757 | * Force DMAing for the beginning of the check. | |
758 | * Some chipsets appear to do interesting | |
759 | * things, if not checked and cleared. | |
760 | * PARANOIA!!! | |
761 | */ | |
4a546e04 | 762 | ide_dma_off_quietly(drive); |
3608b5d7 | 763 | |
7b905994 BZ |
764 | rc = ide_dma_check(drive); |
765 | if (rc) | |
766 | return rc; | |
3608b5d7 | 767 | |
4a546e04 BZ |
768 | ide_dma_on(drive); |
769 | ||
770 | return 0; | |
3608b5d7 BZ |
771 | } |
772 | ||
578cfa0d BZ |
773 | void ide_check_dma_crc(ide_drive_t *drive) |
774 | { | |
775 | u8 mode; | |
776 | ||
777 | ide_dma_off_quietly(drive); | |
778 | drive->crc_count = 0; | |
779 | mode = drive->current_speed; | |
780 | /* | |
781 | * Don't try non Ultra-DMA modes without iCRC's. Force the | |
782 | * device to PIO and make the user enable SWDMA/MWDMA modes. | |
783 | */ | |
784 | if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) | |
785 | mode--; | |
786 | else | |
787 | mode = XFER_PIO_4; | |
788 | ide_set_xfer_rate(drive, mode); | |
789 | if (drive->current_speed >= XFER_SW_DMA_0) | |
790 | ide_dma_on(drive); | |
791 | } | |
792 | ||
de23ec9c | 793 | void ide_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 794 | { |
de23ec9c | 795 | printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name); |
1da177e4 | 796 | } |
de23ec9c | 797 | EXPORT_SYMBOL_GPL(ide_dma_lost_irq); |
1da177e4 | 798 | |
ffa15a69 | 799 | void ide_dma_timeout(ide_drive_t *drive) |
1da177e4 | 800 | { |
db3f99ef | 801 | ide_hwif_t *hwif = drive->hwif; |
c283f5db | 802 | |
1da177e4 | 803 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 804 | |
5e37bdc0 | 805 | if (hwif->dma_ops->dma_test_irq(drive)) |
c283f5db SS |
806 | return; |
807 | ||
ffa15a69 BZ |
808 | ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif)); |
809 | ||
5e37bdc0 | 810 | hwif->dma_ops->dma_end(drive); |
1da177e4 | 811 | } |
ffa15a69 | 812 | EXPORT_SYMBOL_GPL(ide_dma_timeout); |
1da177e4 | 813 | |
0d1bad21 | 814 | void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
815 | { |
816 | if (hwif->dmatable_cpu) { | |
2bbd57ca | 817 | int prd_size = hwif->prd_max_nents * hwif->prd_ent_size; |
36501650 | 818 | |
2bbd57ca BZ |
819 | dma_free_coherent(hwif->dev, prd_size, |
820 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
1da177e4 LT |
821 | hwif->dmatable_cpu = NULL; |
822 | } | |
1da177e4 | 823 | } |
2bbd57ca | 824 | EXPORT_SYMBOL_GPL(ide_release_dma_engine); |
1da177e4 | 825 | |
b8e73fba | 826 | int ide_allocate_dma_engine(ide_hwif_t *hwif) |
1da177e4 | 827 | { |
2bbd57ca | 828 | int prd_size; |
36501650 | 829 | |
2bbd57ca BZ |
830 | if (hwif->prd_max_nents == 0) |
831 | hwif->prd_max_nents = PRD_ENTRIES; | |
832 | if (hwif->prd_ent_size == 0) | |
833 | hwif->prd_ent_size = PRD_BYTES; | |
1da177e4 | 834 | |
2bbd57ca | 835 | prd_size = hwif->prd_max_nents * hwif->prd_ent_size; |
1da177e4 | 836 | |
2bbd57ca BZ |
837 | hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev, prd_size, |
838 | &hwif->dmatable_dma, | |
839 | GFP_ATOMIC); | |
840 | if (hwif->dmatable_cpu == NULL) { | |
841 | printk(KERN_ERR "%s: unable to allocate PRD table\n", | |
5e59c236 | 842 | hwif->name); |
2bbd57ca BZ |
843 | return -ENOMEM; |
844 | } | |
1da177e4 | 845 | |
2bbd57ca | 846 | return 0; |
1da177e4 | 847 | } |
b8e73fba | 848 | EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); |
1da177e4 | 849 | |
2bbd57ca | 850 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
81e8d5a3 | 851 | const struct ide_dma_ops sff_dma_ops = { |
5e37bdc0 BZ |
852 | .dma_host_set = ide_dma_host_set, |
853 | .dma_setup = ide_dma_setup, | |
854 | .dma_exec_cmd = ide_dma_exec_cmd, | |
855 | .dma_start = ide_dma_start, | |
653bcf52 | 856 | .dma_end = ide_dma_end, |
f37afdac | 857 | .dma_test_irq = ide_dma_test_irq, |
5e37bdc0 BZ |
858 | .dma_timeout = ide_dma_timeout, |
859 | .dma_lost_irq = ide_dma_lost_irq, | |
860 | }; | |
81e8d5a3 | 861 | EXPORT_SYMBOL_GPL(sff_dma_ops); |
8e882ba1 | 862 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |