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1da177e4 | 1 | /* |
21b82477 | 2 | * linux/drivers/ide/pci/alim15x3.c Version 0.21 2007/02/03 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry, Maintainer | |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer | |
6 | * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer | |
7 | * | |
8 | * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org) | |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * Copyright (C) 2002 Alan Cox <alan@redhat.com> | |
11 | * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw> | |
21b82477 | 12 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
13 | * |
14 | * (U)DMA capable version of ali 1533/1543(C), 1535(D) | |
15 | * | |
16 | ********************************************************************** | |
17 | * 9/7/99 --Parts from the above author are included and need to be | |
18 | * converted into standard interface, once I finish the thought. | |
19 | * | |
20 | * Recent changes | |
21 | * Don't use LBA48 mode on ALi <= 0xC4 | |
22 | * Don't poke 0x79 with a non ALi northbridge | |
23 | * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang) | |
24 | * Allow UDMA6 on revisions > 0xC4 | |
25 | * | |
26 | * Documentation | |
27 | * Chipset documentation available under NDA only | |
28 | * | |
29 | */ | |
30 | ||
1da177e4 LT |
31 | #include <linux/module.h> |
32 | #include <linux/types.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/hdreg.h> | |
37 | #include <linux/ide.h> | |
38 | #include <linux/init.h> | |
39 | ||
40 | #include <asm/io.h> | |
41 | ||
42 | #define DISPLAY_ALI_TIMINGS | |
43 | ||
44 | /* | |
45 | * ALi devices are not plug in. Otherwise these static values would | |
46 | * need to go. They ought to go away anyway | |
47 | */ | |
48 | ||
49 | static u8 m5229_revision; | |
50 | static u8 chip_is_1543c_e; | |
51 | static struct pci_dev *isa_dev; | |
52 | ||
53 | #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) | |
54 | #include <linux/stat.h> | |
55 | #include <linux/proc_fs.h> | |
56 | ||
57 | static u8 ali_proc = 0; | |
58 | ||
59 | static struct pci_dev *bmide_dev; | |
60 | ||
61 | static char *fifo[4] = { | |
62 | "FIFO Off", | |
63 | "FIFO On ", | |
64 | "DMA mode", | |
65 | "PIO mode" }; | |
66 | ||
67 | static char *udmaT[8] = { | |
68 | "1.5T", | |
69 | " 2T", | |
70 | "2.5T", | |
71 | " 3T", | |
72 | "3.5T", | |
73 | " 4T", | |
74 | " 6T", | |
75 | " 8T" | |
76 | }; | |
77 | ||
78 | static char *channel_status[8] = { | |
79 | "OK ", | |
80 | "busy ", | |
81 | "DRQ ", | |
82 | "DRQ busy ", | |
83 | "error ", | |
84 | "error busy ", | |
85 | "error DRQ ", | |
86 | "error DRQ busy" | |
87 | }; | |
88 | ||
89 | /** | |
90 | * ali_get_info - generate proc file for ALi IDE | |
91 | * @buffer: buffer to fill | |
92 | * @addr: address of user start in buffer | |
93 | * @offset: offset into 'file' | |
94 | * @count: buffer count | |
95 | * | |
96 | * Walks the Ali devices and outputs summary data on the tuning and | |
97 | * anything else that will help with debugging | |
98 | */ | |
99 | ||
100 | static int ali_get_info (char *buffer, char **addr, off_t offset, int count) | |
101 | { | |
102 | unsigned long bibma; | |
103 | u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp; | |
104 | char *q, *p = buffer; | |
105 | ||
106 | /* fetch rev. */ | |
107 | pci_read_config_byte(bmide_dev, 0x08, &rev); | |
108 | if (rev >= 0xc1) /* M1543C or newer */ | |
109 | udmaT[7] = " ???"; | |
110 | else | |
111 | fifo[3] = " ??? "; | |
112 | ||
113 | /* first fetch bibma: */ | |
114 | ||
115 | bibma = pci_resource_start(bmide_dev, 4); | |
116 | ||
117 | /* | |
118 | * at that point bibma+0x2 et bibma+0xa are byte | |
119 | * registers to investigate: | |
120 | */ | |
121 | c0 = inb(bibma + 0x02); | |
122 | c1 = inb(bibma + 0x0a); | |
123 | ||
124 | p += sprintf(p, | |
125 | "\n Ali M15x3 Chipset.\n"); | |
126 | p += sprintf(p, | |
127 | " ------------------\n"); | |
128 | pci_read_config_byte(bmide_dev, 0x78, ®53h); | |
129 | p += sprintf(p, "PCI Clock: %d.\n", reg53h); | |
130 | ||
131 | pci_read_config_byte(bmide_dev, 0x53, ®53h); | |
132 | p += sprintf(p, | |
133 | "CD_ROM FIFO:%s, CD_ROM DMA:%s\n", | |
134 | (reg53h & 0x02) ? "Yes" : "No ", | |
135 | (reg53h & 0x01) ? "Yes" : "No " ); | |
136 | pci_read_config_byte(bmide_dev, 0x74, ®53h); | |
137 | p += sprintf(p, | |
138 | "FIFO Status: contains %d Words, runs%s%s\n\n", | |
139 | (reg53h & 0x3f), | |
140 | (reg53h & 0x40) ? " OVERWR" : "", | |
141 | (reg53h & 0x80) ? " OVERRD." : "." ); | |
142 | ||
143 | p += sprintf(p, | |
144 | "-------------------primary channel" | |
145 | "-------------------secondary channel" | |
146 | "---------\n\n"); | |
147 | ||
148 | pci_read_config_byte(bmide_dev, 0x09, ®53h); | |
149 | p += sprintf(p, | |
150 | "channel status: %s" | |
151 | " %s\n", | |
152 | (reg53h & 0x20) ? "On " : "Off", | |
153 | (reg53h & 0x10) ? "On " : "Off" ); | |
154 | ||
155 | p += sprintf(p, | |
156 | "both channels togth: %s" | |
157 | " %s\n", | |
158 | (c0&0x80) ? "No " : "Yes", | |
159 | (c1&0x80) ? "No " : "Yes" ); | |
160 | ||
161 | pci_read_config_byte(bmide_dev, 0x76, ®53h); | |
162 | p += sprintf(p, | |
163 | "Channel state: %s %s\n", | |
164 | channel_status[reg53h & 0x07], | |
165 | channel_status[(reg53h & 0x70) >> 4] ); | |
166 | ||
167 | pci_read_config_byte(bmide_dev, 0x58, ®5xh); | |
168 | pci_read_config_byte(bmide_dev, 0x5c, ®5yh); | |
169 | p += sprintf(p, | |
170 | "Add. Setup Timing: %dT" | |
171 | " %dT\n", | |
172 | (reg5xh & 0x07) ? (reg5xh & 0x07) : 8, | |
173 | (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 ); | |
174 | ||
175 | pci_read_config_byte(bmide_dev, 0x59, ®5xh); | |
176 | pci_read_config_byte(bmide_dev, 0x5d, ®5yh); | |
177 | p += sprintf(p, | |
178 | "Command Act. Count: %dT" | |
179 | " %dT\n" | |
180 | "Command Rec. Count: %dT" | |
181 | " %dT\n\n", | |
182 | (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8, | |
183 | (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8, | |
184 | (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16, | |
185 | (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 ); | |
186 | ||
187 | p += sprintf(p, | |
188 | "----------------drive0-----------drive1" | |
189 | "------------drive0-----------drive1------\n\n"); | |
190 | p += sprintf(p, | |
191 | "DMA enabled: %s %s" | |
192 | " %s %s\n", | |
193 | (c0&0x20) ? "Yes" : "No ", | |
194 | (c0&0x40) ? "Yes" : "No ", | |
195 | (c1&0x20) ? "Yes" : "No ", | |
196 | (c1&0x40) ? "Yes" : "No " ); | |
197 | ||
198 | pci_read_config_byte(bmide_dev, 0x54, ®5xh); | |
199 | pci_read_config_byte(bmide_dev, 0x55, ®5yh); | |
200 | q = "FIFO threshold: %2d Words %2d Words" | |
201 | " %2d Words %2d Words\n"; | |
202 | if (rev < 0xc1) { | |
203 | if ((rev == 0x20) && | |
204 | (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) { | |
205 | p += sprintf(p, q, 8, 8, 8, 8); | |
206 | } else { | |
207 | p += sprintf(p, q, | |
208 | (reg5xh & 0x03) + 12, | |
209 | ((reg5xh & 0x30)>>4) + 12, | |
210 | (reg5yh & 0x03) + 12, | |
211 | ((reg5yh & 0x30)>>4) + 12 ); | |
212 | } | |
213 | } else { | |
214 | int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4; | |
215 | int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4; | |
216 | int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4; | |
217 | int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4; | |
218 | p += sprintf(p, q, t1, t2, t3, t4); | |
219 | } | |
220 | ||
221 | #if 0 | |
222 | p += sprintf(p, | |
223 | "FIFO threshold: %2d Words %2d Words" | |
224 | " %2d Words %2d Words\n", | |
225 | (reg5xh & 0x03) + 12, | |
226 | ((reg5xh & 0x30)>>4) + 12, | |
227 | (reg5yh & 0x03) + 12, | |
228 | ((reg5yh & 0x30)>>4) + 12 ); | |
229 | #endif | |
230 | ||
231 | p += sprintf(p, | |
232 | "FIFO mode: %s %s %s %s\n", | |
233 | fifo[((reg5xh & 0x0c) >> 2)], | |
234 | fifo[((reg5xh & 0xc0) >> 6)], | |
235 | fifo[((reg5yh & 0x0c) >> 2)], | |
236 | fifo[((reg5yh & 0xc0) >> 6)] ); | |
237 | ||
238 | pci_read_config_byte(bmide_dev, 0x5a, ®5xh); | |
239 | pci_read_config_byte(bmide_dev, 0x5b, ®5xh1); | |
240 | pci_read_config_byte(bmide_dev, 0x5e, ®5yh); | |
241 | pci_read_config_byte(bmide_dev, 0x5f, ®5yh1); | |
242 | ||
243 | p += sprintf(p,/* | |
244 | "------------------drive0-----------drive1" | |
245 | "------------drive0-----------drive1------\n")*/ | |
246 | "Dt RW act. Cnt %2dT %2dT" | |
247 | " %2dT %2dT\n" | |
248 | "Dt RW rec. Cnt %2dT %2dT" | |
249 | " %2dT %2dT\n\n", | |
250 | (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8, | |
251 | (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8, | |
252 | (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8, | |
253 | (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8, | |
254 | (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16, | |
255 | (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16, | |
256 | (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16, | |
257 | (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 ); | |
258 | ||
259 | p += sprintf(p, | |
260 | "-----------------------------------UDMA Timings" | |
261 | "--------------------------------\n\n"); | |
262 | ||
263 | pci_read_config_byte(bmide_dev, 0x56, ®5xh); | |
264 | pci_read_config_byte(bmide_dev, 0x57, ®5yh); | |
265 | p += sprintf(p, | |
266 | "UDMA: %s %s" | |
267 | " %s %s\n" | |
268 | "UDMA timings: %s %s" | |
269 | " %s %s\n\n", | |
270 | (reg5xh & 0x08) ? "OK" : "No", | |
271 | (reg5xh & 0x80) ? "OK" : "No", | |
272 | (reg5yh & 0x08) ? "OK" : "No", | |
273 | (reg5yh & 0x80) ? "OK" : "No", | |
274 | udmaT[(reg5xh & 0x07)], | |
275 | udmaT[(reg5xh & 0x70) >> 4], | |
276 | udmaT[reg5yh & 0x07], | |
277 | udmaT[(reg5yh & 0x70) >> 4] ); | |
278 | ||
279 | return p-buffer; /* => must be less than 4k! */ | |
280 | } | |
281 | #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */ | |
282 | ||
283 | /** | |
21b82477 | 284 | * ali15x3_tune_pio - set up chipset for PIO mode |
1da177e4 | 285 | * @drive: drive to tune |
21b82477 | 286 | * @pio: desired mode |
1da177e4 | 287 | * |
21b82477 SS |
288 | * Select the best PIO mode for the drive in question. |
289 | * Then program the controller for this mode. | |
290 | * | |
291 | * Returns the PIO mode programmed. | |
1da177e4 LT |
292 | */ |
293 | ||
21b82477 | 294 | static u8 ali15x3_tune_pio (ide_drive_t *drive, u8 pio) |
1da177e4 LT |
295 | { |
296 | ide_pio_data_t d; | |
297 | ide_hwif_t *hwif = HWIF(drive); | |
298 | struct pci_dev *dev = hwif->pci_dev; | |
299 | int s_time, a_time, c_time; | |
300 | u8 s_clc, a_clc, r_clc; | |
301 | unsigned long flags; | |
302 | int bus_speed = system_bus_clock(); | |
303 | int port = hwif->channel ? 0x5c : 0x58; | |
304 | int portFIFO = hwif->channel ? 0x55 : 0x54; | |
305 | u8 cd_dma_fifo = 0; | |
306 | int unit = drive->select.b.unit & 1; | |
307 | ||
308 | pio = ide_get_best_pio_mode(drive, pio, 5, &d); | |
309 | s_time = ide_pio_timings[pio].setup_time; | |
310 | a_time = ide_pio_timings[pio].active_time; | |
311 | if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8) | |
312 | s_clc = 0; | |
313 | if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8) | |
314 | a_clc = 0; | |
315 | c_time = ide_pio_timings[pio].cycle_time; | |
316 | ||
317 | #if 0 | |
318 | if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16) | |
319 | r_clc = 0; | |
320 | #endif | |
321 | ||
322 | if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) { | |
323 | r_clc = 1; | |
324 | } else { | |
325 | if (r_clc >= 16) | |
326 | r_clc = 0; | |
327 | } | |
328 | local_irq_save(flags); | |
329 | ||
330 | /* | |
331 | * PIO mode => ATA FIFO on, ATAPI FIFO off | |
332 | */ | |
333 | pci_read_config_byte(dev, portFIFO, &cd_dma_fifo); | |
334 | if (drive->media==ide_disk) { | |
335 | if (unit) { | |
336 | pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50); | |
337 | } else { | |
338 | pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05); | |
339 | } | |
340 | } else { | |
341 | if (unit) { | |
342 | pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F); | |
343 | } else { | |
344 | pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0); | |
345 | } | |
346 | } | |
347 | ||
348 | pci_write_config_byte(dev, port, s_clc); | |
349 | pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc); | |
350 | local_irq_restore(flags); | |
351 | ||
352 | /* | |
353 | * setup active rec | |
354 | * { 70, 165, 365 }, PIO Mode 0 | |
355 | * { 50, 125, 208 }, PIO Mode 1 | |
356 | * { 30, 100, 110 }, PIO Mode 2 | |
357 | * { 30, 80, 70 }, PIO Mode 3 with IORDY | |
358 | * { 25, 70, 25 }, PIO Mode 4 with IORDY ns | |
359 | * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard) | |
360 | */ | |
361 | ||
21b82477 SS |
362 | return pio; |
363 | } | |
364 | ||
365 | /** | |
366 | * ali15x3_tune_drive - set up drive for PIO mode | |
367 | * @drive: drive to tune | |
368 | * @pio: desired mode | |
369 | * | |
370 | * Program the controller with the best PIO timing for the given drive. | |
371 | * Then set up the drive itself. | |
372 | */ | |
373 | ||
374 | static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio) | |
375 | { | |
376 | pio = ali15x3_tune_pio(drive, pio); | |
377 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
378 | } |
379 | ||
380 | /** | |
2d5eaa6d BZ |
381 | * ali_udma_filter - compute UDMA mask |
382 | * @drive: IDE device | |
1da177e4 | 383 | * |
2d5eaa6d BZ |
384 | * Return available UDMA modes. |
385 | * | |
386 | * The actual rules for the ALi are: | |
1da177e4 LT |
387 | * No UDMA on revisions <= 0x20 |
388 | * Disk only for revisions < 0xC2 | |
389 | * Not WDC drives for revisions < 0xC2 | |
390 | * | |
391 | * FIXME: WDC ifdef needs to die | |
392 | */ | |
1da177e4 | 393 | |
2d5eaa6d | 394 | static u8 ali_udma_filter(ide_drive_t *drive) |
1da177e4 | 395 | { |
2d5eaa6d BZ |
396 | if (m5229_revision > 0x20 && m5229_revision < 0xC2) { |
397 | if (drive->media != ide_disk) | |
398 | return 0; | |
399 | #ifndef CONFIG_WDC_ALI15X3 | |
400 | if (chip_is_1543c_e && strstr(drive->id->model, "WDC ")) | |
401 | return 0; | |
402 | #endif | |
1da177e4 LT |
403 | } |
404 | ||
2d5eaa6d | 405 | return drive->hwif->ultra_mask; |
1da177e4 LT |
406 | } |
407 | ||
408 | /** | |
21b82477 | 409 | * ali15x3_tune_chipset - set up chipset/drive for new speed |
1da177e4 LT |
410 | * @drive: drive to configure for |
411 | * @xferspeed: desired speed | |
412 | * | |
413 | * Configure the hardware for the desired IDE transfer mode. | |
414 | * We also do the needed drive configuration through helpers | |
415 | */ | |
416 | ||
417 | static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
418 | { | |
419 | ide_hwif_t *hwif = HWIF(drive); | |
420 | struct pci_dev *dev = hwif->pci_dev; | |
2d5eaa6d | 421 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
422 | u8 speed1 = speed; |
423 | u8 unit = (drive->select.b.unit & 0x01); | |
424 | u8 tmpbyte = 0x00; | |
425 | int m5229_udma = (hwif->channel) ? 0x57 : 0x56; | |
426 | ||
427 | if (speed == XFER_UDMA_6) | |
428 | speed1 = 0x47; | |
429 | ||
430 | if (speed < XFER_UDMA_0) { | |
431 | u8 ultra_enable = (unit) ? 0x7f : 0xf7; | |
432 | /* | |
433 | * clear "ultra enable" bit | |
434 | */ | |
435 | pci_read_config_byte(dev, m5229_udma, &tmpbyte); | |
436 | tmpbyte &= ultra_enable; | |
437 | pci_write_config_byte(dev, m5229_udma, tmpbyte); | |
438 | ||
439 | if (speed < XFER_SW_DMA_0) | |
21b82477 | 440 | (void) ali15x3_tune_pio(drive, speed - XFER_PIO_0); |
1da177e4 LT |
441 | } else { |
442 | pci_read_config_byte(dev, m5229_udma, &tmpbyte); | |
443 | tmpbyte &= (0x0f << ((1-unit) << 2)); | |
444 | /* | |
445 | * enable ultra dma and set timing | |
446 | */ | |
447 | tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2)); | |
448 | pci_write_config_byte(dev, m5229_udma, tmpbyte); | |
449 | if (speed >= XFER_UDMA_3) { | |
450 | pci_read_config_byte(dev, 0x4b, &tmpbyte); | |
451 | tmpbyte |= 1; | |
452 | pci_write_config_byte(dev, 0x4b, tmpbyte); | |
453 | } | |
454 | } | |
455 | return (ide_config_drive_speed(drive, speed)); | |
456 | } | |
457 | ||
458 | ||
459 | /** | |
460 | * config_chipset_for_dma - set up DMA mode | |
461 | * @drive: drive to configure for | |
462 | * | |
463 | * Place a drive into DMA mode and tune the chipset for | |
464 | * the selected speed. | |
465 | * | |
466 | * Returns true if DMA mode can be used | |
467 | */ | |
468 | ||
469 | static int config_chipset_for_dma (ide_drive_t *drive) | |
470 | { | |
2d5eaa6d | 471 | u8 speed = ide_max_dma_mode(drive); |
1da177e4 LT |
472 | |
473 | if (!(speed)) | |
474 | return 0; | |
475 | ||
476 | (void) ali15x3_tune_chipset(drive, speed); | |
477 | return ide_dma_enable(drive); | |
478 | } | |
479 | ||
480 | /** | |
481 | * ali15x3_config_drive_for_dma - configure for DMA | |
482 | * @drive: drive to configure | |
483 | * | |
484 | * Configure a drive for DMA operation. If DMA is not possible we | |
485 | * drop the drive into PIO mode instead. | |
1da177e4 | 486 | */ |
3608b5d7 | 487 | |
1da177e4 LT |
488 | static int ali15x3_config_drive_for_dma(ide_drive_t *drive) |
489 | { | |
490 | ide_hwif_t *hwif = HWIF(drive); | |
491 | struct hd_driveid *id = drive->id; | |
492 | ||
493 | if ((m5229_revision<=0x20) && (drive->media!=ide_disk)) | |
072cdcbb | 494 | goto ata_pio; |
1da177e4 LT |
495 | |
496 | drive->init_speed = 0; | |
497 | ||
498 | if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) { | |
499 | /* Consult the list of known "bad" drives */ | |
500 | if (__ide_dma_bad_drive(drive)) | |
501 | goto ata_pio; | |
502 | if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) { | |
503 | if (id->dma_ultra & hwif->ultra_mask) { | |
504 | /* Force if Capable UltraDMA */ | |
505 | int dma = config_chipset_for_dma(drive); | |
506 | if ((id->field_valid & 2) && !dma) | |
507 | goto try_dma_modes; | |
508 | } | |
509 | } else if (id->field_valid & 2) { | |
510 | try_dma_modes: | |
511 | if ((id->dma_mword & hwif->mwdma_mask) || | |
512 | (id->dma_1word & hwif->swdma_mask)) { | |
513 | /* Force if Capable regular DMA modes */ | |
514 | if (!config_chipset_for_dma(drive)) | |
072cdcbb | 515 | goto ata_pio; |
1da177e4 LT |
516 | } |
517 | } else if (__ide_dma_good_drive(drive) && | |
518 | (id->eide_dma_time < 150)) { | |
519 | /* Consult the list of known "good" drives */ | |
520 | if (!config_chipset_for_dma(drive)) | |
072cdcbb | 521 | goto ata_pio; |
1da177e4 LT |
522 | } else { |
523 | goto ata_pio; | |
524 | } | |
525 | } else { | |
526 | ata_pio: | |
527 | hwif->tuneproc(drive, 255); | |
3608b5d7 | 528 | return -1; |
1da177e4 | 529 | } |
3608b5d7 BZ |
530 | |
531 | return 0; | |
1da177e4 LT |
532 | } |
533 | ||
534 | /** | |
535 | * ali15x3_dma_setup - begin a DMA phase | |
536 | * @drive: target device | |
537 | * | |
538 | * Returns 1 if the DMA cannot be performed, zero on success. | |
539 | */ | |
540 | ||
541 | static int ali15x3_dma_setup(ide_drive_t *drive) | |
542 | { | |
543 | if (m5229_revision < 0xC2 && drive->media != ide_disk) { | |
544 | if (rq_data_dir(drive->hwif->hwgroup->rq)) | |
545 | return 1; /* try PIO instead of DMA */ | |
546 | } | |
547 | return ide_dma_setup(drive); | |
548 | } | |
549 | ||
550 | /** | |
551 | * init_chipset_ali15x3 - Initialise an ALi IDE controller | |
552 | * @dev: PCI device | |
553 | * @name: Name of the controller | |
554 | * | |
555 | * This function initializes the ALI IDE controller and where | |
556 | * appropriate also sets up the 1533 southbridge. | |
557 | */ | |
558 | ||
c2f12589 | 559 | static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name) |
1da177e4 LT |
560 | { |
561 | unsigned long flags; | |
562 | u8 tmpbyte; | |
b1489009 | 563 | struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0)); |
1da177e4 LT |
564 | |
565 | pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision); | |
566 | ||
b1489009 | 567 | isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); |
1da177e4 LT |
568 | |
569 | #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) | |
570 | if (!ali_proc) { | |
571 | ali_proc = 1; | |
572 | bmide_dev = dev; | |
573 | ide_pci_create_host_proc("ali", ali_get_info); | |
574 | } | |
575 | #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */ | |
576 | ||
577 | local_irq_save(flags); | |
578 | ||
579 | if (m5229_revision < 0xC2) { | |
580 | /* | |
581 | * revision 0x20 (1543-E, 1543-F) | |
582 | * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E) | |
583 | * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7 | |
584 | */ | |
585 | pci_read_config_byte(dev, 0x4b, &tmpbyte); | |
586 | /* | |
587 | * clear bit 7 | |
588 | */ | |
589 | pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); | |
b1489009 | 590 | goto out; |
1da177e4 LT |
591 | } |
592 | ||
593 | /* | |
594 | * 1543C-B?, 1535, 1535D, 1553 | |
595 | * Note 1: not all "motherboard" support this detection | |
596 | * Note 2: if no udma 66 device, the detection may "error". | |
597 | * but in this case, we will not set the device to | |
598 | * ultra 66, the detection result is not important | |
599 | */ | |
600 | ||
601 | /* | |
602 | * enable "Cable Detection", m5229, 0x4b, bit3 | |
603 | */ | |
604 | pci_read_config_byte(dev, 0x4b, &tmpbyte); | |
605 | pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08); | |
606 | ||
607 | /* | |
608 | * We should only tune the 1533 enable if we are using an ALi | |
609 | * North bridge. We might have no north found on some zany | |
610 | * box without a device at 0:0.0. The ALi bridge will be at | |
611 | * 0:0.0 so if we didn't find one we know what is cooking. | |
612 | */ | |
b1489009 AC |
613 | if (north && north->vendor != PCI_VENDOR_ID_AL) |
614 | goto out; | |
1da177e4 LT |
615 | |
616 | if (m5229_revision < 0xC5 && isa_dev) | |
617 | { | |
618 | /* | |
619 | * set south-bridge's enable bit, m1533, 0x79 | |
620 | */ | |
621 | ||
622 | pci_read_config_byte(isa_dev, 0x79, &tmpbyte); | |
623 | if (m5229_revision == 0xC2) { | |
624 | /* | |
625 | * 1543C-B0 (m1533, 0x79, bit 2) | |
626 | */ | |
627 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04); | |
628 | } else if (m5229_revision >= 0xC3) { | |
629 | /* | |
630 | * 1553/1535 (m1533, 0x79, bit 1) | |
631 | */ | |
632 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); | |
633 | } | |
634 | } | |
b1489009 AC |
635 | out: |
636 | pci_dev_put(north); | |
637 | pci_dev_put(isa_dev); | |
1da177e4 LT |
638 | local_irq_restore(flags); |
639 | return 0; | |
640 | } | |
641 | ||
642 | /** | |
643 | * ata66_ali15x3 - check for UDMA 66 support | |
644 | * @hwif: IDE interface | |
645 | * | |
646 | * This checks if the controller and the cable are capable | |
647 | * of UDMA66 transfers. It doesn't check the drives. | |
648 | * But see note 2 below! | |
649 | * | |
650 | * FIXME: frobs bits that are not defined on newer ALi devicea | |
651 | */ | |
652 | ||
c2f12589 | 653 | static unsigned int __devinit ata66_ali15x3 (ide_hwif_t *hwif) |
1da177e4 LT |
654 | { |
655 | struct pci_dev *dev = hwif->pci_dev; | |
656 | unsigned int ata66 = 0; | |
657 | u8 cable_80_pin[2] = { 0, 0 }; | |
658 | ||
659 | unsigned long flags; | |
660 | u8 tmpbyte; | |
661 | ||
662 | local_irq_save(flags); | |
663 | ||
664 | if (m5229_revision >= 0xC2) { | |
665 | /* | |
666 | * Ultra66 cable detection (from Host View) | |
667 | * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin | |
668 | */ | |
669 | pci_read_config_byte(dev, 0x4a, &tmpbyte); | |
670 | /* | |
671 | * 0x4a, bit0 is 0 => primary channel | |
672 | * has 80-pin (from host view) | |
673 | */ | |
674 | if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1; | |
675 | /* | |
676 | * 0x4a, bit1 is 0 => secondary channel | |
677 | * has 80-pin (from host view) | |
678 | */ | |
679 | if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1; | |
680 | /* | |
681 | * Allow ata66 if cable of current channel has 80 pins | |
682 | */ | |
683 | ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0]; | |
684 | } else { | |
685 | /* | |
686 | * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 | |
687 | */ | |
688 | pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); | |
689 | chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; | |
690 | } | |
691 | ||
692 | /* | |
693 | * CD_ROM DMA on (m5229, 0x53, bit0) | |
694 | * Enable this bit even if we want to use PIO | |
695 | * PIO FIFO off (m5229, 0x53, bit1) | |
696 | * The hardware will use 0x54h and 0x55h to control PIO FIFO | |
697 | * (Not on later devices it seems) | |
698 | * | |
699 | * 0x53 changes meaning on later revs - we must no touch | |
700 | * bit 1 on them. Need to check if 0x20 is the right break | |
701 | */ | |
702 | ||
703 | pci_read_config_byte(dev, 0x53, &tmpbyte); | |
704 | ||
705 | if(m5229_revision <= 0x20) | |
706 | tmpbyte = (tmpbyte & (~0x02)) | 0x01; | |
e11db063 | 707 | else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) |
0d8a95ef | 708 | tmpbyte |= 0x03; |
1da177e4 LT |
709 | else |
710 | tmpbyte |= 0x01; | |
711 | ||
712 | pci_write_config_byte(dev, 0x53, tmpbyte); | |
713 | ||
714 | local_irq_restore(flags); | |
715 | ||
716 | return(ata66); | |
717 | } | |
718 | ||
719 | /** | |
720 | * init_hwif_common_ali15x3 - Set up ALI IDE hardware | |
721 | * @hwif: IDE interface | |
722 | * | |
723 | * Initialize the IDE structure side of the ALi 15x3 driver. | |
724 | */ | |
725 | ||
c2f12589 | 726 | static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif) |
1da177e4 LT |
727 | { |
728 | hwif->autodma = 0; | |
729 | hwif->tuneproc = &ali15x3_tune_drive; | |
730 | hwif->speedproc = &ali15x3_tune_chipset; | |
2d5eaa6d | 731 | hwif->udma_filter = &ali_udma_filter; |
1da177e4 LT |
732 | |
733 | /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ | |
734 | hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0; | |
735 | ||
736 | if (!hwif->dma_base) { | |
737 | hwif->drives[0].autotune = 1; | |
738 | hwif->drives[1].autotune = 1; | |
739 | return; | |
740 | } | |
741 | ||
742 | hwif->atapi_dma = 1; | |
743 | ||
18137207 BZ |
744 | if (m5229_revision <= 0x20) |
745 | hwif->ultra_mask = 0x00; /* no udma */ | |
746 | else if (m5229_revision < 0xC2) | |
747 | hwif->ultra_mask = 0x07; /* udma0-2 */ | |
748 | else if (m5229_revision == 0xC2 || m5229_revision == 0xC3) | |
749 | hwif->ultra_mask = 0x1f; /* udma0-4 */ | |
750 | else if (m5229_revision == 0xC4) | |
751 | hwif->ultra_mask = 0x3f; /* udma0-5 */ | |
752 | else | |
753 | hwif->ultra_mask = 0x7f; /* udma0-6 */ | |
754 | ||
1da177e4 LT |
755 | hwif->mwdma_mask = 0x07; |
756 | hwif->swdma_mask = 0x07; | |
757 | ||
758 | if (m5229_revision >= 0x20) { | |
759 | /* | |
760 | * M1543C or newer for DMAing | |
761 | */ | |
762 | hwif->ide_dma_check = &ali15x3_config_drive_for_dma; | |
763 | hwif->dma_setup = &ali15x3_dma_setup; | |
764 | if (!noautodma) | |
765 | hwif->autodma = 1; | |
766 | if (!(hwif->udma_four)) | |
767 | hwif->udma_four = ata66_ali15x3(hwif); | |
768 | } | |
769 | hwif->drives[0].autodma = hwif->autodma; | |
770 | hwif->drives[1].autodma = hwif->autodma; | |
771 | } | |
772 | ||
773 | /** | |
774 | * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff | |
775 | * @hwif: interface to configure | |
776 | * | |
777 | * Obtain the IRQ tables for an ALi based IDE solution on the PC | |
778 | * class platforms. This part of the code isn't applicable to the | |
779 | * Sparc systems | |
780 | */ | |
781 | ||
c2f12589 | 782 | static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif) |
1da177e4 LT |
783 | { |
784 | u8 ideic, inmir; | |
785 | s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6, | |
786 | 1, 11, 0, 12, 0, 14, 0, 15 }; | |
787 | int irq = -1; | |
788 | ||
789 | if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229) | |
790 | hwif->irq = hwif->channel ? 15 : 14; | |
791 | ||
792 | if (isa_dev) { | |
793 | /* | |
794 | * read IDE interface control | |
795 | */ | |
796 | pci_read_config_byte(isa_dev, 0x58, &ideic); | |
797 | ||
798 | /* bit0, bit1 */ | |
799 | ideic = ideic & 0x03; | |
800 | ||
801 | /* get IRQ for IDE Controller */ | |
802 | if ((hwif->channel && ideic == 0x03) || | |
803 | (!hwif->channel && !ideic)) { | |
804 | /* | |
805 | * get SIRQ1 routing table | |
806 | */ | |
807 | pci_read_config_byte(isa_dev, 0x44, &inmir); | |
808 | inmir = inmir & 0x0f; | |
809 | irq = irq_routing_table[inmir]; | |
810 | } else if (hwif->channel && !(ideic & 0x01)) { | |
811 | /* | |
812 | * get SIRQ2 routing table | |
813 | */ | |
814 | pci_read_config_byte(isa_dev, 0x75, &inmir); | |
815 | inmir = inmir & 0x0f; | |
816 | irq = irq_routing_table[inmir]; | |
817 | } | |
818 | if(irq >= 0) | |
819 | hwif->irq = irq; | |
820 | } | |
821 | ||
822 | init_hwif_common_ali15x3(hwif); | |
823 | } | |
824 | ||
825 | /** | |
826 | * init_dma_ali15x3 - set up DMA on ALi15x3 | |
827 | * @hwif: IDE interface | |
828 | * @dmabase: DMA interface base PCI address | |
829 | * | |
830 | * Set up the DMA functionality on the ALi 15x3. For the ALi | |
831 | * controllers this is generic so we can let the generic code do | |
832 | * the actual work. | |
833 | */ | |
834 | ||
c2f12589 | 835 | static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase) |
1da177e4 LT |
836 | { |
837 | if (m5229_revision < 0x20) | |
838 | return; | |
0ecdca26 BZ |
839 | if (!hwif->channel) |
840 | outb(inb(dmabase + 2) & 0x60, dmabase + 2); | |
1da177e4 LT |
841 | ide_setup_dma(hwif, dmabase, 8); |
842 | } | |
843 | ||
844 | static ide_pci_device_t ali15x3_chipset __devinitdata = { | |
845 | .name = "ALI15X3", | |
846 | .init_chipset = init_chipset_ali15x3, | |
847 | .init_hwif = init_hwif_ali15x3, | |
848 | .init_dma = init_dma_ali15x3, | |
849 | .channels = 2, | |
850 | .autodma = AUTODMA, | |
851 | .bootable = ON_BOARD, | |
852 | }; | |
853 | ||
854 | /** | |
855 | * alim15x3_init_one - set up an ALi15x3 IDE controller | |
856 | * @dev: PCI device to set up | |
857 | * | |
858 | * Perform the actual set up for an ALi15x3 that has been found by the | |
859 | * hot plug layer. | |
860 | */ | |
861 | ||
862 | static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
863 | { | |
cc3f7ca5 HL |
864 | static struct pci_device_id ati_rs100[] = { |
865 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) }, | |
866 | { }, | |
867 | }; | |
868 | ||
1da177e4 LT |
869 | ide_pci_device_t *d = &ali15x3_chipset; |
870 | ||
cc3f7ca5 | 871 | if (pci_dev_present(ati_rs100)) |
2fefef18 | 872 | printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n"); |
1da177e4 LT |
873 | |
874 | #if defined(CONFIG_SPARC64) | |
875 | d->init_hwif = init_hwif_common_ali15x3; | |
876 | #endif /* CONFIG_SPARC64 */ | |
877 | return ide_setup_pci_device(dev, d); | |
878 | } | |
879 | ||
880 | ||
881 | static struct pci_device_id alim15x3_pci_tbl[] = { | |
882 | { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
883 | { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
884 | { 0, }, | |
885 | }; | |
886 | MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl); | |
887 | ||
888 | static struct pci_driver driver = { | |
889 | .name = "ALI15x3_IDE", | |
890 | .id_table = alim15x3_pci_tbl, | |
891 | .probe = alim15x3_init_one, | |
892 | }; | |
893 | ||
82ab1eec | 894 | static int __init ali15x3_ide_init(void) |
1da177e4 LT |
895 | { |
896 | return ide_pci_register_driver(&driver); | |
897 | } | |
898 | ||
899 | module_init(ali15x3_ide_init); | |
900 | ||
901 | MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox"); | |
902 | MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE"); | |
903 | MODULE_LICENSE("GPL"); |