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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004 | |
3 | * | |
4 | * Copyright (C) 2003 ATI Inc. <hyu@ati.com> | |
5 | * Copyright (C) 2004 Bartlomiej Zolnierkiewicz | |
6 | * | |
7 | */ | |
8 | ||
1da177e4 LT |
9 | #include <linux/types.h> |
10 | #include <linux/module.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/ioport.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/hdreg.h> | |
15 | #include <linux/ide.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/io.h> | |
20 | ||
21 | #define ATIIXP_IDE_PIO_TIMING 0x40 | |
22 | #define ATIIXP_IDE_MDMA_TIMING 0x44 | |
23 | #define ATIIXP_IDE_PIO_CONTROL 0x48 | |
24 | #define ATIIXP_IDE_PIO_MODE 0x4a | |
25 | #define ATIIXP_IDE_UDMA_CONTROL 0x54 | |
26 | #define ATIIXP_IDE_UDMA_MODE 0x56 | |
27 | ||
28 | typedef struct { | |
29 | u8 command_width; | |
30 | u8 recover_width; | |
31 | } atiixp_ide_timing; | |
32 | ||
33 | static atiixp_ide_timing pio_timing[] = { | |
34 | { 0x05, 0x0d }, | |
35 | { 0x04, 0x07 }, | |
36 | { 0x03, 0x04 }, | |
37 | { 0x02, 0x02 }, | |
38 | { 0x02, 0x00 }, | |
39 | }; | |
40 | ||
41 | static atiixp_ide_timing mdma_timing[] = { | |
42 | { 0x07, 0x07 }, | |
43 | { 0x02, 0x01 }, | |
44 | { 0x02, 0x00 }, | |
45 | }; | |
46 | ||
47 | static int save_mdma_mode[4]; | |
48 | ||
6c5f8cc3 A |
49 | static DEFINE_SPINLOCK(atiixp_lock); |
50 | ||
1da177e4 LT |
51 | /** |
52 | * atiixp_ratemask - compute rate mask for ATIIXP IDE | |
53 | * @drive: IDE drive to compute for | |
54 | * | |
55 | * Returns the available modes for the ATIIXP IDE controller. | |
56 | */ | |
57 | ||
58 | static u8 atiixp_ratemask(ide_drive_t *drive) | |
59 | { | |
60 | u8 mode = 3; | |
61 | ||
62 | if (!eighty_ninty_three(drive)) | |
63 | mode = min(mode, (u8)1); | |
64 | return mode; | |
65 | } | |
66 | ||
67 | /** | |
68 | * atiixp_dma_2_pio - return the PIO mode matching DMA | |
69 | * @xfer_rate: transfer speed | |
70 | * | |
71 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
72 | * mode requested by the controller. | |
73 | */ | |
74 | ||
75 | static u8 atiixp_dma_2_pio(u8 xfer_rate) { | |
76 | switch(xfer_rate) { | |
77 | case XFER_UDMA_6: | |
78 | case XFER_UDMA_5: | |
79 | case XFER_UDMA_4: | |
80 | case XFER_UDMA_3: | |
81 | case XFER_UDMA_2: | |
82 | case XFER_UDMA_1: | |
83 | case XFER_UDMA_0: | |
84 | case XFER_MW_DMA_2: | |
85 | case XFER_PIO_4: | |
86 | return 4; | |
87 | case XFER_MW_DMA_1: | |
88 | case XFER_PIO_3: | |
89 | return 3; | |
90 | case XFER_SW_DMA_2: | |
91 | case XFER_PIO_2: | |
92 | return 2; | |
93 | case XFER_MW_DMA_0: | |
94 | case XFER_SW_DMA_1: | |
95 | case XFER_SW_DMA_0: | |
96 | case XFER_PIO_1: | |
97 | case XFER_PIO_0: | |
98 | case XFER_PIO_SLOW: | |
99 | default: | |
100 | return 0; | |
101 | } | |
102 | } | |
103 | ||
104 | static int atiixp_ide_dma_host_on(ide_drive_t *drive) | |
105 | { | |
106 | struct pci_dev *dev = drive->hwif->pci_dev; | |
107 | unsigned long flags; | |
108 | u16 tmp16; | |
109 | ||
6c5f8cc3 | 110 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
111 | |
112 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
113 | if (save_mdma_mode[drive->dn]) | |
114 | tmp16 &= ~(1 << drive->dn); | |
115 | else | |
116 | tmp16 |= (1 << drive->dn); | |
117 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
118 | ||
6c5f8cc3 | 119 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
120 | |
121 | return __ide_dma_host_on(drive); | |
122 | } | |
123 | ||
124 | static int atiixp_ide_dma_host_off(ide_drive_t *drive) | |
125 | { | |
126 | struct pci_dev *dev = drive->hwif->pci_dev; | |
127 | unsigned long flags; | |
128 | u16 tmp16; | |
129 | ||
6c5f8cc3 | 130 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
131 | |
132 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
133 | tmp16 &= ~(1 << drive->dn); | |
134 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
135 | ||
6c5f8cc3 | 136 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
137 | |
138 | return __ide_dma_host_off(drive); | |
139 | } | |
140 | ||
141 | /** | |
142 | * atiixp_tune_drive - tune a drive attached to a ATIIXP | |
143 | * @drive: drive to tune | |
144 | * @pio: desired PIO mode | |
145 | * | |
146 | * Set the interface PIO mode. | |
147 | */ | |
148 | ||
149 | static void atiixp_tuneproc(ide_drive_t *drive, u8 pio) | |
150 | { | |
151 | struct pci_dev *dev = drive->hwif->pci_dev; | |
152 | unsigned long flags; | |
153 | int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8; | |
154 | u32 pio_timing_data; | |
155 | u16 pio_mode_data; | |
156 | ||
6c5f8cc3 | 157 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
158 | |
159 | pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); | |
160 | pio_mode_data &= ~(0x07 << (drive->dn * 4)); | |
161 | pio_mode_data |= (pio << (drive->dn * 4)); | |
162 | pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data); | |
163 | ||
164 | pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); | |
165 | pio_timing_data &= ~(0xff << timing_shift); | |
166 | pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) | | |
167 | (pio_timing[pio].command_width << (timing_shift + 4)); | |
168 | pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); | |
169 | ||
6c5f8cc3 | 170 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
171 | } |
172 | ||
173 | /** | |
174 | * atiixp_tune_chipset - tune a ATIIXP interface | |
175 | * @drive: IDE drive to tune | |
176 | * @xferspeed: speed to configure | |
177 | * | |
178 | * Set a ATIIXP interface channel to the desired speeds. This involves | |
179 | * requires the right timing data into the ATIIXP configuration space | |
180 | * then setting the drive parameters appropriately | |
181 | */ | |
182 | ||
183 | static int atiixp_speedproc(ide_drive_t *drive, u8 xferspeed) | |
184 | { | |
185 | struct pci_dev *dev = drive->hwif->pci_dev; | |
186 | unsigned long flags; | |
187 | int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8; | |
188 | u32 tmp32; | |
189 | u16 tmp16; | |
190 | u8 speed, pio; | |
191 | ||
192 | speed = ide_rate_filter(atiixp_ratemask(drive), xferspeed); | |
193 | ||
6c5f8cc3 | 194 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
195 | |
196 | save_mdma_mode[drive->dn] = 0; | |
197 | if (speed >= XFER_UDMA_0) { | |
198 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16); | |
199 | tmp16 &= ~(0x07 << (drive->dn * 4)); | |
200 | tmp16 |= ((speed & 0x07) << (drive->dn * 4)); | |
201 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16); | |
202 | } else { | |
203 | if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) { | |
204 | save_mdma_mode[drive->dn] = speed; | |
205 | pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32); | |
206 | tmp32 &= ~(0xff << timing_shift); | |
207 | tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) | | |
208 | (mdma_timing[speed & 0x03].command_width << (timing_shift + 4)); | |
209 | pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32); | |
210 | } | |
211 | } | |
212 | ||
6c5f8cc3 | 213 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
214 | |
215 | if (speed >= XFER_SW_DMA_0) | |
216 | pio = atiixp_dma_2_pio(speed); | |
217 | else | |
218 | pio = speed - XFER_PIO_0; | |
219 | ||
220 | atiixp_tuneproc(drive, pio); | |
221 | ||
222 | return ide_config_drive_speed(drive, speed); | |
223 | } | |
224 | ||
225 | /** | |
226 | * atiixp_config_drive_for_dma - configure drive for DMA | |
227 | * @drive: IDE drive to configure | |
228 | * | |
229 | * Set up a ATIIXP interface channel for the best available speed. | |
230 | * We prefer UDMA if it is available and then MWDMA. If DMA is | |
231 | * not available we switch to PIO and return 0. | |
232 | */ | |
233 | ||
234 | static int atiixp_config_drive_for_dma(ide_drive_t *drive) | |
235 | { | |
236 | u8 speed = ide_dma_speed(drive, atiixp_ratemask(drive)); | |
237 | ||
39baf8a7 BZ |
238 | if (!speed) |
239 | return 0; | |
1da177e4 LT |
240 | |
241 | (void) atiixp_speedproc(drive, speed); | |
242 | return ide_dma_enable(drive); | |
243 | } | |
244 | ||
245 | /** | |
246 | * atiixp_dma_check - set up an IDE device | |
247 | * @drive: IDE drive to configure | |
248 | * | |
249 | * Set up the ATIIXP interface for the best available speed on this | |
250 | * interface, preferring DMA to PIO. | |
251 | */ | |
252 | ||
253 | static int atiixp_dma_check(ide_drive_t *drive) | |
254 | { | |
255 | ide_hwif_t *hwif = HWIF(drive); | |
256 | struct hd_driveid *id = drive->id; | |
257 | u8 tspeed, speed; | |
258 | ||
259 | drive->init_speed = 0; | |
260 | ||
261 | if ((id->capability & 1) && drive->autodma) { | |
262 | ||
263 | if (ide_use_dma(drive)) { | |
264 | if (atiixp_config_drive_for_dma(drive)) | |
265 | return hwif->ide_dma_on(drive); | |
266 | } | |
267 | ||
268 | goto fast_ata_pio; | |
269 | ||
270 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
271 | fast_ata_pio: | |
272 | tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL); | |
273 | speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0; | |
274 | hwif->speedproc(drive, speed); | |
275 | return hwif->ide_dma_off_quietly(drive); | |
276 | } | |
277 | /* IORDY not supported */ | |
278 | return 0; | |
279 | } | |
280 | ||
281 | /** | |
282 | * init_hwif_atiixp - fill in the hwif for the ATIIXP | |
283 | * @hwif: IDE interface | |
284 | * | |
285 | * Set up the ide_hwif_t for the ATIIXP interface according to the | |
286 | * capabilities of the hardware. | |
287 | */ | |
288 | ||
289 | static void __devinit init_hwif_atiixp(ide_hwif_t *hwif) | |
290 | { | |
e5c073ff CH |
291 | u8 udma_mode = 0; |
292 | u8 ch = hwif->channel; | |
293 | struct pci_dev *pdev = hwif->pci_dev; | |
294 | ||
1da177e4 | 295 | if (!hwif->irq) |
e5c073ff | 296 | hwif->irq = ch ? 15 : 14; |
1da177e4 LT |
297 | |
298 | hwif->autodma = 0; | |
299 | hwif->tuneproc = &atiixp_tuneproc; | |
300 | hwif->speedproc = &atiixp_speedproc; | |
301 | hwif->drives[0].autotune = 1; | |
302 | hwif->drives[1].autotune = 1; | |
303 | ||
304 | if (!hwif->dma_base) | |
305 | return; | |
306 | ||
307 | hwif->atapi_dma = 1; | |
308 | hwif->ultra_mask = 0x3f; | |
309 | hwif->mwdma_mask = 0x06; | |
310 | hwif->swdma_mask = 0x04; | |
311 | ||
e5c073ff CH |
312 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode); |
313 | if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40) | |
314 | hwif->udma_four = 1; | |
315 | else | |
316 | hwif->udma_four = 0; | |
317 | ||
1da177e4 LT |
318 | hwif->ide_dma_host_on = &atiixp_ide_dma_host_on; |
319 | hwif->ide_dma_host_off = &atiixp_ide_dma_host_off; | |
320 | hwif->ide_dma_check = &atiixp_dma_check; | |
321 | if (!noautodma) | |
322 | hwif->autodma = 1; | |
323 | ||
324 | hwif->drives[1].autodma = hwif->autodma; | |
325 | hwif->drives[0].autodma = hwif->autodma; | |
326 | } | |
327 | ||
2b33b4dc | 328 | |
1da177e4 LT |
329 | static ide_pci_device_t atiixp_pci_info[] __devinitdata = { |
330 | { /* 0 */ | |
331 | .name = "ATIIXP", | |
332 | .init_hwif = init_hwif_atiixp, | |
333 | .channels = 2, | |
334 | .autodma = AUTODMA, | |
335 | .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}}, | |
336 | .bootable = ON_BOARD, | |
b25168df CH |
337 | },{ /* 1 */ |
338 | .name = "SB600_PATA", | |
339 | .init_hwif = init_hwif_atiixp, | |
340 | .channels = 1, | |
341 | .autodma = AUTODMA, | |
342 | .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}}, | |
343 | .bootable = ON_BOARD, | |
344 | }, | |
1da177e4 LT |
345 | }; |
346 | ||
347 | /** | |
348 | * atiixp_init_one - called when a ATIIXP is found | |
349 | * @dev: the atiixp device | |
350 | * @id: the matching pci id | |
351 | * | |
352 | * Called when the PCI registration layer (or the IDE initialization) | |
353 | * finds a device matching our IDE device tables. | |
354 | */ | |
355 | ||
356 | static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
357 | { | |
358 | return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]); | |
359 | } | |
360 | ||
361 | static struct pci_device_id atiixp_pci_tbl[] = { | |
362 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
363 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
364 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
b25168df | 365 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1da177e4 LT |
366 | { 0, }, |
367 | }; | |
368 | MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl); | |
369 | ||
370 | static struct pci_driver driver = { | |
371 | .name = "ATIIXP_IDE", | |
372 | .id_table = atiixp_pci_tbl, | |
373 | .probe = atiixp_init_one, | |
374 | }; | |
375 | ||
82ab1eec | 376 | static int __init atiixp_ide_init(void) |
1da177e4 LT |
377 | { |
378 | return ide_pci_register_driver(&driver); | |
379 | } | |
380 | ||
381 | module_init(atiixp_ide_init); | |
382 | ||
383 | MODULE_AUTHOR("HUI YU"); | |
384 | MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE"); | |
385 | MODULE_LICENSE("GPL"); |