[deliverable/linux.git] / drivers / ide / pci / atiixp.c

/*
 *  linux/drivers/ide/pci/atiixp.c	Version 0.01-bart2	Feb. 26, 2004
 *
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004 Bartlomiej Zolnierkiewicz
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

typedef struct {
	u8 command_width;
	u8 recover_width;
} atiixp_ide_timing;

static atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static int save_mdma_mode[4];

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_ratemask		-	compute rate mask for ATIIXP IDE
 *	@drive: IDE drive to compute for
 *
 *	Returns the available modes for the ATIIXP IDE controller.
 */

static u8 atiixp_ratemask(ide_drive_t *drive)
{
	u8 mode = 3;

	if (!eighty_ninty_three(drive))
		mode = min(mode, (u8)1);
	return mode;
}

/**
 *	atiixp_dma_2_pio		-	return the PIO mode matching DMA
 *	@xfer_rate: transfer speed
 *
 *	Returns the nearest equivalent PIO timing for the PIO or DMA
 *	mode requested by the controller.
 */

static u8 atiixp_dma_2_pio(u8 xfer_rate) {
	switch(xfer_rate) {
		case XFER_UDMA_6:
		case XFER_UDMA_5:
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:
		case XFER_PIO_4:
			return 4;
		case XFER_MW_DMA_1:
		case XFER_PIO_3:
			return 3;
		case XFER_SW_DMA_2:
		case XFER_PIO_2:
			return 2;
		case XFER_MW_DMA_0:
		case XFER_SW_DMA_1:
		case XFER_SW_DMA_0:
		case XFER_PIO_1:
		case XFER_PIO_0:
		case XFER_PIO_SLOW:
		default:
			return 0;
	}
}

static int atiixp_ide_dma_host_on(ide_drive_t *drive)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	u16 tmp16;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	if (save_mdma_mode[drive->dn])
		tmp16 &= ~(1 << drive->dn);
	else
		tmp16 |= (1 << drive->dn);
	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);

	spin_unlock_irqrestore(&atiixp_lock, flags);

	return __ide_dma_host_on(drive);
}

static void atiixp_dma_host_off(ide_drive_t *drive)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	u16 tmp16;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	tmp16 &= ~(1 << drive->dn);
	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);

	spin_unlock_irqrestore(&atiixp_lock, flags);

	ide_dma_host_off(drive);
}

/**
 *	atiixp_tune_drive		-	tune a drive attached to a ATIIXP
 *	@drive: drive to tune
 *	@pio: desired PIO mode
 *
 *	Set the interface PIO mode.
 */

static void atiixp_tuneproc(ide_drive_t *drive, u8 pio)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 pio_timing_data;
	u16 pio_mode_data;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_tune_chipset	-	tune a ATIIXP interface
 *	@drive: IDE drive to tune
 *	@xferspeed: speed to configure
 *
 *	Set a ATIIXP interface channel to the desired speeds. This involves
 *	requires the right timing data into the ATIIXP configuration space
 *	then setting the drive parameters appropriately
 */

static int atiixp_speedproc(ide_drive_t *drive, u8 xferspeed)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 tmp32;
	u16 tmp16;
	u8 speed, pio;

	speed = ide_rate_filter(atiixp_ratemask(drive), xferspeed);

	spin_lock_irqsave(&atiixp_lock, flags);

	save_mdma_mode[drive->dn] = 0;
	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
	} else {
		if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
			save_mdma_mode[drive->dn] = speed;
			pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
			tmp32 &= ~(0xff << timing_shift);
			tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) |
				(mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
			pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
		}
	}

	spin_unlock_irqrestore(&atiixp_lock, flags);

	if (speed >= XFER_SW_DMA_0)
		pio = atiixp_dma_2_pio(speed);
	else
		pio = speed - XFER_PIO_0;

	atiixp_tuneproc(drive, pio);

	return ide_config_drive_speed(drive, speed);
}

/**
 *	atiixp_config_drive_for_dma	-	configure drive for DMA
 *	@drive: IDE drive to configure
 *
 *	Set up a ATIIXP interface channel for the best available speed.
 *	We prefer UDMA if it is available and then MWDMA. If DMA is
 *	not available we switch to PIO and return 0.
 */

static int atiixp_config_drive_for_dma(ide_drive_t *drive)
{
	u8 speed = ide_dma_speed(drive, atiixp_ratemask(drive));

	if (!speed)
		return 0;

	(void) atiixp_speedproc(drive, speed);
	return ide_dma_enable(drive);
}

/**
 *	atiixp_dma_check	-	set up an IDE device
 *	@drive: IDE drive to configure
 *
 *	Set up the ATIIXP interface for the best available speed on this
 *	interface, preferring DMA to PIO.
 */

static int atiixp_dma_check(ide_drive_t *drive)
{
	u8 tspeed, speed;

	drive->init_speed = 0;

	if (ide_use_dma(drive) && atiixp_config_drive_for_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive)) {
		tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
		speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0;
		atiixp_speedproc(drive, speed);
	}

	return -1;
}

/**
 *	init_hwif_atiixp		-	fill in the hwif for the ATIIXP
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the ATIIXP interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
{
	u8 udma_mode = 0;
	u8 ch = hwif->channel;
	struct pci_dev *pdev = hwif->pci_dev;

	if (!hwif->irq)
		hwif->irq = ch ? 15 : 14;

	hwif->autodma = 0;
	hwif->tuneproc = &atiixp_tuneproc;
	hwif->speedproc = &atiixp_speedproc;
	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x3f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		hwif->udma_four = 1;
	else
		hwif->udma_four = 0;

	hwif->ide_dma_host_on = &atiixp_ide_dma_host_on;
	hwif->dma_host_off = &atiixp_dma_host_off;
	hwif->ide_dma_check = &atiixp_dma_check;
	if (!noautodma)
		hwif->autodma = 1;

	hwif->drives[1].autodma = hwif->autodma;
	hwif->drives[0].autodma = hwif->autodma;
}


static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
	{	/* 0 */
		.name		= "ATIIXP",
		.init_hwif	= init_hwif_atiixp,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.bootable	= ON_BOARD,
	},{	/* 1 */
		.name		= "SB600_PATA",
		.init_hwif	= init_hwif_atiixp,
		.channels	= 1,
		.autodma	= AUTODMA,
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 		.bootable	= ON_BOARD,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
}

static struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(atiixp_ide_init);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
	3	*
	4	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
	5	* Copyright (C) 2004 Bartlomiej Zolnierkiewicz
	6	*
	7	*/
	8
1da177e4 LT	9	#include <linux/types.h>
	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/ioport.h>
	13	#include <linux/pci.h>
	14	#include <linux/hdreg.h>
	15	#include <linux/ide.h>
	16	#include <linux/delay.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
	21	#define ATIIXP_IDE_PIO_TIMING 0x40
	22	#define ATIIXP_IDE_MDMA_TIMING 0x44
	23	#define ATIIXP_IDE_PIO_CONTROL 0x48
	24	#define ATIIXP_IDE_PIO_MODE 0x4a
	25	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	26	#define ATIIXP_IDE_UDMA_MODE 0x56
	27
	28	typedef struct {
	29	u8 command_width;
	30	u8 recover_width;
	31	} atiixp_ide_timing;
	32
	33	static atiixp_ide_timing pio_timing[] = {
	34	{ 0x05, 0x0d },
	35	{ 0x04, 0x07 },
	36	{ 0x03, 0x04 },
	37	{ 0x02, 0x02 },
	38	{ 0x02, 0x00 },
	39	};
	40
	41	static atiixp_ide_timing mdma_timing[] = {
	42	{ 0x07, 0x07 },
	43	{ 0x02, 0x01 },
	44	{ 0x02, 0x00 },
	45	};
	46
	47	static int save_mdma_mode[4];
	48
6c5f8cc3 A	49	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 A	50
1da177e4 LT	51	/**
	52	* atiixp_ratemask - compute rate mask for ATIIXP IDE
	53	* @drive: IDE drive to compute for
	54	*
	55	* Returns the available modes for the ATIIXP IDE controller.
	56	*/
	57
	58	static u8 atiixp_ratemask(ide_drive_t *drive)
	59	{
	60	u8 mode = 3;
	61
	62	if (!eighty_ninty_three(drive))
	63	mode = min(mode, (u8)1);
	64	return mode;
	65	}
	66
	67	/**
	68	* atiixp_dma_2_pio - return the PIO mode matching DMA
	69	* @xfer_rate: transfer speed
	70	*
	71	* Returns the nearest equivalent PIO timing for the PIO or DMA
	72	* mode requested by the controller.
	73	*/
	74
	75	static u8 atiixp_dma_2_pio(u8 xfer_rate) {
	76	switch(xfer_rate) {
	77	case XFER_UDMA_6:
	78	case XFER_UDMA_5:
	79	case XFER_UDMA_4:
	80	case XFER_UDMA_3:
	81	case XFER_UDMA_2:
	82	case XFER_UDMA_1:
	83	case XFER_UDMA_0:
	84	case XFER_MW_DMA_2:
	85	case XFER_PIO_4:
	86	return 4;
	87	case XFER_MW_DMA_1:
	88	case XFER_PIO_3:
	89	return 3;
	90	case XFER_SW_DMA_2:
	91	case XFER_PIO_2:
	92	return 2;
	93	case XFER_MW_DMA_0:
	94	case XFER_SW_DMA_1:
	95	case XFER_SW_DMA_0:
	96	case XFER_PIO_1:
	97	case XFER_PIO_0:
	98	case XFER_PIO_SLOW:
	99	default:
	100	return 0;
	101	}
	102	}
	103
	104	static int atiixp_ide_dma_host_on(ide_drive_t *drive)
	105	{
	106	struct pci_dev *dev = drive->hwif->pci_dev;
	107	unsigned long flags;
	108	u16 tmp16;
	109
6c5f8cc3	110	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	111
	112	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	113	if (save_mdma_mode[drive->dn])
	114	tmp16 &= ~(1 << drive->dn);
	115	else
	116	tmp16 \|= (1 << drive->dn);
	117	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	118
6c5f8cc3	119	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	120
	121	return __ide_dma_host_on(drive);
	122	}
	123
7469aaf6	124	static void atiixp_dma_host_off(ide_drive_t *drive)
1da177e4 LT	125	{
	126	struct pci_dev *dev = drive->hwif->pci_dev;
	127	unsigned long flags;
	128	u16 tmp16;
	129
6c5f8cc3	130	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	131
	132	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	133	tmp16 &= ~(1 << drive->dn);
	134	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	135
6c5f8cc3	136	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4	137
7469aaf6	138	ide_dma_host_off(drive);
1da177e4 LT	139	}
	140
	141	/**
	142	* atiixp_tune_drive - tune a drive attached to a ATIIXP
	143	* @drive: drive to tune
	144	* @pio: desired PIO mode
	145	*
	146	* Set the interface PIO mode.
	147	*/
	148
	149	static void atiixp_tuneproc(ide_drive_t *drive, u8 pio)
	150	{
	151	struct pci_dev *dev = drive->hwif->pci_dev;
	152	unsigned long flags;
	153	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	154	u32 pio_timing_data;
	155	u16 pio_mode_data;
	156
6c5f8cc3	157	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	158
	159	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	160	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	161	pio_mode_data \|= (pio << (drive->dn * 4));
	162	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	163
	164	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	165	pio_timing_data &= ~(0xff << timing_shift);
	166	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	167	(pio_timing[pio].command_width << (timing_shift + 4));
	168	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	169
6c5f8cc3	170	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	171	}
	172
	173	/**
	174	* atiixp_tune_chipset - tune a ATIIXP interface
	175	* @drive: IDE drive to tune
	176	* @xferspeed: speed to configure
	177	*
	178	* Set a ATIIXP interface channel to the desired speeds. This involves
	179	* requires the right timing data into the ATIIXP configuration space
	180	* then setting the drive parameters appropriately
	181	*/
	182
	183	static int atiixp_speedproc(ide_drive_t *drive, u8 xferspeed)
	184	{
	185	struct pci_dev *dev = drive->hwif->pci_dev;
	186	unsigned long flags;
	187	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	188	u32 tmp32;
	189	u16 tmp16;
	190	u8 speed, pio;
	191
	192	speed = ide_rate_filter(atiixp_ratemask(drive), xferspeed);
	193
6c5f8cc3	194	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	195
	196	save_mdma_mode[drive->dn] = 0;
	197	if (speed >= XFER_UDMA_0) {
	198	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	199	tmp16 &= ~(0x07 << (drive->dn * 4));
	200	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	201	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
	202	} else {
	203	if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
	204	save_mdma_mode[drive->dn] = speed;
	205	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	206	tmp32 &= ~(0xff << timing_shift);
	207	tmp32 \|= (mdma_timing[speed & 0x03].recover_width << timing_shift) \|
	208	(mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
	209	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	210	}
	211	}
	212
6c5f8cc3	213	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	214
	215	if (speed >= XFER_SW_DMA_0)
	216	pio = atiixp_dma_2_pio(speed);
	217	else
	218	pio = speed - XFER_PIO_0;
	219
	220	atiixp_tuneproc(drive, pio);
	221
	222	return ide_config_drive_speed(drive, speed);
	223	}
	224
	225	/**
	226	* atiixp_config_drive_for_dma - configure drive for DMA
	227	* @drive: IDE drive to configure
	228	*
	229	* Set up a ATIIXP interface channel for the best available speed.
	230	* We prefer UDMA if it is available and then MWDMA. If DMA is
	231	* not available we switch to PIO and return 0.
	232	*/
	233
	234	static int atiixp_config_drive_for_dma(ide_drive_t *drive)
	235	{
	236	u8 speed = ide_dma_speed(drive, atiixp_ratemask(drive));
	237
39baf8a7 BZ	238	if (!speed)
39baf8a7 BZ	239	return 0;
1da177e4 LT	240
	241	(void) atiixp_speedproc(drive, speed);
	242	return ide_dma_enable(drive);
	243	}
	244
	245	/**
	246	* atiixp_dma_check - set up an IDE device
	247	* @drive: IDE drive to configure
	248	*
	249	* Set up the ATIIXP interface for the best available speed on this
	250	* interface, preferring DMA to PIO.
	251	*/
	252
	253	static int atiixp_dma_check(ide_drive_t *drive)
	254	{
1da177e4 LT	255	u8 tspeed, speed;
	256
	257	drive->init_speed = 0;
	258
7569e8dc	259	if (ide_use_dma(drive) && atiixp_config_drive_for_dma(drive))
3608b5d7	260	return 0;
1da177e4	261
7569e8dc	262	if (ide_use_fast_pio(drive)) {
1da177e4 LT	263	tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
1da177e4 LT	264	speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0;
3608b5d7	265	atiixp_speedproc(drive, speed);
1da177e4	266	}
d8f4469d	267
3608b5d7	268	return -1;
1da177e4 LT	269	}
	270
	271	/**
	272	* init_hwif_atiixp - fill in the hwif for the ATIIXP
	273	* @hwif: IDE interface
	274	*
	275	* Set up the ide_hwif_t for the ATIIXP interface according to the
	276	* capabilities of the hardware.
	277	*/
	278
	279	static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
	280	{
e5c073ff CH	281	u8 udma_mode = 0;
	282	u8 ch = hwif->channel;
	283	struct pci_dev *pdev = hwif->pci_dev;
	284
1da177e4	285	if (!hwif->irq)
e5c073ff	286	hwif->irq = ch ? 15 : 14;
1da177e4 LT	287
	288	hwif->autodma = 0;
	289	hwif->tuneproc = &atiixp_tuneproc;
	290	hwif->speedproc = &atiixp_speedproc;
	291	hwif->drives[0].autotune = 1;
	292	hwif->drives[1].autotune = 1;
	293
	294	if (!hwif->dma_base)
	295	return;
	296
	297	hwif->atapi_dma = 1;
	298	hwif->ultra_mask = 0x3f;
	299	hwif->mwdma_mask = 0x06;
	300	hwif->swdma_mask = 0x04;
	301
e5c073ff CH	302	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
	303	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
	304	hwif->udma_four = 1;
	305	else
	306	hwif->udma_four = 0;
	307
1da177e4	308	hwif->ide_dma_host_on = &atiixp_ide_dma_host_on;
7469aaf6	309	hwif->dma_host_off = &atiixp_dma_host_off;
1da177e4 LT	310	hwif->ide_dma_check = &atiixp_dma_check;
	311	if (!noautodma)
	312	hwif->autodma = 1;
	313
	314	hwif->drives[1].autodma = hwif->autodma;
	315	hwif->drives[0].autodma = hwif->autodma;
	316	}
	317
2b33b4dc	318
1da177e4 LT	319	static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
	320	{ /* 0 */
	321	.name = "ATIIXP",
	322	.init_hwif = init_hwif_atiixp,
	323	.channels = 2,
	324	.autodma = AUTODMA,
	325	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
	326	.bootable = ON_BOARD,
b25168df CH	327	},{ /* 1 */
	328	.name = "SB600_PATA",
	329	.init_hwif = init_hwif_atiixp,
	330	.channels = 1,
	331	.autodma = AUTODMA,
	332	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
	333	.bootable = ON_BOARD,
	334	},
1da177e4 LT	335	};
	336
	337	/**
	338	* atiixp_init_one - called when a ATIIXP is found
	339	* @dev: the atiixp device
	340	* @id: the matching pci id
	341	*
	342	* Called when the PCI registration layer (or the IDE initialization)
	343	* finds a device matching our IDE device tables.
	344	*/
	345
	346	static int __devinit atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
	347	{
	348	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
	349	}
	350
	351	static struct pci_device_id atiixp_pci_tbl[] = {
	352	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	353	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	354	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
b25168df	355	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1da177e4 LT	356	{ 0, },
	357	};
	358	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	359
	360	static struct pci_driver driver = {
	361	.name = "ATIIXP_IDE",
	362	.id_table = atiixp_pci_tbl,
	363	.probe = atiixp_init_one,
	364	};
	365
82ab1eec	366	static int __init atiixp_ide_init(void)
1da177e4 LT	367	{
	368	return ide_pci_register_driver(&driver);
	369	}
	370
	371	module_init(atiixp_ide_init);
	372
	373	MODULE_AUTHOR("HUI YU");
	374	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	375	MODULE_LICENSE("GPL");