Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
485efc6c | 2 | * linux/drivers/ide/pci/atiixp.c Version 0.02 Jun 16 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 ATI Inc. <hyu@ati.com> | |
485efc6c | 5 | * Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | */ |
7 | ||
1da177e4 LT |
8 | #include <linux/types.h> |
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/ioport.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/hdreg.h> | |
14 | #include <linux/ide.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/init.h> | |
17 | ||
18 | #include <asm/io.h> | |
19 | ||
20 | #define ATIIXP_IDE_PIO_TIMING 0x40 | |
21 | #define ATIIXP_IDE_MDMA_TIMING 0x44 | |
22 | #define ATIIXP_IDE_PIO_CONTROL 0x48 | |
23 | #define ATIIXP_IDE_PIO_MODE 0x4a | |
24 | #define ATIIXP_IDE_UDMA_CONTROL 0x54 | |
25 | #define ATIIXP_IDE_UDMA_MODE 0x56 | |
26 | ||
27 | typedef struct { | |
28 | u8 command_width; | |
29 | u8 recover_width; | |
30 | } atiixp_ide_timing; | |
31 | ||
32 | static atiixp_ide_timing pio_timing[] = { | |
33 | { 0x05, 0x0d }, | |
34 | { 0x04, 0x07 }, | |
35 | { 0x03, 0x04 }, | |
36 | { 0x02, 0x02 }, | |
37 | { 0x02, 0x00 }, | |
38 | }; | |
39 | ||
40 | static atiixp_ide_timing mdma_timing[] = { | |
41 | { 0x07, 0x07 }, | |
42 | { 0x02, 0x01 }, | |
43 | { 0x02, 0x00 }, | |
44 | }; | |
45 | ||
46 | static int save_mdma_mode[4]; | |
47 | ||
6c5f8cc3 A |
48 | static DEFINE_SPINLOCK(atiixp_lock); |
49 | ||
1da177e4 LT |
50 | /** |
51 | * atiixp_dma_2_pio - return the PIO mode matching DMA | |
52 | * @xfer_rate: transfer speed | |
53 | * | |
54 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
55 | * mode requested by the controller. | |
56 | */ | |
57 | ||
58 | static u8 atiixp_dma_2_pio(u8 xfer_rate) { | |
59 | switch(xfer_rate) { | |
60 | case XFER_UDMA_6: | |
61 | case XFER_UDMA_5: | |
62 | case XFER_UDMA_4: | |
63 | case XFER_UDMA_3: | |
64 | case XFER_UDMA_2: | |
65 | case XFER_UDMA_1: | |
66 | case XFER_UDMA_0: | |
67 | case XFER_MW_DMA_2: | |
68 | case XFER_PIO_4: | |
69 | return 4; | |
70 | case XFER_MW_DMA_1: | |
71 | case XFER_PIO_3: | |
72 | return 3; | |
73 | case XFER_SW_DMA_2: | |
74 | case XFER_PIO_2: | |
75 | return 2; | |
76 | case XFER_MW_DMA_0: | |
77 | case XFER_SW_DMA_1: | |
78 | case XFER_SW_DMA_0: | |
79 | case XFER_PIO_1: | |
80 | case XFER_PIO_0: | |
81 | case XFER_PIO_SLOW: | |
82 | default: | |
83 | return 0; | |
84 | } | |
85 | } | |
86 | ||
ccf35289 | 87 | static void atiixp_dma_host_on(ide_drive_t *drive) |
1da177e4 LT |
88 | { |
89 | struct pci_dev *dev = drive->hwif->pci_dev; | |
90 | unsigned long flags; | |
91 | u16 tmp16; | |
92 | ||
6c5f8cc3 | 93 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
94 | |
95 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
96 | if (save_mdma_mode[drive->dn]) | |
97 | tmp16 &= ~(1 << drive->dn); | |
98 | else | |
99 | tmp16 |= (1 << drive->dn); | |
100 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
101 | ||
6c5f8cc3 | 102 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 | 103 | |
ccf35289 | 104 | ide_dma_host_on(drive); |
1da177e4 LT |
105 | } |
106 | ||
7469aaf6 | 107 | static void atiixp_dma_host_off(ide_drive_t *drive) |
1da177e4 LT |
108 | { |
109 | struct pci_dev *dev = drive->hwif->pci_dev; | |
110 | unsigned long flags; | |
111 | u16 tmp16; | |
112 | ||
6c5f8cc3 | 113 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
114 | |
115 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
116 | tmp16 &= ~(1 << drive->dn); | |
117 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
118 | ||
6c5f8cc3 | 119 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 | 120 | |
7469aaf6 | 121 | ide_dma_host_off(drive); |
1da177e4 LT |
122 | } |
123 | ||
124 | /** | |
88b2b32b BZ |
125 | * atiixp_set_pio_mode - set host controller for PIO mode |
126 | * @drive: drive | |
127 | * @pio: PIO mode number | |
1da177e4 LT |
128 | * |
129 | * Set the interface PIO mode. | |
130 | */ | |
131 | ||
88b2b32b | 132 | static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
133 | { |
134 | struct pci_dev *dev = drive->hwif->pci_dev; | |
135 | unsigned long flags; | |
136 | int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8; | |
137 | u32 pio_timing_data; | |
138 | u16 pio_mode_data; | |
139 | ||
6c5f8cc3 | 140 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
141 | |
142 | pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); | |
143 | pio_mode_data &= ~(0x07 << (drive->dn * 4)); | |
144 | pio_mode_data |= (pio << (drive->dn * 4)); | |
145 | pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data); | |
146 | ||
147 | pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); | |
148 | pio_timing_data &= ~(0xff << timing_shift); | |
149 | pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) | | |
150 | (pio_timing[pio].command_width << (timing_shift + 4)); | |
151 | pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); | |
152 | ||
6c5f8cc3 | 153 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
154 | } |
155 | ||
156 | /** | |
88b2b32b BZ |
157 | * atiixp_set_dma_mode - set host controller for DMA mode |
158 | * @drive: drive | |
159 | * @speed: DMA mode | |
1da177e4 | 160 | * |
88b2b32b BZ |
161 | * Set a ATIIXP host controller to the desired DMA mode. This involves |
162 | * programming the right timing data into the PCI configuration space. | |
1da177e4 LT |
163 | */ |
164 | ||
88b2b32b | 165 | static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
166 | { |
167 | struct pci_dev *dev = drive->hwif->pci_dev; | |
168 | unsigned long flags; | |
169 | int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8; | |
170 | u32 tmp32; | |
171 | u16 tmp16; | |
f212ff28 | 172 | u8 pio; |
1da177e4 | 173 | |
6c5f8cc3 | 174 | spin_lock_irqsave(&atiixp_lock, flags); |
1da177e4 LT |
175 | |
176 | save_mdma_mode[drive->dn] = 0; | |
177 | if (speed >= XFER_UDMA_0) { | |
178 | pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16); | |
179 | tmp16 &= ~(0x07 << (drive->dn * 4)); | |
180 | tmp16 |= ((speed & 0x07) << (drive->dn * 4)); | |
181 | pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16); | |
182 | } else { | |
183 | if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) { | |
184 | save_mdma_mode[drive->dn] = speed; | |
185 | pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32); | |
186 | tmp32 &= ~(0xff << timing_shift); | |
187 | tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) | | |
188 | (mdma_timing[speed & 0x03].command_width << (timing_shift + 4)); | |
189 | pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32); | |
190 | } | |
191 | } | |
192 | ||
6c5f8cc3 | 193 | spin_unlock_irqrestore(&atiixp_lock, flags); |
1da177e4 LT |
194 | |
195 | if (speed >= XFER_SW_DMA_0) | |
196 | pio = atiixp_dma_2_pio(speed); | |
197 | else | |
198 | pio = speed - XFER_PIO_0; | |
199 | ||
88b2b32b | 200 | atiixp_set_pio_mode(drive, pio); |
1da177e4 LT |
201 | } |
202 | ||
1da177e4 LT |
203 | /** |
204 | * atiixp_dma_check - set up an IDE device | |
205 | * @drive: IDE drive to configure | |
206 | * | |
207 | * Set up the ATIIXP interface for the best available speed on this | |
208 | * interface, preferring DMA to PIO. | |
209 | */ | |
210 | ||
211 | static int atiixp_dma_check(ide_drive_t *drive) | |
212 | { | |
1da177e4 LT |
213 | drive->init_speed = 0; |
214 | ||
29e744d0 | 215 | if (ide_tune_dma(drive)) |
3608b5d7 | 216 | return 0; |
1da177e4 | 217 | |
485efc6c | 218 | if (ide_use_fast_pio(drive)) |
26bcb879 | 219 | ide_set_max_pio(drive); |
d8f4469d | 220 | |
3608b5d7 | 221 | return -1; |
1da177e4 LT |
222 | } |
223 | ||
224 | /** | |
225 | * init_hwif_atiixp - fill in the hwif for the ATIIXP | |
226 | * @hwif: IDE interface | |
227 | * | |
228 | * Set up the ide_hwif_t for the ATIIXP interface according to the | |
229 | * capabilities of the hardware. | |
230 | */ | |
231 | ||
232 | static void __devinit init_hwif_atiixp(ide_hwif_t *hwif) | |
233 | { | |
e5c073ff CH |
234 | u8 udma_mode = 0; |
235 | u8 ch = hwif->channel; | |
236 | struct pci_dev *pdev = hwif->pci_dev; | |
237 | ||
1da177e4 | 238 | if (!hwif->irq) |
e5c073ff | 239 | hwif->irq = ch ? 15 : 14; |
1da177e4 LT |
240 | |
241 | hwif->autodma = 0; | |
26bcb879 | 242 | hwif->set_pio_mode = &atiixp_set_pio_mode; |
88b2b32b | 243 | hwif->set_dma_mode = &atiixp_set_dma_mode; |
1da177e4 LT |
244 | hwif->drives[0].autotune = 1; |
245 | hwif->drives[1].autotune = 1; | |
246 | ||
247 | if (!hwif->dma_base) | |
248 | return; | |
249 | ||
250 | hwif->atapi_dma = 1; | |
251 | hwif->ultra_mask = 0x3f; | |
252 | hwif->mwdma_mask = 0x06; | |
253 | hwif->swdma_mask = 0x04; | |
254 | ||
e5c073ff | 255 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode); |
49521f97 | 256 | |
e5c073ff | 257 | if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40) |
49521f97 | 258 | hwif->cbl = ATA_CBL_PATA80; |
e5c073ff | 259 | else |
49521f97 | 260 | hwif->cbl = ATA_CBL_PATA40; |
e5c073ff | 261 | |
ccf35289 | 262 | hwif->dma_host_on = &atiixp_dma_host_on; |
7469aaf6 | 263 | hwif->dma_host_off = &atiixp_dma_host_off; |
1da177e4 LT |
264 | hwif->ide_dma_check = &atiixp_dma_check; |
265 | if (!noautodma) | |
266 | hwif->autodma = 1; | |
267 | ||
268 | hwif->drives[1].autodma = hwif->autodma; | |
269 | hwif->drives[0].autodma = hwif->autodma; | |
270 | } | |
271 | ||
2b33b4dc | 272 | |
1da177e4 LT |
273 | static ide_pci_device_t atiixp_pci_info[] __devinitdata = { |
274 | { /* 0 */ | |
275 | .name = "ATIIXP", | |
276 | .init_hwif = init_hwif_atiixp, | |
1da177e4 LT |
277 | .autodma = AUTODMA, |
278 | .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}}, | |
279 | .bootable = ON_BOARD, | |
4099d143 | 280 | .pio_mask = ATA_PIO4, |
b25168df CH |
281 | },{ /* 1 */ |
282 | .name = "SB600_PATA", | |
283 | .init_hwif = init_hwif_atiixp, | |
b25168df CH |
284 | .autodma = AUTODMA, |
285 | .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}}, | |
286 | .bootable = ON_BOARD, | |
a5d8c5c8 | 287 | .host_flags = IDE_HFLAG_SINGLE, |
4099d143 | 288 | .pio_mask = ATA_PIO4, |
b25168df | 289 | }, |
1da177e4 LT |
290 | }; |
291 | ||
292 | /** | |
293 | * atiixp_init_one - called when a ATIIXP is found | |
294 | * @dev: the atiixp device | |
295 | * @id: the matching pci id | |
296 | * | |
297 | * Called when the PCI registration layer (or the IDE initialization) | |
298 | * finds a device matching our IDE device tables. | |
299 | */ | |
300 | ||
301 | static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
302 | { | |
303 | return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]); | |
304 | } | |
305 | ||
306 | static struct pci_device_id atiixp_pci_tbl[] = { | |
307 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
308 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
309 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
b25168df | 310 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
7cfa7168 | 311 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 LT |
312 | { 0, }, |
313 | }; | |
314 | MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl); | |
315 | ||
316 | static struct pci_driver driver = { | |
317 | .name = "ATIIXP_IDE", | |
318 | .id_table = atiixp_pci_tbl, | |
319 | .probe = atiixp_init_one, | |
320 | }; | |
321 | ||
82ab1eec | 322 | static int __init atiixp_ide_init(void) |
1da177e4 LT |
323 | { |
324 | return ide_pci_register_driver(&driver); | |
325 | } | |
326 | ||
327 | module_init(atiixp_ide_init); | |
328 | ||
329 | MODULE_AUTHOR("HUI YU"); | |
330 | MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE"); | |
331 | MODULE_LICENSE("GPL"); |