[deliverable/linux.git] / drivers / ide / pci / cy82c693.c

/*
 *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
 *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
 *
 * CYPRESS CY82C693 chipset IDE controller
 *
 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
 * Writing the driver was quite simple, since most of the job is
 * done by the generic pci-ide support.
 * The hard part was finding the CY82C693's datasheet on Cypress's
 * web page :-(. But Altavista solved this problem :-).
 *
 *
 * Notes:
 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
 *   a large and fast disk - the results look great, so I'd say the
 *   driver is working fine :-)
 *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
 * - this is my first linux driver, so there's probably a lot  of room
 *   for optimizations and bug fixing, so feel free to do it.
 * - if using PIO mode it's a good idea to set the PIO mode and
 *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
 * - I had some problems with my IBM DHEA with PIO modes < 2
 *   (lost interrupts) ?????
 * - first tests with DMA look okay, they seem to work, but there is a
 *   problem with sound - the BusMaster IDE TimeOut should fixed this
 *
 * Ancient History:
 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
 * ASK@1999-01-23: v0.33 made a few minor code clean ups
 *                       removed DMA clock speed setting by default
 *                       added boot message
 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
 *                       added support to set DMA Controller Clock Speed
 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
 *                       on some drives.
 * ASK@1998-10-29: v0.3 added support to set DMA modes
 * ASK@1998-10-28: v0.2 added support to set PIO modes
 * ASK@1998-10-27: v0.1 first version - chipset detection
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

/* the current version */
#define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"

/*
 *	The following are used to debug the driver.
 */
#define CY82C693_DEBUG_LOGS	0
#define CY82C693_DEBUG_INFO	0

/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
#undef CY82C693_SETDMA_CLOCK

/*
 *	NOTE: the value for busmaster timeout is tricky and I got it by
 *	trial and error!  By using a to low value will cause DMA timeouts
 *	and drop IDE performance, and by using a to high value will cause
 *	audio playback to scatter.
 *	If you know a better value or how to calc it, please let me know.
 */

/* twice the value written in cy82c693ub datasheet */
#define BUSMASTER_TIMEOUT	0x50
/*
 * the value above was tested on my machine and it seems to work okay
 */

/* here are the offset definitions for the registers */
#define CY82_IDE_CMDREG		0x04
#define CY82_IDE_ADDRSETUP	0x48
#define CY82_IDE_MASTER_IOR	0x4C
#define CY82_IDE_MASTER_IOW	0x4D
#define CY82_IDE_SLAVE_IOR	0x4E
#define CY82_IDE_SLAVE_IOW	0x4F
#define CY82_IDE_MASTER_8BIT	0x50
#define CY82_IDE_SLAVE_8BIT	0x51

#define CY82_INDEX_PORT		0x22
#define CY82_DATA_PORT		0x23

#define CY82_INDEX_CTRLREG1	0x01
#define CY82_INDEX_CHANNEL0	0x30
#define CY82_INDEX_CHANNEL1	0x31
#define CY82_INDEX_TIMEOUT	0x32

/* the min and max PCI bus speed in MHz - from datasheet */
#define CY82C963_MIN_BUS_SPEED	25
#define CY82C963_MAX_BUS_SPEED	33

/* the struct for the PIO mode timings */
typedef struct pio_clocks_s {
	u8	address_time;	/* Address setup (clocks) */
	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
} pio_clocks_t;

/*
 * calc clocks using bus_speed
 * returns (rounded up) time in bus clocks for time in ns
 */
static int calc_clk(int time, int bus_speed)
{
	int clocks;

	clocks = (time*bus_speed+999)/1000 - 1;

	if (clocks < 0)
		clocks = 0;

	if (clocks > 0x0F)
		clocks = 0x0F;

	return clocks;
}

/*
 * compute the values for the clock registers for PIO
 * mode and pci_clk [MHz] speed
 *
 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 *
 */
static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
{
	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
	int clk1, clk2;
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;

	/* we don't check against CY82C693's min and max speed,
	 * so you can play with the idebus=xx parameter
	 */

	/* let's calc the address setup time clocks */
	p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);

	/* let's calc the active and recovery time clocks */
	clk1 = calc_clk(t->active, bus_speed);

	/* calc recovery timing */
	clk2 = t->cycle - t->active - t->setup;

	clk2 = calc_clk(clk2, bus_speed);

	clk1 = (clk1<<4)|clk2;	/* combine active and recovery clocks */

	/* note: we use the same values for 16bit IOR and IOW
	 *	those are all the same, since I don't have other
	 *	timings than those from ide-lib.c
	 */

	p_pclk->time_16r = (u8)clk1;
	p_pclk->time_16w = (u8)clk1;

	/* what are good values for 8bit ?? */
	p_pclk->time_8 = (u8)clk1;
}

/*
 * set DMA mode a specific channel for CY82C693
 */

static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;

	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the previous values */

	outb(index, CY82_INDEX_PORT);
	data = inb(CY82_DATA_PORT);

	printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		(data&0x3), ((data>>2)&1));
#endif /* CY82C693_DEBUG_LOGS */

	data = (mode & 3) | (single << 2);

	outb(index, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		mode & 3, single);
#endif /* CY82C693_DEBUG_INFO */

	/*
	 * note: below we set the value for Bus Master IDE TimeOut Register
	 * I'm not absolutly sure what this does, but it solved my problem
	 * with IDE DMA and sound, so I now can play sound and work with
	 * my IDE driver at the same time :-)
	 *
	 * If you know the correct (best) value for this register please
	 * let me know - ASK
	 */

	data = BUSMASTER_TIMEOUT;
	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
		drive->name, data);
#endif /* CY82C693_DEBUG_INFO */
}

static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	pio_clocks_t pclk;
	unsigned int addrCtrl;

	/* select primary or secondary channel */
	if (hwif->index > 0) {  /* drive is on the secondary channel */
		dev = pci_get_slot(dev->bus, dev->devfn+1);
		if (!dev) {
			printk(KERN_ERR "%s: tune_drive: "
				"Cannot find secondary interface!\n",
				drive->name);
			return;
		}
	}

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the register values */

	if (drive->select.b.unit == 0) {
		/*
		 * get master drive registers
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
		addrCtrl &= 0x0F;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	} else {
		/*
		 * set slave drive registers
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= 0xF0;
		addrCtrl >>= 4;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	}

	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_LOGS */

	/* let's calc the values for this PIO mode */
	compute_clocks(pio, &pclk);

	/* now let's write  the clocks registers */
	if (drive->select.b.unit == 0) {
		/*
		 * set master drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF);
		addrCtrl |= (unsigned int)pclk.address_time;
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);

		addrCtrl &= 0xF;
	} else {
		/*
		 * set slave drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF0);
		addrCtrl |= ((unsigned int)pclk.address_time<<4);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);

		addrCtrl >>= 4;
		addrCtrl &= 0xF;
	}

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_INFO */
}

/*
 * this function is called during init and is used to setup the cy82c693 chip
 */
static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
{
	if (PCI_FUNC(dev->devfn) != 1)
		return 0;

#ifdef CY82C693_SETDMA_CLOCK
	u8 data = 0;
#endif /* CY82C693_SETDMA_CLOCK */

	/* write info about this verion of the driver */
	printk(KERN_INFO CY82_VERSION "\n");

#ifdef CY82C693_SETDMA_CLOCK
       /* okay let's set the DMA clock speed */

	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	data = inb(CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

	/*
	 * for some reason sometimes the DMA controller
	 * speed is set to ATCLK/2 ???? - we fix this here
	 *
	 * note: i don't know what causes this strange behaviour,
	 *       but even changing the dma speed doesn't solve it :-(
	 *       the ide performance is still only half the normal speed
	 *
	 *       if anybody knows what goes wrong with my machine, please
	 *       let me know - ASK
	 */

	data |= 0x03;

	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

#endif /* CY82C693_SETDMA_CLOCK */
	return 0;
}

static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
{
	static ide_hwif_t *primary;
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_FUNC(dev->devfn) == 1)
		primary = hwif;
	else {
		hwif->mate = primary;
		hwif->channel = 1;
	}
}

static const struct ide_port_ops cy82c693_port_ops = {
	.set_pio_mode		= cy82c693_set_pio_mode,
	.set_dma_mode		= cy82c693_set_dma_mode,
};

static const struct ide_port_info cy82c693_chipset __devinitdata = {
	.name		= "CY82C693",
	.init_chipset	= init_chipset_cy82c693,
	.init_iops	= init_iops_cy82c693,
	.port_ops	= &cy82c693_port_ops,
	.chipset	= ide_cy82c693,
	.host_flags	= IDE_HFLAG_SINGLE,
	.pio_mask	= ATA_PIO4,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *dev2;
	int ret = -ENODEV;

	/* CY82C693 is more than only a IDE controller.
	   Function 1 is primary IDE channel, function 2 - secondary. */
	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	    PCI_FUNC(dev->devfn) == 1) {
		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
		ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
		/* We leak pci refs here but thats ok - we can't be unloaded */
	}
	return ret;
}

static const struct pci_device_id cy82c693_pci_tbl[] = {
	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);

static struct pci_driver driver = {
	.name		= "Cypress_IDE",
	.id_table	= cy82c693_pci_tbl,
	.probe		= cy82c693_init_one,
};

static int __init cy82c693_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cy82c693_ide_init);

MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
	3	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
	4	*
	5	* CYPRESS CY82C693 chipset IDE controller
	6	*
	7	* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
	8	* Writing the driver was quite simple, since most of the job is
175f354b	9	* done by the generic pci-ide support.
1da177e4 LT	10	* The hard part was finding the CY82C693's datasheet on Cypress's
	11	* web page :-(. But Altavista solved this problem :-).
	12	*
	13	*
	14	* Notes:
	15	* - I recently got a 16.8G IBM DTTA, so I was able to test it with
	16	* a large and fast disk - the results look great, so I'd say the
	17	* driver is working fine :-)
175f354b PC	18	* hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
175f354b PC	19	* - this is my first linux driver, so there's probably a lot of room
1da177e4	20	* for optimizations and bug fixing, so feel free to do it.
175f354b	21	* - if using PIO mode it's a good idea to set the PIO mode and
1da177e4 LT	22	* 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
	23	* - I had some problems with my IBM DHEA with PIO modes < 2
	24	* (lost interrupts) ?????
	25	* - first tests with DMA look okay, they seem to work, but there is a
	26	* problem with sound - the BusMaster IDE TimeOut should fixed this
	27	*
	28	* Ancient History:
	29	* AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
	30	* ASK@1999-01-23: v0.33 made a few minor code clean ups
	31	* removed DMA clock speed setting by default
	32	* added boot message
	33	* ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
	34	* added support to set DMA Controller Clock Speed
	35	* ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
	36	* on some drives.
	37	* ASK@1998-10-29: v0.3 added support to set DMA modes
	38	* ASK@1998-10-28: v0.2 added support to set PIO modes
	39	* ASK@1998-10-27: v0.1 first version - chipset detection
	40	*
	41	*/
	42
1da177e4 LT	43	#include <linux/module.h>
	44	#include <linux/types.h>
	45	#include <linux/pci.h>
1da177e4 LT	46	#include <linux/ide.h>
	47	#include <linux/init.h>
	48
	49	#include <asm/io.h>
	50
	51	/* the current version */
	52	#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
	53
	54	/*
	55	* The following are used to debug the driver.
	56	*/
	57	#define CY82C693_DEBUG_LOGS 0
	58	#define CY82C693_DEBUG_INFO 0
	59
	60	/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
	61	#undef CY82C693_SETDMA_CLOCK
	62
	63	/*
	64	* NOTE: the value for busmaster timeout is tricky and I got it by
	65	* trial and error! By using a to low value will cause DMA timeouts
	66	* and drop IDE performance, and by using a to high value will cause
	67	* audio playback to scatter.
	68	* If you know a better value or how to calc it, please let me know.
	69	*/
	70
	71	/* twice the value written in cy82c693ub datasheet */
	72	#define BUSMASTER_TIMEOUT 0x50
	73	/*
	74	* the value above was tested on my machine and it seems to work okay
	75	*/
	76
	77	/* here are the offset definitions for the registers */
	78	#define CY82_IDE_CMDREG 0x04
	79	#define CY82_IDE_ADDRSETUP 0x48
	80	#define CY82_IDE_MASTER_IOR 0x4C
	81	#define CY82_IDE_MASTER_IOW 0x4D
	82	#define CY82_IDE_SLAVE_IOR 0x4E
	83	#define CY82_IDE_SLAVE_IOW 0x4F
	84	#define CY82_IDE_MASTER_8BIT 0x50
	85	#define CY82_IDE_SLAVE_8BIT 0x51
	86
	87	#define CY82_INDEX_PORT 0x22
	88	#define CY82_DATA_PORT 0x23
	89
	90	#define CY82_INDEX_CTRLREG1 0x01
	91	#define CY82_INDEX_CHANNEL0 0x30
	92	#define CY82_INDEX_CHANNEL1 0x31
	93	#define CY82_INDEX_TIMEOUT 0x32
	94
1da177e4 LT	95	/* the min and max PCI bus speed in MHz - from datasheet */
	96	#define CY82C963_MIN_BUS_SPEED 25
	97	#define CY82C963_MAX_BUS_SPEED 33
	98
	99	/* the struct for the PIO mode timings */
	100	typedef struct pio_clocks_s {
	101	u8 address_time; /* Address setup (clocks) */
	102	u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	103	u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	104	u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
	105	} pio_clocks_t;
	106
	107	/*
	108	* calc clocks using bus_speed
	109	* returns (rounded up) time in bus clocks for time in ns
	110	*/
175f354b	111	static int calc_clk(int time, int bus_speed)
1da177e4 LT	112	{
	113	int clocks;
	114
175f354b	115	clocks = (time*bus_speed+999)/1000 - 1;
1da177e4 LT	116
	117	if (clocks < 0)
	118	clocks = 0;
	119
	120	if (clocks > 0x0F)
	121	clocks = 0x0F;
	122
	123	return clocks;
	124	}
	125
	126	/*
	127	* compute the values for the clock registers for PIO
	128	* mode and pci_clk [MHz] speed
	129	*
	130	* NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
	131	* for mode 3 and 4 drives 8 and 16-bit timings are the same
	132	*
175f354b PC	133	*/
175f354b PC	134	static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
1da177e4	135	{
713a590d	136	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
1da177e4	137	int clk1, clk2;
30e5ee4d	138	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
1da177e4 LT	139
	140	/* we don't check against CY82C693's min and max speed,
	141	* so you can play with the idebus=xx parameter
	142	*/
	143
1da177e4	144	/* let's calc the address setup time clocks */
713a590d	145	p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
1da177e4 LT	146
1da177e4 LT	147	/* let's calc the active and recovery time clocks */
713a590d	148	clk1 = calc_clk(t->active, bus_speed);
1da177e4 LT	149
1da177e4 LT	150	/* calc recovery timing */
713a590d	151	clk2 = t->cycle - t->active - t->setup;
1da177e4 LT	152
	153	clk2 = calc_clk(clk2, bus_speed);
	154
	155	clk1 = (clk1<<4)\|clk2; /* combine active and recovery clocks */
	156
	157	/* note: we use the same values for 16bit IOR and IOW
175f354b	158	* those are all the same, since I don't have other
1da177e4 LT	159	* timings than those from ide-lib.c
	160	*/
	161
	162	p_pclk->time_16r = (u8)clk1;
	163	p_pclk->time_16w = (u8)clk1;
	164
	165	/* what are good values for 8bit ?? */
	166	p_pclk->time_8 = (u8)clk1;
	167	}
	168
	169	/*
	170	* set DMA mode a specific channel for CY82C693
	171	*/
	172
8704de8f	173	static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4	174	{
8704de8f BZ	175	ide_hwif_t *hwif = drive->hwif;
8704de8f BZ	176	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
1da177e4	177
8704de8f	178	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
1da177e4 LT	179
	180	#if CY82C693_DEBUG_LOGS
	181	/* for debug let's show the previous values */
	182
0ecdca26 BZ	183	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	184	data = inb(CY82_DATA_PORT);
1da177e4	185
175f354b	186	printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
1da177e4 LT	187	drive->name, HWIF(drive)->channel, drive->select.b.unit,
	188	(data&0x3), ((data>>2)&1));
	189	#endif /* CY82C693_DEBUG_LOGS */
	190
8704de8f	191	data = (mode & 3) \| (single << 2);
1da177e4	192
0ecdca26 BZ	193	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	194	outb(data, CY82_DATA_PORT);
1da177e4 LT	195
	196	#if CY82C693_DEBUG_INFO
	197	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
	198	drive->name, HWIF(drive)->channel, drive->select.b.unit,
8704de8f	199	mode & 3, single);
1da177e4 LT	200	#endif /* CY82C693_DEBUG_INFO */
1da177e4 LT	201
175f354b	202	/*
1da177e4 LT	203	* note: below we set the value for Bus Master IDE TimeOut Register
	204	* I'm not absolutly sure what this does, but it solved my problem
	205	* with IDE DMA and sound, so I now can play sound and work with
	206	* my IDE driver at the same time :-)
	207	*
	208	* If you know the correct (best) value for this register please
	209	* let me know - ASK
	210	*/
	211
	212	data = BUSMASTER_TIMEOUT;
0ecdca26 BZ	213	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
0ecdca26 BZ	214	outb(data, CY82_DATA_PORT);
1da177e4	215
175f354b PC	216	#if CY82C693_DEBUG_INFO
175f354b PC	217	printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
1da177e4 LT	218	drive->name, data);
	219	#endif /* CY82C693_DEBUG_INFO */
	220	}
	221
26bcb879	222	static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	223	{
1da177e4 LT	224	ide_hwif_t *hwif = HWIF(drive);
36501650	225	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	226	pio_clocks_t pclk;
	227	unsigned int addrCtrl;
	228
	229	/* select primary or secondary channel */
	230	if (hwif->index > 0) { /* drive is on the secondary channel */
652aa162	231	dev = pci_get_slot(dev->bus, dev->devfn+1);
1da177e4 LT	232	if (!dev) {
	233	printk(KERN_ERR "%s: tune_drive: "
	234	"Cannot find secondary interface!\n",
	235	drive->name);
	236	return;
	237	}
	238	}
	239
	240	#if CY82C693_DEBUG_LOGS
	241	/* for debug let's show the register values */
175f354b PC	242
175f354b PC	243	if (drive->select.b.unit == 0) {
1da177e4	244	/*
175f354b	245	* get master drive registers
1da177e4 LT	246	* address setup control register
1da177e4 LT	247	* is 32 bit !!!
175f354b PC	248	*/
175f354b PC	249	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
1da177e4 LT	250	addrCtrl &= 0x0F;
	251
	252	/* now let's get the remaining registers */
	253	pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
	254	pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
	255	pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	256	} else {
	257	/*
	258	* set slave drive registers
	259	* address setup control register
	260	* is 32 bit !!!
175f354b	261	*/
1da177e4 LT	262	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	263
	264	addrCtrl &= 0xF0;
	265	addrCtrl >>= 4;
	266
	267	/* now let's get the remaining registers */
	268	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
	269	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
	270	pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	271	}
	272
	273	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
	274	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	275	drive->name, hwif->channel, drive->select.b.unit,
	276	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	277	#endif /* CY82C693_DEBUG_LOGS */
	278
1da177e4 LT	279	/* let's calc the values for this PIO mode */
	280	compute_clocks(pio, &pclk);
	281
	282	/* now let's write the clocks registers */
	283	if (drive->select.b.unit == 0) {
	284	/*
	285	* set master drive
	286	* address setup control register
	287	* is 32 bit !!!
175f354b	288	*/
1da177e4	289	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
175f354b	290
1da177e4 LT	291	addrCtrl &= (~0xF);
	292	addrCtrl \|= (unsigned int)pclk.address_time;
	293	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	294
	295	/* now let's set the remaining registers */
	296	pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
	297	pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
	298	pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
175f354b	299
1da177e4 LT	300	addrCtrl &= 0xF;
	301	} else {
	302	/*
	303	* set slave drive
	304	* address setup control register
	305	* is 32 bit !!!
175f354b	306	*/
1da177e4 LT	307	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	308
	309	addrCtrl &= (~0xF0);
	310	addrCtrl \|= ((unsigned int)pclk.address_time<<4);
	311	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	312
	313	/* now let's set the remaining registers */
	314	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
	315	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
	316	pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
	317
	318	addrCtrl >>= 4;
	319	addrCtrl &= 0xF;
175f354b	320	}
1da177e4 LT	321
	322	#if CY82C693_DEBUG_INFO
	323	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
	324	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	325	drive->name, hwif->channel, drive->select.b.unit,
	326	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	327	#endif /* CY82C693_DEBUG_INFO */
	328	}
	329
	330	/*
	331	* this function is called during init and is used to setup the cy82c693 chip
	332	*/
ddbc9fb4	333	static unsigned int __devinit init_chipset_cy82c693(struct pci_dev dev, const char name)
1da177e4 LT	334	{
	335	if (PCI_FUNC(dev->devfn) != 1)
	336	return 0;
	337
	338	#ifdef CY82C693_SETDMA_CLOCK
	339	u8 data = 0;
175f354b	340	#endif /* CY82C693_SETDMA_CLOCK */
1da177e4 LT	341
	342	/* write info about this verion of the driver */
	343	printk(KERN_INFO CY82_VERSION "\n");
	344
	345	#ifdef CY82C693_SETDMA_CLOCK
	346	/* okay let's set the DMA clock speed */
175f354b PC	347
	348	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	349	data = inb(CY82_DATA_PORT);
1da177e4 LT	350
	351	#if CY82C693_DEBUG_INFO
	352	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
	353	name, data);
	354	#endif /* CY82C693_DEBUG_INFO */
	355
175f354b	356	/*
1da177e4 LT	357	* for some reason sometimes the DMA controller
1da177e4 LT	358	* speed is set to ATCLK/2 ???? - we fix this here
175f354b	359	*
1da177e4 LT	360	* note: i don't know what causes this strange behaviour,
1da177e4 LT	361	* but even changing the dma speed doesn't solve it :-(
175f354b PC	362	* the ide performance is still only half the normal speed
175f354b PC	363	*
1da177e4 LT	364	* if anybody knows what goes wrong with my machine, please
1da177e4 LT	365	* let me know - ASK
175f354b	366	*/
1da177e4 LT	367
	368	data \|= 0x03;
	369
175f354b PC	370	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
175f354b PC	371	outb(data, CY82_DATA_PORT);
1da177e4 LT	372
1da177e4 LT	373	#if CY82C693_DEBUG_INFO
175f354b	374	printk(KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
1da177e4 LT	375	name, data);
	376	#endif /* CY82C693_DEBUG_INFO */
	377
	378	#endif /* CY82C693_SETDMA_CLOCK */
	379	return 0;
	380	}
	381
e851b620	382	static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
1da177e4	383	{
f32d26ae	384	static ide_hwif_t *primary;
36501650	385	struct pci_dev *dev = to_pci_dev(hwif->dev);
f32d26ae	386
36501650	387	if (PCI_FUNC(dev->devfn) == 1)
1da177e4 LT	388	primary = hwif;
	389	else {
	390	hwif->mate = primary;
	391	hwif->channel = 1;
	392	}
	393	}
	394
ac95beed BZ	395	static const struct ide_port_ops cy82c693_port_ops = {
	396	.set_pio_mode = cy82c693_set_pio_mode,
	397	.set_dma_mode = cy82c693_set_dma_mode,
	398	};
	399
85620436	400	static const struct ide_port_info cy82c693_chipset __devinitdata = {
7b77d864 BZ	401	.name = "CY82C693",
	402	.init_chipset = init_chipset_cy82c693,
	403	.init_iops = init_iops_cy82c693,
ac95beed	404	.port_ops = &cy82c693_port_ops,
528a572d	405	.chipset = ide_cy82c693,
951784b6	406	.host_flags = IDE_HFLAG_SINGLE,
4099d143	407	.pio_mask = ATA_PIO4,
8704de8f BZ	408	.swdma_mask = ATA_SWDMA2,
8704de8f BZ	409	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	410	};
	411
	412	static int __devinit cy82c693_init_one(struct pci_dev dev, const struct pci_device_id id)
	413	{
1da177e4 LT	414	struct pci_dev *dev2;
	415	int ret = -ENODEV;
	416
	417	/* CY82C693 is more than only a IDE controller.
	418	Function 1 is primary IDE channel, function 2 - secondary. */
175f354b	419	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
1da177e4	420	PCI_FUNC(dev->devfn) == 1) {
652aa162	421	dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
6cdf6eb3	422	ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
652aa162	423	/* We leak pci refs here but thats ok - we can't be unloaded */
1da177e4 LT	424	}
	425	return ret;
	426	}
	427
9cbcc5e3 BZ	428	static const struct pci_device_id cy82c693_pci_tbl[] = {
9cbcc5e3 BZ	429	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
1da177e4 LT	430	{ 0, },
	431	};
	432	MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
	433
	434	static struct pci_driver driver = {
	435	.name = "Cypress_IDE",
	436	.id_table = cy82c693_pci_tbl,
	437	.probe = cy82c693_init_one,
	438	};
	439
82ab1eec	440	static int __init cy82c693_ide_init(void)
1da177e4 LT	441	{
	442	return ide_pci_register_driver(&driver);
	443	}
	444
	445	module_init(cy82c693_ide_init);
	446
	447	MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
	448	MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
	449	MODULE_LICENSE("GPL");