[deliverable/linux.git] / drivers / ide / pci / hpt34x.c

/*
 * linux/drivers/ide/pci/hpt34x.c		Version 0.40	Sept 10, 2002
 *
 * Copyright (C) 1998-2000	Andre Hedrick <andre@linux-ide.org>
 * May be copied or modified under the terms of the GNU General Public License
 *
 *
 * 00:12.0 Unknown mass storage controller:
 * Triones Technologies, Inc.
 * Unknown device 0003 (rev 01)
 *
 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
 * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
 * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
 * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
 * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
 *
 * ide-pci.c reference
 *
 * Since there are two cards that report almost identically,
 * the only discernable difference is the values reported in pcicmd.
 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
 * Non-bootable card or HPT343 :: pcicmd == 0x05
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define HPT343_DEBUG_DRIVE_INFO		0

static u8 hpt34x_ratemask (ide_drive_t *drive)
{
	return 1;
}

static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	u8 speed	= ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
	u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
	u8			hi_speed, lo_speed;

	hi_speed = speed >> 4;
	lo_speed = speed & 0x0f;

	if (hi_speed & 7) {
		hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
	} else {
		lo_speed <<= 5;
		lo_speed >>= 5;
	}

	pci_read_config_dword(dev, 0x44, &reg1);
	pci_read_config_dword(dev, 0x48, &reg2);
	tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
	tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
	pci_write_config_dword(dev, 0x44, tmp1);
	pci_write_config_dword(dev, 0x48, tmp2);

#if HPT343_DEBUG_DRIVE_INFO
	printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
		" (0x%02x 0x%02x)\n",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, reg1, tmp1, reg2, tmp2,
		hi_speed, lo_speed);
#endif /* HPT343_DEBUG_DRIVE_INFO */

	return(ide_config_drive_speed(drive, speed));
}

static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
	(void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
}

/*
 * This allows the configuration of ide_pci chipset registers
 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 * after the drive is reported by the OS.  Initially for designed for
 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
 */

static int config_chipset_for_dma (ide_drive_t *drive)
{
	u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));

	if (!(speed))
		return 0;

	(void) hpt34x_tune_chipset(drive, speed);
	return ide_dma_enable(drive);
}

static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);

	drive->init_speed = 0;

	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
#ifndef CONFIG_HPT34X_AUTODMA
		return hwif->ide_dma_off_quietly(drive);
#else
		return hwif->ide_dma_on(drive);
#endif

	if (ide_use_fast_pio(drive))
		hpt34x_tune_drive(drive, 255);

	return hwif->ide_dma_off_quietly(drive);
}

/*
 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
 */
#define	HPT34X_PCI_INIT_REG		0x80

static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
{
	int i = 0;
	unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
	unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
	unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
	u16 cmd;
	unsigned long flags;

	local_irq_save(flags);

	pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
	pci_read_config_word(dev, PCI_COMMAND, &cmd);

	if (cmd & PCI_COMMAND_MEMORY) {
		if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
			pci_write_config_dword(dev, PCI_ROM_ADDRESS,
				dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
			printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
				(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
		}
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	} else {
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
	}

	/*
	 * Since 20-23 can be assigned and are R/W, we correct them.
	 */
	pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
	for(i=0; i<4; i++) {
		dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
		dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
		dev->resource[i].flags = IORESOURCE_IO;
		pci_write_config_dword(dev,
				(PCI_BASE_ADDRESS_0 + (i * 4)),
				dev->resource[i].start);
	}
	pci_write_config_word(dev, PCI_COMMAND, cmd);

	local_irq_restore(flags);

	return dev->irq;
}

static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
{
	u16 pcicmd = 0;

	hwif->autodma = 0;

	hwif->tuneproc = &hpt34x_tune_drive;
	hwif->speedproc = &hpt34x_tune_chipset;
	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);

	if (!hwif->dma_base)
		return;

	hwif->ultra_mask = 0x07;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;

	hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
	if (!noautodma)
		hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t hpt34x_chipset __devinitdata = {
	.name		= "HPT34X",
	.init_chipset	= init_chipset_hpt34x,
	.init_hwif	= init_hwif_hpt34x,
	.channels	= 2,
	.autodma	= NOAUTODMA,
	.bootable	= NEVER_BOARD,
	.extra		= 16
};

static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &hpt34x_chipset;
	static char *chipset_names[] = {"HPT343", "HPT345"};
	u16 pcicmd = 0;

	pci_read_config_word(dev, PCI_COMMAND, &pcicmd);

	d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
	d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;

	return ide_setup_pci_device(dev, d);
}

static struct pci_device_id hpt34x_pci_tbl[] = {
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);

static struct pci_driver driver = {
	.name		= "HPT34x_IDE",
	.id_table	= hpt34x_pci_tbl,
	.probe		= hpt34x_init_one,
};

static int __init hpt34x_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(hpt34x_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
	3	*
	4	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	5	* May be copied or modified under the terms of the GNU General Public License
	6	*
	7	*
	8	* 00:12.0 Unknown mass storage controller:
	9	* Triones Technologies, Inc.
	10	* Unknown device 0003 (rev 01)
	11	*
	12	* hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
	13	* hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
	14	* hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
	15	* hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
	16	* hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
	17	* hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
	18	*
	19	* ide-pci.c reference
	20	*
	21	* Since there are two cards that report almost identically,
	22	* the only discernable difference is the values reported in pcicmd.
	23	* Booting-BIOS card or HPT363 :: pcicmd == 0x07
	24	* Non-bootable card or HPT343 :: pcicmd == 0x05
	25	*/
	26
1da177e4 LT	27	#include <linux/module.h>
	28	#include <linux/types.h>
	29	#include <linux/kernel.h>
	30	#include <linux/delay.h>
	31	#include <linux/timer.h>
	32	#include <linux/mm.h>
	33	#include <linux/ioport.h>
	34	#include <linux/blkdev.h>
	35	#include <linux/hdreg.h>
	36	#include <linux/interrupt.h>
	37	#include <linux/pci.h>
	38	#include <linux/init.h>
	39	#include <linux/ide.h>
	40
	41	#include <asm/io.h>
	42	#include <asm/irq.h>
	43
	44	#define HPT343_DEBUG_DRIVE_INFO 0
	45
	46	static u8 hpt34x_ratemask (ide_drive_t *drive)
	47	{
	48	return 1;
	49	}
	50
1da177e4 LT	51	static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
	52	{
	53	struct pci_dev *dev = HWIF(drive)->pci_dev;
	54	u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
	55	u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
	56	u8 hi_speed, lo_speed;
	57
	58	hi_speed = speed >> 4;
	59	lo_speed = speed & 0x0f;
	60
	61	if (hi_speed & 7) {
	62	hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
	63	} else {
	64	lo_speed <<= 5;
	65	lo_speed >>= 5;
	66	}
	67
	68	pci_read_config_dword(dev, 0x44, &reg1);
	69	pci_read_config_dword(dev, 0x48, &reg2);
	70	tmp1 = ((lo_speed << (3drive->dn)) \| (reg1 & ~(7 << (3drive->dn))));
296d9bcc	71	tmp2 = ((hi_speed << drive->dn) \| (reg2 & ~(0x11 << drive->dn)));
1da177e4 LT	72	pci_write_config_dword(dev, 0x44, tmp1);
	73	pci_write_config_dword(dev, 0x48, tmp2);
	74
	75	#if HPT343_DEBUG_DRIVE_INFO
	76	printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
	77	" (0x%02x 0x%02x)\n",
	78	drive->name, ide_xfer_verbose(speed),
	79	drive->dn, reg1, tmp1, reg2, tmp2,
	80	hi_speed, lo_speed);
	81	#endif /* HPT343_DEBUG_DRIVE_INFO */
	82
	83	return(ide_config_drive_speed(drive, speed));
	84	}
	85
	86	static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
	87	{
	88	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
1da177e4 LT	89	(void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
	90	}
	91
	92	/*
	93	* This allows the configuration of ide_pci chipset registers
	94	* for cards that learn about the drive's UDMA, DMA, PIO capabilities
	95	* after the drive is reported by the OS. Initially for designed for
	96	* HPT343 UDMA chipset by HighPoint\|Triones Technologies, Inc.
	97	*/
	98
	99	static int config_chipset_for_dma (ide_drive_t *drive)
	100	{
	101	u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
	102
	103	if (!(speed))
	104	return 0;
	105
1da177e4 LT	106	(void) hpt34x_tune_chipset(drive, speed);
	107	return ide_dma_enable(drive);
	108	}
	109
	110	static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
	111	{
	112	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	113
	114	drive->init_speed = 0;
	115
7569e8dc	116	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
1da177e4	117	#ifndef CONFIG_HPT34X_AUTODMA
7569e8dc	118	return hwif->ide_dma_off_quietly(drive);
1da177e4	119	#else
7569e8dc	120	return hwif->ide_dma_on(drive);
1da177e4	121	#endif
1da177e4	122
d8f4469d	123	if (ide_use_fast_pio(drive))
1da177e4	124	hpt34x_tune_drive(drive, 255);
d8f4469d BZ	125
d8f4469d BZ	126	return hwif->ide_dma_off_quietly(drive);
1da177e4 LT	127	}
	128
	129	/*
	130	* If the BIOS does not set the IO base addaress to XX00, 343 will fail.
	131	*/
	132	#define HPT34X_PCI_INIT_REG 0x80
	133
	134	static unsigned int __devinit init_chipset_hpt34x(struct pci_dev dev, const char name)
	135	{
	136	int i = 0;
	137	unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
	138	unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
	139	unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
	140	u16 cmd;
	141	unsigned long flags;
	142
	143	local_irq_save(flags);
	144
	145	pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
	146	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	147
	148	if (cmd & PCI_COMMAND_MEMORY) {
	149	if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
299cc3c1	150	pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1da177e4 LT	151	dev->resource[PCI_ROM_RESOURCE].start \| PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	152	printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
08f46de9	153	(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
1da177e4 LT	154	}
	155	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	156	} else {
	157	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
	158	}
	159
	160	/*
	161	* Since 20-23 can be assigned and are R/W, we correct them.
	162	*/
	163	pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
	164	for(i=0; i<4; i++) {
	165	dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
	166	dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
	167	dev->resource[i].flags = IORESOURCE_IO;
	168	pci_write_config_dword(dev,
	169	(PCI_BASE_ADDRESS_0 + (i * 4)),
	170	dev->resource[i].start);
	171	}
	172	pci_write_config_word(dev, PCI_COMMAND, cmd);
	173
	174	local_irq_restore(flags);
	175
	176	return dev->irq;
	177	}
	178
	179	static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
	180	{
	181	u16 pcicmd = 0;
	182
	183	hwif->autodma = 0;
	184
	185	hwif->tuneproc = &hpt34x_tune_drive;
	186	hwif->speedproc = &hpt34x_tune_chipset;
1da177e4 LT	187	hwif->drives[0].autotune = 1;
	188	hwif->drives[1].autotune = 1;
	189
	190	pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
	191
	192	if (!hwif->dma_base)
	193	return;
	194
	195	hwif->ultra_mask = 0x07;
	196	hwif->mwdma_mask = 0x07;
	197	hwif->swdma_mask = 0x07;
	198
	199	hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
	200	if (!noautodma)
	201	hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
	202	hwif->drives[0].autodma = hwif->autodma;
	203	hwif->drives[1].autodma = hwif->autodma;
	204	}
	205
	206	static ide_pci_device_t hpt34x_chipset __devinitdata = {
	207	.name = "HPT34X",
	208	.init_chipset = init_chipset_hpt34x,
	209	.init_hwif = init_hwif_hpt34x,
	210	.channels = 2,
	211	.autodma = NOAUTODMA,
	212	.bootable = NEVER_BOARD,
	213	.extra = 16
	214	};
	215
	216	static int __devinit hpt34x_init_one(struct pci_dev dev, const struct pci_device_id id)
	217	{
	218	ide_pci_device_t *d = &hpt34x_chipset;
	219	static char *chipset_names[] = {"HPT343", "HPT345"};
	220	u16 pcicmd = 0;
	221
	222	pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
	223
	224	d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
	225	d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
	226
	227	return ide_setup_pci_device(dev, d);
	228	}
	229
	230	static struct pci_device_id hpt34x_pci_tbl[] = {
	231	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	232	{ 0, },
	233	};
	234	MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
	235
	236	static struct pci_driver driver = {
	237	.name = "HPT34x_IDE",
	238	.id_table = hpt34x_pci_tbl,
	239	.probe = hpt34x_init_one,
	240	};
	241
82ab1eec	242	static int __init hpt34x_ide_init(void)
1da177e4 LT	243	{
	244	return ide_pci_register_driver(&driver);
	245	}
	246
	247	module_init(hpt34x_ide_init);
	248
	249	MODULE_AUTHOR("Andre Hedrick");
	250	MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
	251	MODULE_LICENSE("GPL");