Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9adf768a | 2 | * linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> | |
fed21641 | 5 | * Copyright (C) 2006-2007 MontaVista Software, Inc. |
4fce3164 | 6 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
7 | * |
8 | * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this | |
9 | * compiled into the kernel if you have more than one card installed. | |
10 | * Note that BIOS v1.29 is reported to fix the problem. Since this is | |
11 | * safe chipset tuning, including this support is harmless | |
12 | * | |
13 | * Promise Ultra66 cards with BIOS v1.11 this | |
14 | * compiled into the kernel if you have more than one card installed. | |
15 | * | |
16 | * Promise Ultra100 cards. | |
17 | * | |
18 | * The latest chipset code will support the following :: | |
19 | * Three Ultra33 controllers and 12 drives. | |
20 | * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word. | |
21 | * The 8/4 ratio is a BIOS code limit by promise. | |
22 | * | |
23 | * UNLESS you enable "CONFIG_PDC202XX_BURST" | |
24 | * | |
25 | */ | |
26 | ||
27 | /* | |
28 | * Portions Copyright (C) 1999 Promise Technology, Inc. | |
29 | * Author: Frank Tiernan (frankt@promise.com) | |
30 | * Released under terms of General Public License | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/types.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/timer.h> | |
38 | #include <linux/mm.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/blkdev.h> | |
41 | #include <linux/hdreg.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/init.h> | |
45 | #include <linux/ide.h> | |
46 | ||
47 | #include <asm/io.h> | |
48 | #include <asm/irq.h> | |
49 | ||
1da177e4 LT |
50 | #define PDC202XX_DEBUG_DRIVE_INFO 0 |
51 | ||
52 | static const char *pdc_quirk_drives[] = { | |
53 | "QUANTUM FIREBALLlct08 08", | |
54 | "QUANTUM FIREBALLP KA6.4", | |
55 | "QUANTUM FIREBALLP KA9.1", | |
56 | "QUANTUM FIREBALLP LM20.4", | |
57 | "QUANTUM FIREBALLP KX13.6", | |
58 | "QUANTUM FIREBALLP KX20.5", | |
59 | "QUANTUM FIREBALLP KX27.3", | |
60 | "QUANTUM FIREBALLP LM20.5", | |
61 | NULL | |
62 | }; | |
63 | ||
4fce3164 | 64 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *); |
1da177e4 | 65 | |
88b2b32b | 66 | static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
67 | { |
68 | ide_hwif_t *hwif = HWIF(drive); | |
69 | struct pci_dev *dev = hwif->pci_dev; | |
70 | u8 drive_pci = 0x60 + (drive->dn << 2); | |
1da177e4 | 71 | |
4fce3164 | 72 | u8 AP = 0, BP = 0, CP = 0; |
1da177e4 LT |
73 | u8 TA = 0, TB = 0, TC = 0; |
74 | ||
4fce3164 BZ |
75 | #if PDC202XX_DEBUG_DRIVE_INFO |
76 | u32 drive_conf = 0; | |
1da177e4 | 77 | pci_read_config_dword(dev, drive_pci, &drive_conf); |
4fce3164 | 78 | #endif |
1da177e4 | 79 | |
4fce3164 BZ |
80 | /* |
81 | * TODO: do this once per channel | |
82 | */ | |
83 | if (dev->device != PCI_DEVICE_ID_PROMISE_20246) | |
84 | pdc_old_disable_66MHz_clock(hwif); | |
1da177e4 | 85 | |
4fce3164 BZ |
86 | pci_read_config_byte(dev, drive_pci, &AP); |
87 | pci_read_config_byte(dev, drive_pci + 1, &BP); | |
88 | pci_read_config_byte(dev, drive_pci + 2, &CP); | |
1da177e4 LT |
89 | |
90 | switch(speed) { | |
1da177e4 LT |
91 | case XFER_UDMA_5: |
92 | case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; | |
93 | case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; | |
94 | case XFER_UDMA_3: | |
95 | case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; | |
96 | case XFER_UDMA_0: | |
97 | case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; | |
98 | case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; | |
4fce3164 | 99 | case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; |
1da177e4 LT |
100 | case XFER_PIO_4: TA = 0x01; TB = 0x04; break; |
101 | case XFER_PIO_3: TA = 0x02; TB = 0x06; break; | |
102 | case XFER_PIO_2: TA = 0x03; TB = 0x08; break; | |
103 | case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; | |
104 | case XFER_PIO_0: | |
105 | default: TA = 0x09; TB = 0x13; break; | |
106 | } | |
107 | ||
108 | if (speed < XFER_SW_DMA_0) { | |
4fce3164 BZ |
109 | /* |
110 | * preserve SYNC_INT / ERDDY_EN bits while clearing | |
111 | * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A | |
112 | */ | |
113 | AP &= ~0x3f; | |
114 | if (drive->id->capability & 4) | |
115 | AP |= 0x20; /* set IORDY_EN bit */ | |
116 | if (drive->media == ide_disk) | |
117 | AP |= 0x10; /* set Prefetch_EN bit */ | |
118 | /* clear PB[4:0] bits of register B */ | |
119 | BP &= ~0x1f; | |
120 | pci_write_config_byte(dev, drive_pci, AP | TA); | |
121 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
1da177e4 | 122 | } else { |
4fce3164 BZ |
123 | /* clear MB[2:0] bits of register B */ |
124 | BP &= ~0xe0; | |
125 | /* clear MC[3:0] bits of register C */ | |
126 | CP &= ~0x0f; | |
127 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
128 | pci_write_config_byte(dev, drive_pci + 2, CP | TC); | |
1da177e4 LT |
129 | } |
130 | ||
131 | #if PDC202XX_DEBUG_DRIVE_INFO | |
132 | printk(KERN_DEBUG "%s: %s drive%d 0x%08x ", | |
133 | drive->name, ide_xfer_verbose(speed), | |
134 | drive->dn, drive_conf); | |
4fce3164 | 135 | pci_read_config_dword(dev, drive_pci, &drive_conf); |
1da177e4 | 136 | printk("0x%08x\n", drive_conf); |
4fce3164 | 137 | #endif |
1da177e4 LT |
138 | } |
139 | ||
26bcb879 | 140 | static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 141 | { |
88b2b32b | 142 | pdc202xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
143 | } |
144 | ||
145 | static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif) | |
146 | { | |
147 | u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10); | |
49521f97 | 148 | |
1da177e4 | 149 | pci_read_config_word(hwif->pci_dev, 0x50, &CIS); |
49521f97 BZ |
150 | |
151 | return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 LT |
152 | } |
153 | ||
154 | /* | |
155 | * Set the control register to use the 66MHz system | |
156 | * clock for UDMA 3/4/5 mode operation when necessary. | |
157 | * | |
4fce3164 BZ |
158 | * FIXME: this register is shared by both channels, some locking is needed |
159 | * | |
1da177e4 LT |
160 | * It may also be possible to leave the 66MHz clock on |
161 | * and readjust the timing parameters. | |
162 | */ | |
163 | static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) | |
164 | { | |
165 | unsigned long clock_reg = hwif->dma_master + 0x11; | |
0ecdca26 | 166 | u8 clock = inb(clock_reg); |
1da177e4 | 167 | |
0ecdca26 | 168 | outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
169 | } |
170 | ||
171 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) | |
172 | { | |
173 | unsigned long clock_reg = hwif->dma_master + 0x11; | |
0ecdca26 | 174 | u8 clock = inb(clock_reg); |
1da177e4 | 175 | |
0ecdca26 | 176 | outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
177 | } |
178 | ||
1da177e4 LT |
179 | static int pdc202xx_quirkproc (ide_drive_t *drive) |
180 | { | |
d24ec426 SS |
181 | const char **list, *model = drive->id->model; |
182 | ||
183 | for (list = pdc_quirk_drives; *list != NULL; list++) | |
184 | if (strstr(model, *list) != NULL) | |
185 | return 2; | |
186 | return 0; | |
1da177e4 LT |
187 | } |
188 | ||
189 | static void pdc202xx_old_ide_dma_start(ide_drive_t *drive) | |
190 | { | |
191 | if (drive->current_speed > XFER_UDMA_2) | |
192 | pdc_old_enable_66MHz_clock(drive->hwif); | |
f3d5b34c | 193 | if (drive->media != ide_disk || drive->addressing == 1) { |
1da177e4 LT |
194 | struct request *rq = HWGROUP(drive)->rq; |
195 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
196 | unsigned long high_16 = hwif->dma_master; |
197 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); | |
198 | u32 word_count = 0; | |
0ecdca26 | 199 | u8 clock = inb(high_16 + 0x11); |
1da177e4 | 200 | |
0ecdca26 | 201 | outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); |
1da177e4 LT |
202 | word_count = (rq->nr_sectors << 8); |
203 | word_count = (rq_data_dir(rq) == READ) ? | |
204 | word_count | 0x05000000 : | |
205 | word_count | 0x06000000; | |
0ecdca26 | 206 | outl(word_count, atapi_reg); |
1da177e4 LT |
207 | } |
208 | ide_dma_start(drive); | |
209 | } | |
210 | ||
211 | static int pdc202xx_old_ide_dma_end(ide_drive_t *drive) | |
212 | { | |
f3d5b34c | 213 | if (drive->media != ide_disk || drive->addressing == 1) { |
1da177e4 | 214 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 LT |
215 | unsigned long high_16 = hwif->dma_master; |
216 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); | |
217 | u8 clock = 0; | |
218 | ||
0ecdca26 BZ |
219 | outl(0, atapi_reg); /* zero out extra */ |
220 | clock = inb(high_16 + 0x11); | |
221 | outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); | |
1da177e4 LT |
222 | } |
223 | if (drive->current_speed > XFER_UDMA_2) | |
224 | pdc_old_disable_66MHz_clock(drive->hwif); | |
225 | return __ide_dma_end(drive); | |
226 | } | |
227 | ||
228 | static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive) | |
229 | { | |
230 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 | 231 | unsigned long high_16 = hwif->dma_master; |
0ecdca26 BZ |
232 | u8 dma_stat = inb(hwif->dma_status); |
233 | u8 sc1d = inb(high_16 + 0x001d); | |
1da177e4 LT |
234 | |
235 | if (hwif->channel) { | |
236 | /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */ | |
237 | if ((sc1d & 0x50) == 0x50) | |
238 | goto somebody_else; | |
239 | else if ((sc1d & 0x40) == 0x40) | |
240 | return (dma_stat & 4) == 4; | |
241 | } else { | |
242 | /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */ | |
243 | if ((sc1d & 0x05) == 0x05) | |
244 | goto somebody_else; | |
245 | else if ((sc1d & 0x04) == 0x04) | |
246 | return (dma_stat & 4) == 4; | |
247 | } | |
248 | somebody_else: | |
249 | return (dma_stat & 4) == 4; /* return 1 if INTR asserted */ | |
250 | } | |
251 | ||
841d2a9b | 252 | static void pdc202xx_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 253 | { |
841d2a9b SS |
254 | ide_hwif_t *hwif = HWIF(drive); |
255 | ||
256 | if (hwif->resetproc != NULL) | |
257 | hwif->resetproc(drive); | |
258 | ||
259 | ide_dma_lost_irq(drive); | |
1da177e4 LT |
260 | } |
261 | ||
c283f5db | 262 | static void pdc202xx_dma_timeout(ide_drive_t *drive) |
1da177e4 | 263 | { |
c283f5db SS |
264 | ide_hwif_t *hwif = HWIF(drive); |
265 | ||
266 | if (hwif->resetproc != NULL) | |
267 | hwif->resetproc(drive); | |
268 | ||
269 | ide_dma_timeout(drive); | |
1da177e4 LT |
270 | } |
271 | ||
272 | static void pdc202xx_reset_host (ide_hwif_t *hwif) | |
273 | { | |
1da177e4 | 274 | unsigned long high_16 = hwif->dma_master; |
0ecdca26 | 275 | u8 udma_speed_flag = inb(high_16 | 0x001f); |
1da177e4 | 276 | |
0ecdca26 | 277 | outb(udma_speed_flag | 0x10, high_16 | 0x001f); |
1da177e4 | 278 | mdelay(100); |
0ecdca26 | 279 | outb(udma_speed_flag & ~0x10, high_16 | 0x001f); |
1da177e4 LT |
280 | mdelay(2000); /* 2 seconds ?! */ |
281 | ||
282 | printk(KERN_WARNING "PDC202XX: %s channel reset.\n", | |
283 | hwif->channel ? "Secondary" : "Primary"); | |
284 | } | |
285 | ||
286 | static void pdc202xx_reset (ide_drive_t *drive) | |
287 | { | |
288 | ide_hwif_t *hwif = HWIF(drive); | |
289 | ide_hwif_t *mate = hwif->mate; | |
26bcb879 | 290 | |
1da177e4 LT |
291 | pdc202xx_reset_host(hwif); |
292 | pdc202xx_reset_host(mate); | |
26bcb879 BZ |
293 | |
294 | ide_set_max_pio(drive); | |
1da177e4 LT |
295 | } |
296 | ||
57e834e2 AC |
297 | static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, |
298 | const char *name) | |
1da177e4 | 299 | { |
1da177e4 LT |
300 | return dev->irq; |
301 | } | |
302 | ||
303 | static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif) | |
304 | { | |
26bcb879 | 305 | hwif->set_pio_mode = &pdc202xx_set_pio_mode; |
88b2b32b | 306 | hwif->set_dma_mode = &pdc202xx_set_mode; |
26bcb879 | 307 | |
1da177e4 LT |
308 | hwif->quirkproc = &pdc202xx_quirkproc; |
309 | ||
8b6ebe01 | 310 | if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) |
1da177e4 | 311 | hwif->resetproc = &pdc202xx_reset; |
1da177e4 | 312 | |
e98d6e50 BZ |
313 | if (hwif->dma_base == 0) |
314 | return; | |
315 | ||
841d2a9b | 316 | hwif->dma_lost_irq = &pdc202xx_dma_lost_irq; |
c283f5db | 317 | hwif->dma_timeout = &pdc202xx_dma_timeout; |
1da177e4 LT |
318 | |
319 | if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) { | |
49521f97 BZ |
320 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
321 | hwif->cbl = pdc202xx_old_cable_detect(hwif); | |
322 | ||
1da177e4 LT |
323 | hwif->dma_start = &pdc202xx_old_ide_dma_start; |
324 | hwif->ide_dma_end = &pdc202xx_old_ide_dma_end; | |
325 | } | |
326 | hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq; | |
1da177e4 LT |
327 | } |
328 | ||
329 | static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase) | |
330 | { | |
331 | u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; | |
332 | ||
333 | if (hwif->channel) { | |
334 | ide_setup_dma(hwif, dmabase, 8); | |
335 | return; | |
336 | } | |
337 | ||
0ecdca26 BZ |
338 | udma_speed_flag = inb(dmabase | 0x1f); |
339 | primary_mode = inb(dmabase | 0x1a); | |
340 | secondary_mode = inb(dmabase | 0x1b); | |
1da177e4 LT |
341 | printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ |
342 | "Primary %s Mode " \ | |
343 | "Secondary %s Mode.\n", hwif->cds->name, | |
344 | (udma_speed_flag & 1) ? "EN" : "DIS", | |
345 | (primary_mode & 1) ? "MASTER" : "PCI", | |
346 | (secondary_mode & 1) ? "MASTER" : "PCI" ); | |
347 | ||
348 | #ifdef CONFIG_PDC202XX_BURST | |
349 | if (!(udma_speed_flag & 1)) { | |
350 | printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", | |
351 | hwif->cds->name, udma_speed_flag, | |
352 | (udma_speed_flag|1)); | |
0ecdca26 BZ |
353 | outb(udma_speed_flag | 1, dmabase | 0x1f); |
354 | printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); | |
1da177e4 LT |
355 | } |
356 | #endif /* CONFIG_PDC202XX_BURST */ | |
1da177e4 LT |
357 | |
358 | ide_setup_dma(hwif, dmabase, 8); | |
359 | } | |
360 | ||
97f84baa BZ |
361 | static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, |
362 | const char *name) | |
1da177e4 LT |
363 | { |
364 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { | |
365 | u8 irq = 0, irq2 = 0; | |
366 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
367 | /* 0xbc */ | |
368 | pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); | |
369 | if (irq != irq2) { | |
370 | pci_write_config_byte(dev, | |
371 | (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ | |
97f84baa BZ |
372 | printk(KERN_INFO "%s: PCI config space interrupt " |
373 | "mirror fixed\n", name); | |
1da177e4 LT |
374 | } |
375 | } | |
1da177e4 LT |
376 | } |
377 | ||
272a3709 | 378 | #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \ |
5ef8cb5d BZ |
379 | { \ |
380 | .name = name_str, \ | |
381 | .init_chipset = init_chipset_pdc202xx, \ | |
382 | .init_hwif = init_hwif_pdc202xx, \ | |
383 | .init_dma = init_dma_pdc202xx, \ | |
384 | .extra = 48, \ | |
ed67b923 | 385 | .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | \ |
272a3709 | 386 | extra_flags | \ |
ed67b923 | 387 | IDE_HFLAG_OFF_BOARD, \ |
5ef8cb5d BZ |
388 | .pio_mask = ATA_PIO4, \ |
389 | .mwdma_mask = ATA_MWDMA2, \ | |
390 | .udma_mask = udma, \ | |
391 | } | |
392 | ||
85620436 | 393 | static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { |
1da177e4 LT |
394 | { /* 0 */ |
395 | .name = "PDC20246", | |
1da177e4 LT |
396 | .init_chipset = init_chipset_pdc202xx, |
397 | .init_hwif = init_hwif_pdc202xx, | |
398 | .init_dma = init_dma_pdc202xx, | |
1da177e4 | 399 | .extra = 16, |
ed67b923 BZ |
400 | .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | |
401 | IDE_HFLAG_OFF_BOARD, | |
4099d143 | 402 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
403 | .mwdma_mask = ATA_MWDMA2, |
404 | .udma_mask = ATA_UDMA2, | |
5ef8cb5d BZ |
405 | }, |
406 | ||
272a3709 BZ |
407 | /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0), |
408 | /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0), | |
409 | /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256), | |
410 | /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256), | |
1da177e4 LT |
411 | }; |
412 | ||
413 | /** | |
414 | * pdc202xx_init_one - called when a PDC202xx is found | |
415 | * @dev: the pdc202xx device | |
416 | * @id: the matching pci id | |
417 | * | |
418 | * Called when the PCI registration layer (or the IDE initialization) | |
419 | * finds a device matching our IDE device tables. | |
420 | */ | |
421 | ||
422 | static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
423 | { | |
85620436 | 424 | const struct ide_port_info *d; |
97f84baa BZ |
425 | u8 idx = id->driver_data; |
426 | ||
427 | d = &pdc202xx_chipsets[idx]; | |
428 | ||
429 | if (idx < 3) | |
430 | pdc202ata4_fixup_irq(dev, d->name); | |
431 | ||
432 | if (idx == 3) { | |
433 | struct pci_dev *bridge = dev->bus->self; | |
1da177e4 | 434 | |
97f84baa BZ |
435 | if (bridge && |
436 | bridge->vendor == PCI_VENDOR_ID_INTEL && | |
437 | (bridge->device == PCI_DEVICE_ID_INTEL_I960 || | |
438 | bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { | |
439 | printk(KERN_INFO "ide: Skipping Promise PDC20265 " | |
440 | "attached to I2O RAID controller\n"); | |
441 | return -ENODEV; | |
442 | } | |
443 | } | |
444 | ||
445 | return ide_setup_pci_device(dev, d); | |
1da177e4 LT |
446 | } |
447 | ||
9cbcc5e3 BZ |
448 | static const struct pci_device_id pdc202xx_pci_tbl[] = { |
449 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, | |
450 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, | |
451 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 }, | |
452 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 }, | |
453 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 }, | |
1da177e4 LT |
454 | { 0, }, |
455 | }; | |
456 | MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); | |
457 | ||
458 | static struct pci_driver driver = { | |
459 | .name = "Promise_Old_IDE", | |
460 | .id_table = pdc202xx_pci_tbl, | |
461 | .probe = pdc202xx_init_one, | |
462 | }; | |
463 | ||
82ab1eec | 464 | static int __init pdc202xx_ide_init(void) |
1da177e4 LT |
465 | { |
466 | return ide_pci_register_driver(&driver); | |
467 | } | |
468 | ||
469 | module_init(pdc202xx_ide_init); | |
470 | ||
471 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); | |
472 | MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); | |
473 | MODULE_LICENSE("GPL"); |