Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
7207626f | 2 | * linux/drivers/ide/pci/piix.c Version 0.50 Jun 10, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
07af4276 | 7 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
44854add | 11 | * PIO mode setting function for Intel chipsets. |
1da177e4 LT |
12 | * For use instead of BIOS settings. |
13 | * | |
14 | * 40-41 | |
15 | * 42-43 | |
16 | * | |
17 | * 41 | |
18 | * 43 | |
19 | * | |
20 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); | |
21 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); | |
22 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); | |
23 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); | |
24 | * | |
25 | * sitre = word40 & 0x4000; primary | |
26 | * sitre = word42 & 0x4000; secondary | |
27 | * | |
28 | * 44 8421|8421 hdd|hdb | |
44854add | 29 | * |
1da177e4 LT |
30 | * 48 8421 hdd|hdc|hdb|hda udma enabled |
31 | * | |
32 | * 0001 hda | |
33 | * 0010 hdb | |
34 | * 0100 hdc | |
35 | * 1000 hdd | |
36 | * | |
37 | * 4a 84|21 hdb|hda | |
38 | * 4b 84|21 hdd|hdc | |
39 | * | |
40 | * ata-33/82371AB | |
41 | * ata-33/82371EB | |
42 | * ata-33/82801AB ata-66/82801AA | |
43 | * 00|00 udma 0 00|00 reserved | |
44 | * 01|01 udma 1 01|01 udma 3 | |
45 | * 10|10 udma 2 10|10 udma 4 | |
46 | * 11|11 reserved 11|11 reserved | |
47 | * | |
48 | * 54 8421|8421 ata66 drive|ata66 enable | |
49 | * | |
50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); | |
51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); | |
52 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); | |
53 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); | |
54 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); | |
55 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); | |
56 | * | |
57 | * Documentation | |
58 | * Publically available from Intel web site. Errata documentation | |
59 | * is also publically available. As an aide to anyone hacking on this | |
60 | * driver the list of errata that are relevant is below.going back to | |
61 | * PIIX4. Older device documentation is now a bit tricky to find. | |
62 | * | |
63 | * Errata of note: | |
64 | * | |
65 | * Unfixable | |
66 | * PIIX4 errata #9 - Only on ultra obscure hw | |
67 | * ICH3 errata #13 - Not observed to affect real hw | |
68 | * by Intel | |
69 | * | |
70 | * Things we must deal with | |
71 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
72 | * (must stop/start dma to recover) | |
73 | * 440MX errata #15 - As PIIX4 errata #10 | |
74 | * PIIX4 errata #15 - Must not read control registers | |
75 | * during a PIO transfer | |
76 | * 440MX errata #13 - As PIIX4 errata #15 | |
77 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
78 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
79 | * ICH2 spec c #9 - Extra operations needed to handle | |
80 | * drive hotswap [NOT YET SUPPORTED] | |
81 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
82 | * and must be dword aligned | |
83 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
84 | * | |
85 | * Should have been BIOS fixed: | |
86 | * 450NX: errata #19 - DMA hangs on old 450NX | |
87 | * 450NX: errata #20 - DMA hangs on old 450NX | |
88 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
89 | * ICH3 errata #15 - IDE deadlock under high load | |
90 | * (BIOS must set dev 31 fn 0 bit 23) | |
91 | * ICH3 errata #18 - Don't use native mode | |
92 | */ | |
93 | ||
1da177e4 LT |
94 | #include <linux/types.h> |
95 | #include <linux/module.h> | |
96 | #include <linux/kernel.h> | |
97 | #include <linux/ioport.h> | |
98 | #include <linux/pci.h> | |
99 | #include <linux/hdreg.h> | |
100 | #include <linux/ide.h> | |
101 | #include <linux/delay.h> | |
102 | #include <linux/init.h> | |
103 | ||
104 | #include <asm/io.h> | |
105 | ||
106 | static int no_piix_dma; | |
107 | ||
1da177e4 LT |
108 | /** |
109 | * piix_dma_2_pio - return the PIO mode matching DMA | |
110 | * @xfer_rate: transfer speed | |
111 | * | |
112 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
113 | * mode requested by the controller. | |
114 | */ | |
115 | ||
116 | static u8 piix_dma_2_pio (u8 xfer_rate) { | |
117 | switch(xfer_rate) { | |
118 | case XFER_UDMA_6: | |
119 | case XFER_UDMA_5: | |
120 | case XFER_UDMA_4: | |
121 | case XFER_UDMA_3: | |
122 | case XFER_UDMA_2: | |
123 | case XFER_UDMA_1: | |
124 | case XFER_UDMA_0: | |
125 | case XFER_MW_DMA_2: | |
126 | case XFER_PIO_4: | |
127 | return 4; | |
128 | case XFER_MW_DMA_1: | |
129 | case XFER_PIO_3: | |
130 | return 3; | |
131 | case XFER_SW_DMA_2: | |
132 | case XFER_PIO_2: | |
133 | return 2; | |
134 | case XFER_MW_DMA_0: | |
135 | case XFER_SW_DMA_1: | |
136 | case XFER_SW_DMA_0: | |
137 | case XFER_PIO_1: | |
138 | case XFER_PIO_0: | |
139 | case XFER_PIO_SLOW: | |
140 | default: | |
141 | return 0; | |
142 | } | |
143 | } | |
144 | ||
145 | /** | |
07af4276 | 146 | * piix_tune_pio - tune PIIX for PIO mode |
1da177e4 LT |
147 | * @drive: drive to tune |
148 | * @pio: desired PIO mode | |
149 | * | |
07af4276 | 150 | * Set the interface PIO mode based upon the settings done by AMI BIOS. |
1da177e4 | 151 | */ |
07af4276 | 152 | static void piix_tune_pio (ide_drive_t *drive, u8 pio) |
1da177e4 LT |
153 | { |
154 | ide_hwif_t *hwif = HWIF(drive); | |
155 | struct pci_dev *dev = hwif->pci_dev; | |
30dfd12f | 156 | int is_slave = drive->dn & 1; |
1da177e4 LT |
157 | int master_port = hwif->channel ? 0x42 : 0x40; |
158 | int slave_port = 0x44; | |
159 | unsigned long flags; | |
160 | u16 master_data; | |
161 | u8 slave_data; | |
4fb0f76d | 162 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 163 | int control = 0; |
4fb0f76d | 164 | |
30dfd12f | 165 | /* ISP RTC */ |
5ac24697 AC |
166 | static const u8 timings[][2]= { |
167 | { 0, 0 }, | |
168 | { 0, 0 }, | |
169 | { 1, 0 }, | |
170 | { 2, 1 }, | |
171 | { 2, 3 }, }; | |
1da177e4 | 172 | |
4fb0f76d AC |
173 | /* |
174 | * Master vs slave is synchronized above us but the slave register is | |
175 | * shared by the two hwifs so the corner case of two slave timeouts in | |
176 | * parallel must be locked. | |
177 | */ | |
178 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 179 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 | 180 | |
30dfd12f | 181 | if (pio > 1) |
5ac24697 AC |
182 | control |= 1; /* Programmable timing on */ |
183 | if (drive->media == ide_disk) | |
184 | control |= 4; /* Prefetch, post write */ | |
30dfd12f | 185 | if (pio > 2) |
5ac24697 | 186 | control |= 2; /* IORDY */ |
1da177e4 | 187 | if (is_slave) { |
30dfd12f SS |
188 | master_data |= 0x4000; |
189 | master_data &= ~0x0070; | |
5ac24697 | 190 | if (pio > 1) { |
07af4276 SS |
191 | /* Set PPE, IE and TIME */ |
192 | master_data |= control << 4; | |
5ac24697 | 193 | } |
1da177e4 | 194 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
195 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
196 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
197 | (hwif->channel ? 4 : 0); | |
1da177e4 | 198 | } else { |
30dfd12f | 199 | master_data &= ~0x3307; |
5ac24697 | 200 | if (pio > 1) { |
1da177e4 | 201 | /* enable PPE, IE and TIME */ |
07af4276 | 202 | master_data |= control; |
5ac24697 | 203 | } |
07af4276 | 204 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
205 | } |
206 | pci_write_config_word(dev, master_port, master_data); | |
207 | if (is_slave) | |
208 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 209 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
210 | } |
211 | ||
07af4276 SS |
212 | /** |
213 | * piix_tune_drive - tune a drive attached to PIIX | |
214 | * @drive: drive to tune | |
215 | * @pio: desired PIO mode | |
216 | * | |
217 | * Set the drive's PIO mode (might be useful if drive is not registered | |
218 | * in CMOS for any reason). | |
219 | */ | |
220 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) | |
221 | { | |
2134758d | 222 | pio = ide_get_best_pio_mode(drive, pio, 4); |
07af4276 SS |
223 | piix_tune_pio(drive, pio); |
224 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
225 | } | |
226 | ||
1da177e4 LT |
227 | /** |
228 | * piix_tune_chipset - tune a PIIX interface | |
229 | * @drive: IDE drive to tune | |
230 | * @xferspeed: speed to configure | |
231 | * | |
232 | * Set a PIIX interface channel to the desired speeds. This involves | |
233 | * requires the right timing data into the PIIX configuration space | |
234 | * then setting the drive parameters appropriately | |
235 | */ | |
236 | ||
237 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
238 | { | |
239 | ide_hwif_t *hwif = HWIF(drive); | |
240 | struct pci_dev *dev = hwif->pci_dev; | |
241 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
2d5eaa6d | 242 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
243 | int a_speed = 3 << (drive->dn * 4); |
244 | int u_flag = 1 << drive->dn; | |
245 | int v_flag = 0x01 << drive->dn; | |
246 | int w_flag = 0x10 << drive->dn; | |
247 | int u_speed = 0; | |
248 | int sitre; | |
249 | u16 reg4042, reg4a; | |
250 | u8 reg48, reg54, reg55; | |
251 | ||
252 | pci_read_config_word(dev, maslave, ®4042); | |
253 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
254 | pci_read_config_byte(dev, 0x48, ®48); | |
255 | pci_read_config_word(dev, 0x4a, ®4a); | |
256 | pci_read_config_byte(dev, 0x54, ®54); | |
257 | pci_read_config_byte(dev, 0x55, ®55); | |
258 | ||
259 | switch(speed) { | |
260 | case XFER_UDMA_4: | |
261 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
262 | case XFER_UDMA_5: | |
263 | case XFER_UDMA_3: | |
264 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
265 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
266 | case XFER_MW_DMA_2: | |
267 | case XFER_MW_DMA_1: | |
268 | case XFER_SW_DMA_2: break; | |
269 | case XFER_PIO_4: | |
270 | case XFER_PIO_3: | |
271 | case XFER_PIO_2: | |
272 | case XFER_PIO_0: break; | |
273 | default: return -1; | |
274 | } | |
275 | ||
276 | if (speed >= XFER_UDMA_0) { | |
277 | if (!(reg48 & u_flag)) | |
278 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
279 | if (speed == XFER_UDMA_5) { | |
280 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
281 | } else { | |
282 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
283 | } | |
284 | if ((reg4a & a_speed) != u_speed) | |
285 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
286 | if (speed > XFER_UDMA_2) { | |
287 | if (!(reg54 & v_flag)) | |
288 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
289 | } else | |
290 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
291 | } else { | |
292 | if (reg48 & u_flag) | |
293 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
294 | if (reg4a & a_speed) | |
295 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
296 | if (reg54 & v_flag) | |
297 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
298 | if (reg55 & w_flag) | |
299 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
300 | } | |
301 | ||
07af4276 SS |
302 | piix_tune_pio(drive, piix_dma_2_pio(speed)); |
303 | return ide_config_drive_speed(drive, speed); | |
1da177e4 LT |
304 | } |
305 | ||
1da177e4 LT |
306 | /** |
307 | * piix_config_drive_xfer_rate - set up an IDE device | |
308 | * @drive: IDE drive to configure | |
309 | * | |
310 | * Set up the PIIX interface for the best available speed on this | |
311 | * interface, preferring DMA to PIO. | |
312 | */ | |
313 | ||
314 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) | |
315 | { | |
1da177e4 LT |
316 | drive->init_speed = 0; |
317 | ||
29e744d0 | 318 | if (ide_tune_dma(drive)) |
3608b5d7 | 319 | return 0; |
1da177e4 | 320 | |
d8f4469d | 321 | if (ide_use_fast_pio(drive)) |
07af4276 | 322 | piix_tune_drive(drive, 255); |
d8f4469d | 323 | |
3608b5d7 | 324 | return -1; |
1da177e4 LT |
325 | } |
326 | ||
327 | /** | |
f0dd8712 AL |
328 | * piix_is_ichx - check if ICHx |
329 | * @dev: PCI device to check | |
1da177e4 | 330 | * |
f0dd8712 | 331 | * returns 1 if ICHx, 0 otherwise. |
1da177e4 | 332 | */ |
f0dd8712 | 333 | static int piix_is_ichx(struct pci_dev *dev) |
1da177e4 | 334 | { |
f0dd8712 | 335 | switch (dev->device) { |
1da177e4 LT |
336 | case PCI_DEVICE_ID_INTEL_82801EB_1: |
337 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
338 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
339 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
340 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
341 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
342 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
343 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
344 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
345 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
346 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
347 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
348 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
349 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
350 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 351 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 352 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
f0dd8712 | 353 | return 1; |
1da177e4 LT |
354 | } |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
f0dd8712 AL |
359 | /** |
360 | * init_chipset_piix - set up the PIIX chipset | |
361 | * @dev: PCI device to set up | |
362 | * @name: Name of the device | |
363 | * | |
364 | * Initialize the PCI device as required. For the PIIX this turns | |
365 | * out to be nice and simple | |
366 | */ | |
367 | ||
368 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) | |
369 | { | |
370 | if (piix_is_ichx(dev)) { | |
371 | unsigned int extra = 0; | |
372 | pci_read_config_dword(dev, 0x54, &extra); | |
373 | pci_write_config_dword(dev, 0x54, extra|0x400); | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | /** | |
380 | * piix_dma_clear_irq - clear BMDMA status | |
381 | * @drive: IDE drive to clear | |
382 | * | |
383 | * Called from ide_intr() for PIO interrupts | |
384 | * to clear BMDMA status as needed by ICHx | |
385 | */ | |
386 | static void piix_dma_clear_irq(ide_drive_t *drive) | |
387 | { | |
388 | ide_hwif_t *hwif = HWIF(drive); | |
389 | u8 dma_stat; | |
390 | ||
391 | /* clear the INTR & ERROR bits */ | |
392 | dma_stat = hwif->INB(hwif->dma_status); | |
393 | /* Should we force the bit as well ? */ | |
394 | hwif->OUTB(dma_stat, hwif->dma_status); | |
395 | } | |
396 | ||
7207626f BZ |
397 | struct ich_laptop { |
398 | u16 device; | |
399 | u16 subvendor; | |
400 | u16 subdevice; | |
401 | }; | |
402 | ||
403 | /* | |
404 | * List of laptops that use short cables rather than 80 wire | |
405 | */ | |
406 | ||
407 | static const struct ich_laptop ich_laptop[] = { | |
408 | /* devid, subvendor, subdev */ | |
409 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
410 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ | |
411 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ | |
412 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */ | |
413 | /* end marker */ | |
414 | { 0, } | |
415 | }; | |
416 | ||
49521f97 | 417 | static u8 __devinit piix_cable_detect(ide_hwif_t *hwif) |
74594fd1 | 418 | { |
7207626f BZ |
419 | struct pci_dev *pdev = hwif->pci_dev; |
420 | const struct ich_laptop *lap = &ich_laptop[0]; | |
74594fd1 BZ |
421 | u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; |
422 | ||
7207626f BZ |
423 | /* check for specials */ |
424 | while (lap->device) { | |
425 | if (lap->device == pdev->device && | |
426 | lap->subvendor == pdev->subsystem_vendor && | |
427 | lap->subdevice == pdev->subsystem_device) { | |
428 | return ATA_CBL_PATA40_SHORT; | |
429 | } | |
430 | lap++; | |
431 | } | |
432 | ||
433 | pci_read_config_byte(pdev, 0x54, ®54h); | |
74594fd1 | 434 | |
49521f97 | 435 | return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
74594fd1 BZ |
436 | } |
437 | ||
1da177e4 LT |
438 | /** |
439 | * init_hwif_piix - fill in the hwif for the PIIX | |
440 | * @hwif: IDE interface | |
441 | * | |
442 | * Set up the ide_hwif_t for the PIIX interface according to the | |
443 | * capabilities of the hardware. | |
444 | */ | |
445 | ||
446 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
447 | { | |
1da177e4 LT |
448 | #ifndef CONFIG_IA64 |
449 | if (!hwif->irq) | |
450 | hwif->irq = hwif->channel ? 15 : 14; | |
451 | #endif /* CONFIG_IA64 */ | |
452 | ||
453 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { | |
454 | /* This is a painful system best to let it self tune for now */ | |
455 | return; | |
456 | } | |
457 | ||
458 | hwif->autodma = 0; | |
459 | hwif->tuneproc = &piix_tune_drive; | |
460 | hwif->speedproc = &piix_tune_chipset; | |
461 | hwif->drives[0].autotune = 1; | |
462 | hwif->drives[1].autotune = 1; | |
463 | ||
464 | if (!hwif->dma_base) | |
465 | return; | |
466 | ||
f0dd8712 AL |
467 | /* ICHx need to clear the bmdma status for all interrupts */ |
468 | if (piix_is_ichx(hwif->pci_dev)) | |
469 | hwif->ide_dma_clear_irq = &piix_dma_clear_irq; | |
470 | ||
1da177e4 | 471 | hwif->atapi_dma = 1; |
18137207 BZ |
472 | |
473 | hwif->ultra_mask = hwif->cds->udma_mask; | |
1da177e4 LT |
474 | hwif->mwdma_mask = 0x06; |
475 | hwif->swdma_mask = 0x04; | |
476 | ||
18137207 | 477 | if (hwif->ultra_mask & 0x78) { |
49521f97 BZ |
478 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
479 | hwif->cbl = piix_cable_detect(hwif); | |
1da177e4 LT |
480 | } |
481 | ||
74594fd1 BZ |
482 | if (no_piix_dma) |
483 | hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; | |
484 | ||
1da177e4 LT |
485 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; |
486 | if (!noautodma) | |
487 | hwif->autodma = 1; | |
488 | ||
489 | hwif->drives[1].autodma = hwif->autodma; | |
490 | hwif->drives[0].autodma = hwif->autodma; | |
491 | } | |
492 | ||
18137207 | 493 | #define DECLARE_PIIX_DEV(name_str, udma) \ |
1da177e4 LT |
494 | { \ |
495 | .name = name_str, \ | |
496 | .init_chipset = init_chipset_piix, \ | |
497 | .init_hwif = init_hwif_piix, \ | |
1da177e4 LT |
498 | .autodma = AUTODMA, \ |
499 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
500 | .bootable = ON_BOARD, \ | |
18137207 | 501 | .udma_mask = udma, \ |
1da177e4 LT |
502 | } |
503 | ||
504 | static ide_pci_device_t piix_pci_info[] __devinitdata = { | |
18137207 BZ |
505 | /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */ |
506 | /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */ | |
1da177e4 | 507 | |
d2872239 SS |
508 | /* 2 */ |
509 | { /* | |
510 | * MPIIX actually has only a single IDE channel mapped to | |
511 | * the primary or secondary ports depending on the value | |
512 | * of the bit 14 of the IDETIM register at offset 0x6c | |
513 | */ | |
1da177e4 LT |
514 | .name = "MPIIX", |
515 | .init_hwif = init_hwif_piix, | |
1da177e4 | 516 | .autodma = NODMA, |
d2872239 | 517 | .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, |
1da177e4 | 518 | .bootable = ON_BOARD, |
a5d8c5c8 | 519 | .host_flags = IDE_HFLAG_ISA_PORTS, |
1da177e4 LT |
520 | }, |
521 | ||
18137207 BZ |
522 | /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */ |
523 | /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ | |
524 | /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */ | |
525 | /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ | |
526 | /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */ | |
527 | /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */ | |
528 | /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ | |
529 | /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */ | |
530 | /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */ | |
531 | /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */ | |
532 | /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */ | |
533 | /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ | |
534 | /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */ | |
535 | /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */ | |
536 | /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ | |
537 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */ | |
538 | /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */ | |
539 | /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */ | |
540 | /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */ | |
541 | /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ | |
542 | /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */ | |
543 | /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */ | |
1da177e4 LT |
544 | }; |
545 | ||
546 | /** | |
547 | * piix_init_one - called when a PIIX is found | |
548 | * @dev: the piix device | |
549 | * @id: the matching pci id | |
550 | * | |
551 | * Called when the PCI registration layer (or the IDE initialization) | |
552 | * finds a device matching our IDE device tables. | |
553 | */ | |
554 | ||
555 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
556 | { | |
557 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; | |
558 | ||
559 | return ide_setup_pci_device(dev, d); | |
560 | } | |
561 | ||
562 | /** | |
563 | * piix_check_450nx - Check for problem 450NX setup | |
564 | * | |
565 | * Check for the present of 450NX errata #19 and errata #25. If | |
566 | * they are found, disable use of DMA IDE | |
567 | */ | |
568 | ||
569 | static void __devinit piix_check_450nx(void) | |
570 | { | |
571 | struct pci_dev *pdev = NULL; | |
572 | u16 cfg; | |
1424e504 | 573 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
574 | { |
575 | /* Look for 450NX PXB. Check for problem configurations | |
576 | A PCI quirk checks bit 6 already */ | |
1da177e4 LT |
577 | pci_read_config_word(pdev, 0x41, &cfg); |
578 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 579 | if (pdev->revision == 0x00) |
1da177e4 LT |
580 | no_piix_dma = 1; |
581 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 582 | else if (cfg & (1<<14) && pdev->revision < 5) |
1da177e4 LT |
583 | no_piix_dma = 2; |
584 | } | |
585 | if(no_piix_dma) | |
586 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); | |
587 | if(no_piix_dma == 2) | |
588 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); | |
589 | } | |
590 | ||
591 | static struct pci_device_id piix_pci_tbl[] = { | |
592 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
593 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
594 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
595 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
596 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
597 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
598 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, | |
599 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, | |
600 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, | |
601 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, | |
602 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, | |
603 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, | |
604 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, | |
605 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, | |
606 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, | |
607 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, | |
608 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, | |
609 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, | |
610 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
611 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, | |
612 | #endif | |
613 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, | |
614 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, | |
615 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, | |
616 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, | |
d69332b8 | 617 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
b7bed9ec | 618 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
1da177e4 LT |
619 | { 0, }, |
620 | }; | |
621 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
622 | ||
623 | static struct pci_driver driver = { | |
624 | .name = "PIIX_IDE", | |
625 | .id_table = piix_pci_tbl, | |
626 | .probe = piix_init_one, | |
627 | }; | |
628 | ||
629 | static int __init piix_ide_init(void) | |
630 | { | |
631 | piix_check_450nx(); | |
632 | return ide_pci_register_driver(&driver); | |
633 | } | |
634 | ||
635 | module_init(piix_ide_init); | |
636 | ||
637 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
638 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
639 | MODULE_LICENSE("GPL"); |