Commit | Line | Data |
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1da177e4 | 1 | /* |
30dfd12f | 2 | * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
44854add | 7 | * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
44854add | 11 | * PIO mode setting function for Intel chipsets. |
1da177e4 LT |
12 | * For use instead of BIOS settings. |
13 | * | |
14 | * 40-41 | |
15 | * 42-43 | |
16 | * | |
17 | * 41 | |
18 | * 43 | |
19 | * | |
20 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); | |
21 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); | |
22 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); | |
23 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); | |
24 | * | |
25 | * sitre = word40 & 0x4000; primary | |
26 | * sitre = word42 & 0x4000; secondary | |
27 | * | |
28 | * 44 8421|8421 hdd|hdb | |
44854add | 29 | * |
1da177e4 LT |
30 | * 48 8421 hdd|hdc|hdb|hda udma enabled |
31 | * | |
32 | * 0001 hda | |
33 | * 0010 hdb | |
34 | * 0100 hdc | |
35 | * 1000 hdd | |
36 | * | |
37 | * 4a 84|21 hdb|hda | |
38 | * 4b 84|21 hdd|hdc | |
39 | * | |
40 | * ata-33/82371AB | |
41 | * ata-33/82371EB | |
42 | * ata-33/82801AB ata-66/82801AA | |
43 | * 00|00 udma 0 00|00 reserved | |
44 | * 01|01 udma 1 01|01 udma 3 | |
45 | * 10|10 udma 2 10|10 udma 4 | |
46 | * 11|11 reserved 11|11 reserved | |
47 | * | |
48 | * 54 8421|8421 ata66 drive|ata66 enable | |
49 | * | |
50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); | |
51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); | |
52 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); | |
53 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); | |
54 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); | |
55 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); | |
56 | * | |
57 | * Documentation | |
58 | * Publically available from Intel web site. Errata documentation | |
59 | * is also publically available. As an aide to anyone hacking on this | |
60 | * driver the list of errata that are relevant is below.going back to | |
61 | * PIIX4. Older device documentation is now a bit tricky to find. | |
62 | * | |
63 | * Errata of note: | |
64 | * | |
65 | * Unfixable | |
66 | * PIIX4 errata #9 - Only on ultra obscure hw | |
67 | * ICH3 errata #13 - Not observed to affect real hw | |
68 | * by Intel | |
69 | * | |
70 | * Things we must deal with | |
71 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
72 | * (must stop/start dma to recover) | |
73 | * 440MX errata #15 - As PIIX4 errata #10 | |
74 | * PIIX4 errata #15 - Must not read control registers | |
75 | * during a PIO transfer | |
76 | * 440MX errata #13 - As PIIX4 errata #15 | |
77 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
78 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
79 | * ICH2 spec c #9 - Extra operations needed to handle | |
80 | * drive hotswap [NOT YET SUPPORTED] | |
81 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
82 | * and must be dword aligned | |
83 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
84 | * | |
85 | * Should have been BIOS fixed: | |
86 | * 450NX: errata #19 - DMA hangs on old 450NX | |
87 | * 450NX: errata #20 - DMA hangs on old 450NX | |
88 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
89 | * ICH3 errata #15 - IDE deadlock under high load | |
90 | * (BIOS must set dev 31 fn 0 bit 23) | |
91 | * ICH3 errata #18 - Don't use native mode | |
92 | */ | |
93 | ||
1da177e4 LT |
94 | #include <linux/types.h> |
95 | #include <linux/module.h> | |
96 | #include <linux/kernel.h> | |
97 | #include <linux/ioport.h> | |
98 | #include <linux/pci.h> | |
99 | #include <linux/hdreg.h> | |
100 | #include <linux/ide.h> | |
101 | #include <linux/delay.h> | |
102 | #include <linux/init.h> | |
103 | ||
104 | #include <asm/io.h> | |
105 | ||
106 | static int no_piix_dma; | |
107 | ||
108 | /** | |
109 | * piix_ratemask - compute rate mask for PIIX IDE | |
110 | * @drive: IDE drive to compute for | |
111 | * | |
112 | * Returns the available modes for the PIIX IDE controller. | |
113 | */ | |
114 | ||
115 | static u8 piix_ratemask (ide_drive_t *drive) | |
116 | { | |
117 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
118 | u8 mode; | |
119 | ||
120 | switch(dev->device) { | |
121 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
122 | mode = 3; | |
123 | break; | |
124 | /* UDMA 100 capable */ | |
125 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
126 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
127 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
128 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
129 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
130 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
131 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
132 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
133 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
134 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
135 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
136 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 137 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 138 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
1da177e4 LT |
139 | mode = 3; |
140 | break; | |
141 | /* UDMA 66 capable */ | |
142 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
143 | case PCI_DEVICE_ID_INTEL_82372FB_1: | |
144 | mode = 2; | |
145 | break; | |
146 | /* UDMA 33 capable */ | |
147 | case PCI_DEVICE_ID_INTEL_82371AB: | |
148 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
149 | case PCI_DEVICE_ID_INTEL_82451NX: | |
150 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
151 | return 1; | |
152 | /* Non UDMA capable (MWDMA2) */ | |
153 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
154 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
155 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
156 | case PCI_DEVICE_ID_INTEL_82371MX: | |
157 | default: | |
158 | return 0; | |
159 | } | |
160 | ||
161 | /* | |
162 | * If we are UDMA66 capable fall back to UDMA33 | |
163 | * if the drive cannot see an 80pin cable. | |
164 | */ | |
165 | if (!eighty_ninty_three(drive)) | |
30dfd12f | 166 | mode = min_t(u8, mode, 1); |
1da177e4 LT |
167 | return mode; |
168 | } | |
169 | ||
170 | /** | |
171 | * piix_dma_2_pio - return the PIO mode matching DMA | |
172 | * @xfer_rate: transfer speed | |
173 | * | |
174 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
175 | * mode requested by the controller. | |
176 | */ | |
177 | ||
178 | static u8 piix_dma_2_pio (u8 xfer_rate) { | |
179 | switch(xfer_rate) { | |
180 | case XFER_UDMA_6: | |
181 | case XFER_UDMA_5: | |
182 | case XFER_UDMA_4: | |
183 | case XFER_UDMA_3: | |
184 | case XFER_UDMA_2: | |
185 | case XFER_UDMA_1: | |
186 | case XFER_UDMA_0: | |
187 | case XFER_MW_DMA_2: | |
188 | case XFER_PIO_4: | |
189 | return 4; | |
190 | case XFER_MW_DMA_1: | |
191 | case XFER_PIO_3: | |
192 | return 3; | |
193 | case XFER_SW_DMA_2: | |
194 | case XFER_PIO_2: | |
195 | return 2; | |
196 | case XFER_MW_DMA_0: | |
197 | case XFER_SW_DMA_1: | |
198 | case XFER_SW_DMA_0: | |
199 | case XFER_PIO_1: | |
200 | case XFER_PIO_0: | |
201 | case XFER_PIO_SLOW: | |
202 | default: | |
203 | return 0; | |
204 | } | |
205 | } | |
206 | ||
207 | /** | |
208 | * piix_tune_drive - tune a drive attached to a PIIX | |
209 | * @drive: drive to tune | |
210 | * @pio: desired PIO mode | |
211 | * | |
212 | * Set the interface PIO mode based upon the settings done by AMI BIOS | |
213 | * (might be useful if drive is not registered in CMOS for any reason). | |
214 | */ | |
215 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) | |
216 | { | |
217 | ide_hwif_t *hwif = HWIF(drive); | |
218 | struct pci_dev *dev = hwif->pci_dev; | |
30dfd12f | 219 | int is_slave = drive->dn & 1; |
1da177e4 LT |
220 | int master_port = hwif->channel ? 0x42 : 0x40; |
221 | int slave_port = 0x44; | |
222 | unsigned long flags; | |
223 | u16 master_data; | |
224 | u8 slave_data; | |
4fb0f76d | 225 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 226 | int control = 0; |
4fb0f76d | 227 | |
30dfd12f | 228 | /* ISP RTC */ |
5ac24697 AC |
229 | static const u8 timings[][2]= { |
230 | { 0, 0 }, | |
231 | { 0, 0 }, | |
232 | { 1, 0 }, | |
233 | { 2, 1 }, | |
234 | { 2, 3 }, }; | |
1da177e4 | 235 | |
30dfd12f | 236 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
4fb0f76d AC |
237 | |
238 | /* | |
239 | * Master vs slave is synchronized above us but the slave register is | |
240 | * shared by the two hwifs so the corner case of two slave timeouts in | |
241 | * parallel must be locked. | |
242 | */ | |
243 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 244 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 | 245 | |
30dfd12f | 246 | if (pio > 1) |
5ac24697 AC |
247 | control |= 1; /* Programmable timing on */ |
248 | if (drive->media == ide_disk) | |
249 | control |= 4; /* Prefetch, post write */ | |
30dfd12f | 250 | if (pio > 2) |
5ac24697 | 251 | control |= 2; /* IORDY */ |
1da177e4 | 252 | if (is_slave) { |
30dfd12f SS |
253 | master_data |= 0x4000; |
254 | master_data &= ~0x0070; | |
5ac24697 | 255 | if (pio > 1) { |
1da177e4 | 256 | /* enable PPE, IE and TIME */ |
5ac24697 | 257 | master_data = master_data | (control << 4); |
5ac24697 | 258 | } |
1da177e4 LT |
259 | pci_read_config_byte(dev, slave_port, &slave_data); |
260 | slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); | |
261 | slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); | |
262 | } else { | |
30dfd12f | 263 | master_data &= ~0x3307; |
5ac24697 | 264 | if (pio > 1) { |
1da177e4 | 265 | /* enable PPE, IE and TIME */ |
5ac24697 AC |
266 | master_data = master_data | control; |
267 | } | |
1da177e4 LT |
268 | master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); |
269 | } | |
270 | pci_write_config_word(dev, master_port, master_data); | |
271 | if (is_slave) | |
272 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 273 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
274 | } |
275 | ||
276 | /** | |
277 | * piix_tune_chipset - tune a PIIX interface | |
278 | * @drive: IDE drive to tune | |
279 | * @xferspeed: speed to configure | |
280 | * | |
281 | * Set a PIIX interface channel to the desired speeds. This involves | |
282 | * requires the right timing data into the PIIX configuration space | |
283 | * then setting the drive parameters appropriately | |
284 | */ | |
285 | ||
286 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
287 | { | |
288 | ide_hwif_t *hwif = HWIF(drive); | |
289 | struct pci_dev *dev = hwif->pci_dev; | |
290 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
291 | u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); | |
292 | int a_speed = 3 << (drive->dn * 4); | |
293 | int u_flag = 1 << drive->dn; | |
294 | int v_flag = 0x01 << drive->dn; | |
295 | int w_flag = 0x10 << drive->dn; | |
296 | int u_speed = 0; | |
297 | int sitre; | |
298 | u16 reg4042, reg4a; | |
299 | u8 reg48, reg54, reg55; | |
300 | ||
301 | pci_read_config_word(dev, maslave, ®4042); | |
302 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
303 | pci_read_config_byte(dev, 0x48, ®48); | |
304 | pci_read_config_word(dev, 0x4a, ®4a); | |
305 | pci_read_config_byte(dev, 0x54, ®54); | |
306 | pci_read_config_byte(dev, 0x55, ®55); | |
307 | ||
308 | switch(speed) { | |
309 | case XFER_UDMA_4: | |
310 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
311 | case XFER_UDMA_5: | |
312 | case XFER_UDMA_3: | |
313 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
314 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
315 | case XFER_MW_DMA_2: | |
316 | case XFER_MW_DMA_1: | |
317 | case XFER_SW_DMA_2: break; | |
318 | case XFER_PIO_4: | |
319 | case XFER_PIO_3: | |
320 | case XFER_PIO_2: | |
321 | case XFER_PIO_0: break; | |
322 | default: return -1; | |
323 | } | |
324 | ||
325 | if (speed >= XFER_UDMA_0) { | |
326 | if (!(reg48 & u_flag)) | |
327 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
328 | if (speed == XFER_UDMA_5) { | |
329 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
330 | } else { | |
331 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
332 | } | |
333 | if ((reg4a & a_speed) != u_speed) | |
334 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
335 | if (speed > XFER_UDMA_2) { | |
336 | if (!(reg54 & v_flag)) | |
337 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
338 | } else | |
339 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
340 | } else { | |
341 | if (reg48 & u_flag) | |
342 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
343 | if (reg4a & a_speed) | |
344 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
345 | if (reg54 & v_flag) | |
346 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
347 | if (reg55 & w_flag) | |
348 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
349 | } | |
350 | ||
351 | piix_tune_drive(drive, piix_dma_2_pio(speed)); | |
352 | return (ide_config_drive_speed(drive, speed)); | |
353 | } | |
354 | ||
1da177e4 LT |
355 | /** |
356 | * piix_config_drive_for_dma - configure drive for DMA | |
357 | * @drive: IDE drive to configure | |
358 | * | |
359 | * Set up a PIIX interface channel for the best available speed. | |
44854add SS |
360 | * We prefer UDMA if it is available and then MWDMA. If DMA is |
361 | * not available we switch to PIO and return 0. | |
1da177e4 LT |
362 | */ |
363 | ||
364 | static int piix_config_drive_for_dma (ide_drive_t *drive) | |
365 | { | |
366 | u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); | |
1da177e4 | 367 | |
44854add SS |
368 | /* |
369 | * If no DMA speed was available or the chipset has DMA bugs | |
370 | * then disable DMA and use PIO | |
371 | */ | |
74594fd1 | 372 | if (!speed) |
44854add | 373 | return 0; |
1da177e4 LT |
374 | |
375 | (void) piix_tune_chipset(drive, speed); | |
376 | return ide_dma_enable(drive); | |
377 | } | |
378 | ||
379 | /** | |
380 | * piix_config_drive_xfer_rate - set up an IDE device | |
381 | * @drive: IDE drive to configure | |
382 | * | |
383 | * Set up the PIIX interface for the best available speed on this | |
384 | * interface, preferring DMA to PIO. | |
385 | */ | |
386 | ||
387 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) | |
388 | { | |
1da177e4 LT |
389 | drive->init_speed = 0; |
390 | ||
7569e8dc | 391 | if (ide_use_dma(drive) && piix_config_drive_for_dma(drive)) |
3608b5d7 | 392 | return 0; |
1da177e4 | 393 | |
d8f4469d | 394 | if (ide_use_fast_pio(drive)) |
1da177e4 | 395 | /* Find best PIO mode. */ |
3608b5d7 BZ |
396 | piix_tune_chipset(drive, XFER_PIO_0 + |
397 | ide_get_best_pio_mode(drive, 255, 4, NULL)); | |
d8f4469d | 398 | |
3608b5d7 | 399 | return -1; |
1da177e4 LT |
400 | } |
401 | ||
402 | /** | |
f0dd8712 AL |
403 | * piix_is_ichx - check if ICHx |
404 | * @dev: PCI device to check | |
1da177e4 | 405 | * |
f0dd8712 | 406 | * returns 1 if ICHx, 0 otherwise. |
1da177e4 | 407 | */ |
f0dd8712 | 408 | static int piix_is_ichx(struct pci_dev *dev) |
1da177e4 | 409 | { |
f0dd8712 | 410 | switch (dev->device) { |
1da177e4 LT |
411 | case PCI_DEVICE_ID_INTEL_82801EB_1: |
412 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
413 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
414 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
415 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
416 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
417 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
418 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
419 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
420 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
421 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
422 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
423 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
424 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
425 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 426 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 427 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
f0dd8712 | 428 | return 1; |
1da177e4 LT |
429 | } |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
f0dd8712 AL |
434 | /** |
435 | * init_chipset_piix - set up the PIIX chipset | |
436 | * @dev: PCI device to set up | |
437 | * @name: Name of the device | |
438 | * | |
439 | * Initialize the PCI device as required. For the PIIX this turns | |
440 | * out to be nice and simple | |
441 | */ | |
442 | ||
443 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) | |
444 | { | |
445 | if (piix_is_ichx(dev)) { | |
446 | unsigned int extra = 0; | |
447 | pci_read_config_dword(dev, 0x54, &extra); | |
448 | pci_write_config_dword(dev, 0x54, extra|0x400); | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | /** | |
455 | * piix_dma_clear_irq - clear BMDMA status | |
456 | * @drive: IDE drive to clear | |
457 | * | |
458 | * Called from ide_intr() for PIO interrupts | |
459 | * to clear BMDMA status as needed by ICHx | |
460 | */ | |
461 | static void piix_dma_clear_irq(ide_drive_t *drive) | |
462 | { | |
463 | ide_hwif_t *hwif = HWIF(drive); | |
464 | u8 dma_stat; | |
465 | ||
466 | /* clear the INTR & ERROR bits */ | |
467 | dma_stat = hwif->INB(hwif->dma_status); | |
468 | /* Should we force the bit as well ? */ | |
469 | hwif->OUTB(dma_stat, hwif->dma_status); | |
470 | } | |
471 | ||
74594fd1 BZ |
472 | static int __devinit piix_cable_detect(ide_hwif_t *hwif) |
473 | { | |
474 | struct pci_dev *dev = hwif->pci_dev; | |
475 | u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; | |
476 | ||
477 | pci_read_config_byte(dev, 0x54, ®54h); | |
478 | ||
479 | return (reg54h & mask) ? 1 : 0; | |
480 | } | |
481 | ||
1da177e4 LT |
482 | /** |
483 | * init_hwif_piix - fill in the hwif for the PIIX | |
484 | * @hwif: IDE interface | |
485 | * | |
486 | * Set up the ide_hwif_t for the PIIX interface according to the | |
487 | * capabilities of the hardware. | |
488 | */ | |
489 | ||
490 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
491 | { | |
1da177e4 LT |
492 | #ifndef CONFIG_IA64 |
493 | if (!hwif->irq) | |
494 | hwif->irq = hwif->channel ? 15 : 14; | |
495 | #endif /* CONFIG_IA64 */ | |
496 | ||
497 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { | |
498 | /* This is a painful system best to let it self tune for now */ | |
499 | return; | |
500 | } | |
501 | ||
502 | hwif->autodma = 0; | |
503 | hwif->tuneproc = &piix_tune_drive; | |
504 | hwif->speedproc = &piix_tune_chipset; | |
505 | hwif->drives[0].autotune = 1; | |
506 | hwif->drives[1].autotune = 1; | |
507 | ||
508 | if (!hwif->dma_base) | |
509 | return; | |
510 | ||
f0dd8712 AL |
511 | /* ICHx need to clear the bmdma status for all interrupts */ |
512 | if (piix_is_ichx(hwif->pci_dev)) | |
513 | hwif->ide_dma_clear_irq = &piix_dma_clear_irq; | |
514 | ||
1da177e4 LT |
515 | hwif->atapi_dma = 1; |
516 | hwif->ultra_mask = 0x3f; | |
517 | hwif->mwdma_mask = 0x06; | |
518 | hwif->swdma_mask = 0x04; | |
519 | ||
520 | switch(hwif->pci_dev->device) { | |
1da177e4 LT |
521 | case PCI_DEVICE_ID_INTEL_82371FB_0: |
522 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
523 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
524 | hwif->ultra_mask = 0x80; | |
525 | break; | |
526 | case PCI_DEVICE_ID_INTEL_82371AB: | |
527 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
528 | case PCI_DEVICE_ID_INTEL_82451NX: | |
529 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
530 | hwif->ultra_mask = 0x07; | |
531 | break; | |
532 | default: | |
74594fd1 BZ |
533 | if (!hwif->udma_four) |
534 | hwif->udma_four = piix_cable_detect(hwif); | |
1da177e4 LT |
535 | break; |
536 | } | |
537 | ||
74594fd1 BZ |
538 | if (no_piix_dma) |
539 | hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; | |
540 | ||
1da177e4 LT |
541 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; |
542 | if (!noautodma) | |
543 | hwif->autodma = 1; | |
544 | ||
545 | hwif->drives[1].autodma = hwif->autodma; | |
546 | hwif->drives[0].autodma = hwif->autodma; | |
547 | } | |
548 | ||
549 | #define DECLARE_PIIX_DEV(name_str) \ | |
550 | { \ | |
551 | .name = name_str, \ | |
552 | .init_chipset = init_chipset_piix, \ | |
553 | .init_hwif = init_hwif_piix, \ | |
554 | .channels = 2, \ | |
555 | .autodma = AUTODMA, \ | |
556 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
557 | .bootable = ON_BOARD, \ | |
558 | } | |
559 | ||
560 | static ide_pci_device_t piix_pci_info[] __devinitdata = { | |
561 | /* 0 */ DECLARE_PIIX_DEV("PIIXa"), | |
562 | /* 1 */ DECLARE_PIIX_DEV("PIIXb"), | |
563 | ||
d2872239 SS |
564 | /* 2 */ |
565 | { /* | |
566 | * MPIIX actually has only a single IDE channel mapped to | |
567 | * the primary or secondary ports depending on the value | |
568 | * of the bit 14 of the IDETIM register at offset 0x6c | |
569 | */ | |
1da177e4 LT |
570 | .name = "MPIIX", |
571 | .init_hwif = init_hwif_piix, | |
572 | .channels = 2, | |
573 | .autodma = NODMA, | |
d2872239 | 574 | .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, |
1da177e4 | 575 | .bootable = ON_BOARD, |
d2872239 | 576 | .flags = IDEPCI_FLAG_ISA_PORTS |
1da177e4 LT |
577 | }, |
578 | ||
579 | /* 3 */ DECLARE_PIIX_DEV("PIIX3"), | |
580 | /* 4 */ DECLARE_PIIX_DEV("PIIX4"), | |
581 | /* 5 */ DECLARE_PIIX_DEV("ICH0"), | |
582 | /* 6 */ DECLARE_PIIX_DEV("PIIX4"), | |
583 | /* 7 */ DECLARE_PIIX_DEV("ICH"), | |
584 | /* 8 */ DECLARE_PIIX_DEV("PIIX4"), | |
585 | /* 9 */ DECLARE_PIIX_DEV("PIIX4"), | |
586 | /* 10 */ DECLARE_PIIX_DEV("ICH2"), | |
587 | /* 11 */ DECLARE_PIIX_DEV("ICH2M"), | |
588 | /* 12 */ DECLARE_PIIX_DEV("ICH3M"), | |
589 | /* 13 */ DECLARE_PIIX_DEV("ICH3"), | |
590 | /* 14 */ DECLARE_PIIX_DEV("ICH4"), | |
591 | /* 15 */ DECLARE_PIIX_DEV("ICH5"), | |
592 | /* 16 */ DECLARE_PIIX_DEV("C-ICH"), | |
593 | /* 17 */ DECLARE_PIIX_DEV("ICH4"), | |
594 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), | |
595 | /* 19 */ DECLARE_PIIX_DEV("ICH5"), | |
596 | /* 20 */ DECLARE_PIIX_DEV("ICH6"), | |
597 | /* 21 */ DECLARE_PIIX_DEV("ICH7"), | |
598 | /* 22 */ DECLARE_PIIX_DEV("ICH4"), | |
d69332b8 | 599 | /* 23 */ DECLARE_PIIX_DEV("ESB2"), |
b7bed9ec | 600 | /* 24 */ DECLARE_PIIX_DEV("ICH8M"), |
1da177e4 LT |
601 | }; |
602 | ||
603 | /** | |
604 | * piix_init_one - called when a PIIX is found | |
605 | * @dev: the piix device | |
606 | * @id: the matching pci id | |
607 | * | |
608 | * Called when the PCI registration layer (or the IDE initialization) | |
609 | * finds a device matching our IDE device tables. | |
610 | */ | |
611 | ||
612 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
613 | { | |
614 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; | |
615 | ||
616 | return ide_setup_pci_device(dev, d); | |
617 | } | |
618 | ||
619 | /** | |
620 | * piix_check_450nx - Check for problem 450NX setup | |
621 | * | |
622 | * Check for the present of 450NX errata #19 and errata #25. If | |
623 | * they are found, disable use of DMA IDE | |
624 | */ | |
625 | ||
626 | static void __devinit piix_check_450nx(void) | |
627 | { | |
628 | struct pci_dev *pdev = NULL; | |
629 | u16 cfg; | |
630 | u8 rev; | |
1424e504 | 631 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
632 | { |
633 | /* Look for 450NX PXB. Check for problem configurations | |
634 | A PCI quirk checks bit 6 already */ | |
635 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
636 | pci_read_config_word(pdev, 0x41, &cfg); | |
637 | /* Only on the original revision: IDE DMA can hang */ | |
638 | if(rev == 0x00) | |
639 | no_piix_dma = 1; | |
640 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
641 | else if(cfg & (1<<14) && rev < 5) | |
642 | no_piix_dma = 2; | |
643 | } | |
644 | if(no_piix_dma) | |
645 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); | |
646 | if(no_piix_dma == 2) | |
647 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); | |
648 | } | |
649 | ||
650 | static struct pci_device_id piix_pci_tbl[] = { | |
651 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
652 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
653 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
654 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
655 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
656 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
657 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, | |
658 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, | |
659 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, | |
660 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, | |
661 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, | |
662 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, | |
663 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, | |
664 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, | |
665 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, | |
666 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, | |
667 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, | |
668 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, | |
669 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
670 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, | |
671 | #endif | |
672 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, | |
673 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, | |
674 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, | |
675 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, | |
d69332b8 | 676 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
b7bed9ec | 677 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
1da177e4 LT |
678 | { 0, }, |
679 | }; | |
680 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
681 | ||
682 | static struct pci_driver driver = { | |
683 | .name = "PIIX_IDE", | |
684 | .id_table = piix_pci_tbl, | |
685 | .probe = piix_init_one, | |
686 | }; | |
687 | ||
688 | static int __init piix_ide_init(void) | |
689 | { | |
690 | piix_check_450nx(); | |
691 | return ide_pci_register_driver(&driver); | |
692 | } | |
693 | ||
694 | module_init(piix_ide_init); | |
695 | ||
696 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
697 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
698 | MODULE_LICENSE("GPL"); |