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bde18a2e KI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ide/pci/siimage.c: | |
7 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
8 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23 | */ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/hdreg.h> | |
30 | #include <linux/ide.h> | |
31 | #include <linux/init.h> | |
32 | ||
33 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
34 | ||
35 | #define SCC_PATA_NAME "scc IDE" | |
36 | ||
37 | #define TDVHSEL_MASTER 0x00000001 | |
38 | #define TDVHSEL_SLAVE 0x00000004 | |
39 | ||
40 | #define MODE_JCUSFEN 0x00000080 | |
41 | ||
42 | #define CCKCTRL_ATARESET 0x00040000 | |
43 | #define CCKCTRL_BUFCNT 0x00020000 | |
44 | #define CCKCTRL_CRST 0x00010000 | |
45 | #define CCKCTRL_OCLKEN 0x00000100 | |
46 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
47 | #define CCKCTRL_LCLKEN 0x00000001 | |
48 | ||
49 | #define QCHCD_IOS_SS 0x00000001 | |
50 | ||
51 | #define QCHSD_STPDIAG 0x00020000 | |
52 | ||
53 | #define INTMASK_MSK 0xD1000012 | |
54 | #define INTSTS_SERROR 0x80000000 | |
55 | #define INTSTS_PRERR 0x40000000 | |
56 | #define INTSTS_RERR 0x10000000 | |
57 | #define INTSTS_ICERR 0x01000000 | |
58 | #define INTSTS_BMSINT 0x00000010 | |
59 | #define INTSTS_BMHE 0x00000008 | |
60 | #define INTSTS_IOIRQS 0x00000004 | |
61 | #define INTSTS_INTRQ 0x00000002 | |
62 | #define INTSTS_ACTEINT 0x00000001 | |
63 | ||
64 | #define ECMODE_VALUE 0x01 | |
65 | ||
66 | static struct scc_ports { | |
67 | unsigned long ctl, dma; | |
589b0626 | 68 | ide_hwif_t *hwif; /* for removing port from system */ |
bde18a2e KI |
69 | } scc_ports[MAX_HWIFS]; |
70 | ||
71 | /* PIO transfer mode table */ | |
72 | /* JCHST */ | |
73 | static unsigned long JCHSTtbl[2][7] = { | |
74 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
75 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
76 | }; | |
77 | ||
78 | /* JCHHT */ | |
79 | static unsigned long JCHHTtbl[2][7] = { | |
80 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
81 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
82 | }; | |
83 | ||
84 | /* JCHCT */ | |
85 | static unsigned long JCHCTtbl[2][7] = { | |
86 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
87 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
88 | }; | |
89 | ||
90 | ||
91 | /* DMA transfer mode table */ | |
92 | /* JCHDCTM/JCHDCTS */ | |
93 | static unsigned long JCHDCTxtbl[2][7] = { | |
94 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
95 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
96 | }; | |
97 | ||
98 | /* JCSTWTM/JCSTWTS */ | |
99 | static unsigned long JCSTWTxtbl[2][7] = { | |
100 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
101 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
102 | }; | |
103 | ||
104 | /* JCTSS */ | |
105 | static unsigned long JCTSStbl[2][7] = { | |
106 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
107 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
108 | }; | |
109 | ||
110 | /* JCENVT */ | |
111 | static unsigned long JCENVTtbl[2][7] = { | |
112 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
113 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
114 | }; | |
115 | ||
116 | /* JCACTSELS/JCACTSELM */ | |
117 | static unsigned long JCACTSELtbl[2][7] = { | |
118 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
119 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
120 | }; | |
121 | ||
122 | ||
123 | static u8 scc_ide_inb(unsigned long port) | |
124 | { | |
125 | u32 data = in_be32((void*)port); | |
126 | return (u8)data; | |
127 | } | |
128 | ||
129 | static u16 scc_ide_inw(unsigned long port) | |
130 | { | |
131 | u32 data = in_be32((void*)port); | |
132 | return (u16)data; | |
133 | } | |
134 | ||
bde18a2e KI |
135 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) |
136 | { | |
137 | u16 *ptr = (u16 *)addr; | |
138 | while (count--) { | |
139 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
140 | } | |
141 | } | |
142 | ||
143 | static void scc_ide_insl(unsigned long port, void *addr, u32 count) | |
144 | { | |
145 | u16 *ptr = (u16 *)addr; | |
146 | while (count--) { | |
147 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
148 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
149 | } | |
150 | } | |
151 | ||
152 | static void scc_ide_outb(u8 addr, unsigned long port) | |
153 | { | |
154 | out_be32((void*)port, addr); | |
155 | } | |
156 | ||
157 | static void scc_ide_outw(u16 addr, unsigned long port) | |
158 | { | |
159 | out_be32((void*)port, addr); | |
160 | } | |
161 | ||
bde18a2e KI |
162 | static void |
163 | scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) | |
164 | { | |
165 | ide_hwif_t *hwif = HWIF(drive); | |
166 | ||
167 | out_be32((void*)port, addr); | |
f644d47a | 168 | eieio(); |
bde18a2e | 169 | in_be32((void*)(hwif->dma_base + 0x01c)); |
f644d47a | 170 | eieio(); |
bde18a2e KI |
171 | } |
172 | ||
173 | static void | |
174 | scc_ide_outsw(unsigned long port, void *addr, u32 count) | |
175 | { | |
176 | u16 *ptr = (u16 *)addr; | |
177 | while (count--) { | |
178 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
179 | } | |
180 | } | |
181 | ||
182 | static void | |
183 | scc_ide_outsl(unsigned long port, void *addr, u32 count) | |
184 | { | |
185 | u16 *ptr = (u16 *)addr; | |
186 | while (count--) { | |
187 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
188 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
189 | } | |
190 | } | |
191 | ||
bde18a2e | 192 | /** |
88b2b32b BZ |
193 | * scc_set_pio_mode - set host controller for PIO mode |
194 | * @drive: drive | |
195 | * @pio: PIO mode number | |
bde18a2e KI |
196 | * |
197 | * Load the timing settings for this device mode into the | |
198 | * controller. | |
199 | */ | |
200 | ||
88b2b32b | 201 | static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) |
bde18a2e KI |
202 | { |
203 | ide_hwif_t *hwif = HWIF(drive); | |
204 | struct scc_ports *ports = ide_get_hwifdata(hwif); | |
205 | unsigned long ctl_base = ports->ctl; | |
206 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
207 | unsigned long piosht_port = ctl_base + 0x000; | |
208 | unsigned long pioct_port = ctl_base + 0x004; | |
209 | unsigned long reg; | |
bde18a2e KI |
210 | int offset; |
211 | ||
0ecdca26 | 212 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
213 | if (reg & CCKCTRL_ATACLKOEN) { |
214 | offset = 1; /* 133MHz */ | |
215 | } else { | |
216 | offset = 0; /* 100MHz */ | |
217 | } | |
3fcece66 | 218 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; |
0ecdca26 | 219 | out_be32((void __iomem *)piosht_port, reg); |
3fcece66 | 220 | reg = JCHCTtbl[offset][pio]; |
0ecdca26 | 221 | out_be32((void __iomem *)pioct_port, reg); |
3fcece66 | 222 | } |
bde18a2e | 223 | |
bde18a2e | 224 | /** |
88b2b32b BZ |
225 | * scc_set_dma_mode - set host controller for DMA mode |
226 | * @drive: drive | |
227 | * @speed: DMA mode | |
bde18a2e KI |
228 | * |
229 | * Load the timing settings for this device mode into the | |
230 | * controller. | |
231 | */ | |
232 | ||
88b2b32b | 233 | static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) |
bde18a2e KI |
234 | { |
235 | ide_hwif_t *hwif = HWIF(drive); | |
bde18a2e KI |
236 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
237 | unsigned long ctl_base = ports->ctl; | |
238 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
239 | unsigned long mdmact_port = ctl_base + 0x008; | |
240 | unsigned long mcrcst_port = ctl_base + 0x00c; | |
241 | unsigned long sdmact_port = ctl_base + 0x010; | |
242 | unsigned long scrcst_port = ctl_base + 0x014; | |
243 | unsigned long udenvt_port = ctl_base + 0x018; | |
244 | unsigned long tdvhsel_port = ctl_base + 0x020; | |
245 | int is_slave = (&hwif->drives[1] == drive); | |
246 | int offset, idx; | |
247 | unsigned long reg; | |
248 | unsigned long jcactsel; | |
249 | ||
0ecdca26 | 250 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
251 | if (reg & CCKCTRL_ATACLKOEN) { |
252 | offset = 1; /* 133MHz */ | |
253 | } else { | |
254 | offset = 0; /* 100MHz */ | |
255 | } | |
256 | ||
4db90a14 | 257 | idx = speed - XFER_UDMA_0; |
bde18a2e KI |
258 | |
259 | jcactsel = JCACTSELtbl[offset][idx]; | |
260 | if (is_slave) { | |
0ecdca26 BZ |
261 | out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); |
262 | out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); | |
263 | jcactsel = jcactsel << 2; | |
264 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); | |
bde18a2e | 265 | } else { |
0ecdca26 BZ |
266 | out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); |
267 | out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); | |
268 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); | |
bde18a2e KI |
269 | } |
270 | reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; | |
0ecdca26 | 271 | out_be32((void __iomem *)udenvt_port, reg); |
bde18a2e KI |
272 | } |
273 | ||
0ecdca26 BZ |
274 | /** |
275 | * scc_ide_dma_setup - begin a DMA phase | |
276 | * @drive: target device | |
277 | * | |
278 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
279 | * and then set up the DMA transfer registers. | |
280 | * | |
281 | * Returns 0 on success. If a PIO fallback is required then 1 | |
282 | * is returned. | |
283 | */ | |
284 | ||
285 | static int scc_dma_setup(ide_drive_t *drive) | |
286 | { | |
287 | ide_hwif_t *hwif = drive->hwif; | |
288 | struct request *rq = HWGROUP(drive)->rq; | |
289 | unsigned int reading; | |
290 | u8 dma_stat; | |
291 | ||
292 | if (rq_data_dir(rq)) | |
293 | reading = 0; | |
294 | else | |
295 | reading = 1 << 3; | |
296 | ||
297 | /* fall back to pio! */ | |
298 | if (!ide_build_dmatable(drive, rq)) { | |
299 | ide_map_sg(drive, rq); | |
300 | return 1; | |
301 | } | |
302 | ||
303 | /* PRD table */ | |
304 | out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma); | |
305 | ||
306 | /* specify r/w */ | |
307 | out_be32((void __iomem *)hwif->dma_command, reading); | |
308 | ||
309 | /* read dma_status for INTR & ERROR flags */ | |
310 | dma_stat = in_be32((void __iomem *)hwif->dma_status); | |
311 | ||
312 | /* clear INTR & ERROR flags */ | |
313 | out_be32((void __iomem *)hwif->dma_status, dma_stat|6); | |
314 | drive->waiting_for_dma = 1; | |
315 | return 0; | |
316 | } | |
317 | ||
318 | ||
bde18a2e KI |
319 | /** |
320 | * scc_ide_dma_end - Stop DMA | |
321 | * @drive: IDE drive | |
322 | * | |
323 | * Check and clear INT Status register. | |
324 | * Then call __ide_dma_end(). | |
325 | */ | |
326 | ||
327 | static int scc_ide_dma_end(ide_drive_t * drive) | |
328 | { | |
329 | ide_hwif_t *hwif = HWIF(drive); | |
330 | unsigned long intsts_port = hwif->dma_base + 0x014; | |
331 | u32 reg; | |
4ae41ff8 KI |
332 | int dma_stat, data_loss = 0; |
333 | static int retry = 0; | |
334 | ||
335 | /* errata A308 workaround: Step5 (check data loss) */ | |
336 | /* We don't check non ide_disk because it is limited to UDMA4 */ | |
23579a2a BZ |
337 | if (!(in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) |
338 | & ERR_STAT) && | |
4ae41ff8 KI |
339 | drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { |
340 | reg = in_be32((void __iomem *)intsts_port); | |
341 | if (!(reg & INTSTS_ACTEINT)) { | |
342 | printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", | |
343 | drive->name); | |
344 | data_loss = 1; | |
345 | if (retry++) { | |
346 | struct request *rq = HWGROUP(drive)->rq; | |
347 | int unit; | |
348 | /* ERROR_RESET and drive->crc_count are needed | |
349 | * to reduce DMA transfer mode in retry process. | |
350 | */ | |
351 | if (rq) | |
352 | rq->errors |= ERROR_RESET; | |
353 | for (unit = 0; unit < MAX_DRIVES; unit++) { | |
354 | ide_drive_t *drive = &hwif->drives[unit]; | |
355 | drive->crc_count++; | |
356 | } | |
357 | } | |
358 | } | |
359 | } | |
bde18a2e KI |
360 | |
361 | while (1) { | |
0ecdca26 | 362 | reg = in_be32((void __iomem *)intsts_port); |
bde18a2e KI |
363 | |
364 | if (reg & INTSTS_SERROR) { | |
365 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); | |
0ecdca26 | 366 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
bde18a2e | 367 | |
0ecdca26 | 368 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
369 | continue; |
370 | } | |
371 | ||
372 | if (reg & INTSTS_PRERR) { | |
373 | u32 maea0, maec0; | |
374 | unsigned long ctl_base = hwif->config_data; | |
375 | ||
0ecdca26 BZ |
376 | maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); |
377 | maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); | |
bde18a2e KI |
378 | |
379 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); | |
380 | ||
0ecdca26 | 381 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
bde18a2e | 382 | |
0ecdca26 | 383 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
384 | continue; |
385 | } | |
386 | ||
387 | if (reg & INTSTS_RERR) { | |
388 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); | |
0ecdca26 | 389 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
bde18a2e | 390 | |
0ecdca26 | 391 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
392 | continue; |
393 | } | |
394 | ||
395 | if (reg & INTSTS_ICERR) { | |
0ecdca26 | 396 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
397 | |
398 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); | |
0ecdca26 | 399 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
bde18a2e KI |
400 | continue; |
401 | } | |
402 | ||
403 | if (reg & INTSTS_BMSINT) { | |
404 | printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); | |
0ecdca26 | 405 | out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); |
bde18a2e KI |
406 | |
407 | ide_do_reset(drive); | |
408 | continue; | |
409 | } | |
410 | ||
411 | if (reg & INTSTS_BMHE) { | |
0ecdca26 | 412 | out_be32((void __iomem *)intsts_port, INTSTS_BMHE); |
bde18a2e KI |
413 | continue; |
414 | } | |
415 | ||
416 | if (reg & INTSTS_ACTEINT) { | |
0ecdca26 | 417 | out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); |
bde18a2e KI |
418 | continue; |
419 | } | |
420 | ||
421 | if (reg & INTSTS_IOIRQS) { | |
0ecdca26 | 422 | out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); |
bde18a2e KI |
423 | continue; |
424 | } | |
425 | break; | |
426 | } | |
427 | ||
4ae41ff8 KI |
428 | dma_stat = __ide_dma_end(drive); |
429 | if (data_loss) | |
430 | dma_stat |= 2; /* emulate DMA error (to retry command) */ | |
431 | return dma_stat; | |
bde18a2e KI |
432 | } |
433 | ||
06a9952b AI |
434 | /* returns 1 if dma irq issued, 0 otherwise */ |
435 | static int scc_dma_test_irq(ide_drive_t *drive) | |
436 | { | |
4ae41ff8 KI |
437 | ide_hwif_t *hwif = HWIF(drive); |
438 | u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); | |
06a9952b | 439 | |
4ae41ff8 | 440 | /* SCC errata A252,A308 workaround: Step4 */ |
23579a2a BZ |
441 | if ((in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) |
442 | & ERR_STAT) && | |
4ae41ff8 | 443 | (int_stat & INTSTS_INTRQ)) |
06a9952b AI |
444 | return 1; |
445 | ||
4ae41ff8 KI |
446 | /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ |
447 | if (int_stat & INTSTS_IOIRQS) | |
06a9952b AI |
448 | return 1; |
449 | ||
450 | if (!drive->waiting_for_dma) | |
451 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
452 | drive->name, __FUNCTION__); | |
453 | return 0; | |
454 | } | |
455 | ||
4ae41ff8 KI |
456 | static u8 scc_udma_filter(ide_drive_t *drive) |
457 | { | |
458 | ide_hwif_t *hwif = drive->hwif; | |
459 | u8 mask = hwif->ultra_mask; | |
460 | ||
461 | /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ | |
462 | if ((drive->media != ide_disk) && (mask & 0xE0)) { | |
463 | printk(KERN_INFO "%s: limit %s to UDMA4\n", | |
464 | SCC_PATA_NAME, drive->name); | |
5f8b6c34 | 465 | mask = ATA_UDMA4; |
4ae41ff8 KI |
466 | } |
467 | ||
468 | return mask; | |
469 | } | |
470 | ||
bde18a2e KI |
471 | /** |
472 | * setup_mmio_scc - map CTRL/BMID region | |
473 | * @dev: PCI device we are configuring | |
474 | * @name: device name | |
475 | * | |
476 | */ | |
477 | ||
478 | static int setup_mmio_scc (struct pci_dev *dev, const char *name) | |
479 | { | |
480 | unsigned long ctl_base = pci_resource_start(dev, 0); | |
481 | unsigned long dma_base = pci_resource_start(dev, 1); | |
482 | unsigned long ctl_size = pci_resource_len(dev, 0); | |
483 | unsigned long dma_size = pci_resource_len(dev, 1); | |
0bd8496b AV |
484 | void __iomem *ctl_addr; |
485 | void __iomem *dma_addr; | |
0d1bad21 | 486 | int i, ret; |
bde18a2e KI |
487 | |
488 | for (i = 0; i < MAX_HWIFS; i++) { | |
489 | if (scc_ports[i].ctl == 0) | |
490 | break; | |
491 | } | |
492 | if (i >= MAX_HWIFS) | |
493 | return -ENOMEM; | |
494 | ||
0d1bad21 BZ |
495 | ret = pci_request_selected_regions(dev, (1 << 2) - 1, name); |
496 | if (ret < 0) { | |
497 | printk(KERN_ERR "%s: can't reserve resources\n", name); | |
498 | return ret; | |
bde18a2e KI |
499 | } |
500 | ||
501 | if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL) | |
0d1bad21 | 502 | goto fail_0; |
bde18a2e KI |
503 | |
504 | if ((dma_addr = ioremap(dma_base, dma_size)) == NULL) | |
0d1bad21 | 505 | goto fail_1; |
bde18a2e KI |
506 | |
507 | pci_set_master(dev); | |
508 | scc_ports[i].ctl = (unsigned long)ctl_addr; | |
509 | scc_ports[i].dma = (unsigned long)dma_addr; | |
510 | pci_set_drvdata(dev, (void *) &scc_ports[i]); | |
511 | ||
512 | return 1; | |
513 | ||
bde18a2e | 514 | fail_1: |
0d1bad21 | 515 | iounmap(ctl_addr); |
bde18a2e KI |
516 | fail_0: |
517 | return -ENOMEM; | |
518 | } | |
519 | ||
3d53ba87 AI |
520 | static int scc_ide_setup_pci_device(struct pci_dev *dev, |
521 | const struct ide_port_info *d) | |
522 | { | |
523 | struct scc_ports *ports = pci_get_drvdata(dev); | |
524 | ide_hwif_t *hwif = NULL; | |
525 | hw_regs_t hw; | |
526 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | |
527 | int i; | |
528 | ||
3fd4d205 BZ |
529 | hwif = ide_find_port(); |
530 | if (hwif == NULL) { | |
3d53ba87 AI |
531 | printk(KERN_ERR "%s: too many IDE interfaces, " |
532 | "no room in table\n", SCC_PATA_NAME); | |
533 | return -ENOMEM; | |
534 | } | |
535 | ||
536 | memset(&hw, 0, sizeof(hw)); | |
537 | for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++) | |
538 | hw.io_ports[i] = ports->dma + 0x20 + i * 4; | |
539 | hw.irq = dev->irq; | |
540 | hw.dev = &dev->dev; | |
541 | hw.chipset = ide_pci; | |
542 | ide_init_port_hw(hwif, &hw); | |
543 | hwif->dev = &dev->dev; | |
544 | hwif->cds = d; | |
545 | ||
546 | idx[0] = hwif->index; | |
547 | ||
548 | ide_device_add(idx, d); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
bde18a2e KI |
553 | /** |
554 | * init_setup_scc - set up an SCC PATA Controller | |
555 | * @dev: PCI device | |
039788e1 | 556 | * @d: IDE port info |
bde18a2e KI |
557 | * |
558 | * Perform the initial set up for this device. | |
559 | */ | |
560 | ||
039788e1 | 561 | static int __devinit init_setup_scc(struct pci_dev *dev, |
85620436 | 562 | const struct ide_port_info *d) |
bde18a2e KI |
563 | { |
564 | unsigned long ctl_base; | |
565 | unsigned long dma_base; | |
566 | unsigned long cckctrl_port; | |
567 | unsigned long intmask_port; | |
568 | unsigned long mode_port; | |
569 | unsigned long ecmode_port; | |
570 | unsigned long dma_status_port; | |
571 | u32 reg = 0; | |
572 | struct scc_ports *ports; | |
573 | int rc; | |
574 | ||
3d53ba87 AI |
575 | rc = pci_enable_device(dev); |
576 | if (rc) | |
577 | goto end; | |
578 | ||
bde18a2e | 579 | rc = setup_mmio_scc(dev, d->name); |
3d53ba87 AI |
580 | if (rc < 0) |
581 | goto end; | |
bde18a2e KI |
582 | |
583 | ports = pci_get_drvdata(dev); | |
584 | ctl_base = ports->ctl; | |
585 | dma_base = ports->dma; | |
586 | cckctrl_port = ctl_base + 0xff0; | |
587 | intmask_port = dma_base + 0x010; | |
588 | mode_port = ctl_base + 0x024; | |
589 | ecmode_port = ctl_base + 0xf00; | |
590 | dma_status_port = dma_base + 0x004; | |
591 | ||
592 | /* controller initialization */ | |
593 | reg = 0; | |
594 | out_be32((void*)cckctrl_port, reg); | |
595 | reg |= CCKCTRL_ATACLKOEN; | |
596 | out_be32((void*)cckctrl_port, reg); | |
597 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
598 | out_be32((void*)cckctrl_port, reg); | |
599 | reg |= CCKCTRL_CRST; | |
600 | out_be32((void*)cckctrl_port, reg); | |
601 | ||
602 | for (;;) { | |
603 | reg = in_be32((void*)cckctrl_port); | |
604 | if (reg & CCKCTRL_CRST) | |
605 | break; | |
606 | udelay(5000); | |
607 | } | |
608 | ||
609 | reg |= CCKCTRL_ATARESET; | |
610 | out_be32((void*)cckctrl_port, reg); | |
611 | ||
612 | out_be32((void*)ecmode_port, ECMODE_VALUE); | |
613 | out_be32((void*)mode_port, MODE_JCUSFEN); | |
614 | out_be32((void*)intmask_port, INTMASK_MSK); | |
615 | ||
3d53ba87 AI |
616 | rc = scc_ide_setup_pci_device(dev, d); |
617 | ||
618 | end: | |
619 | return rc; | |
bde18a2e KI |
620 | } |
621 | ||
622 | /** | |
623 | * init_mmio_iops_scc - set up the iops for MMIO | |
624 | * @hwif: interface to set up | |
625 | * | |
626 | */ | |
627 | ||
628 | static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) | |
629 | { | |
36501650 | 630 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
bde18a2e KI |
631 | struct scc_ports *ports = pci_get_drvdata(dev); |
632 | unsigned long dma_base = ports->dma; | |
633 | ||
634 | ide_set_hwifdata(hwif, ports); | |
635 | ||
636 | hwif->INB = scc_ide_inb; | |
637 | hwif->INW = scc_ide_inw; | |
bde18a2e KI |
638 | hwif->INSW = scc_ide_insw; |
639 | hwif->INSL = scc_ide_insl; | |
640 | hwif->OUTB = scc_ide_outb; | |
641 | hwif->OUTBSYNC = scc_ide_outbsync; | |
642 | hwif->OUTW = scc_ide_outw; | |
bde18a2e KI |
643 | hwif->OUTSW = scc_ide_outsw; |
644 | hwif->OUTSL = scc_ide_outsl; | |
645 | ||
bde18a2e KI |
646 | hwif->dma_base = dma_base; |
647 | hwif->config_data = ports->ctl; | |
2ad1e558 | 648 | hwif->mmio = 1; |
bde18a2e KI |
649 | } |
650 | ||
651 | /** | |
652 | * init_iops_scc - set up iops | |
653 | * @hwif: interface to set up | |
654 | * | |
655 | * Do the basic setup for the SCC hardware interface | |
656 | * and then do the MMIO setup. | |
657 | */ | |
658 | ||
659 | static void __devinit init_iops_scc(ide_hwif_t *hwif) | |
660 | { | |
36501650 BZ |
661 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
662 | ||
bde18a2e KI |
663 | hwif->hwif_data = NULL; |
664 | if (pci_get_drvdata(dev) == NULL) | |
665 | return; | |
666 | init_mmio_iops_scc(hwif); | |
667 | } | |
668 | ||
b4d1c73d BZ |
669 | static u8 __devinit scc_cable_detect(ide_hwif_t *hwif) |
670 | { | |
671 | return ATA_CBL_PATA80; | |
672 | } | |
673 | ||
bde18a2e KI |
674 | /** |
675 | * init_hwif_scc - set up hwif | |
676 | * @hwif: interface to set up | |
677 | * | |
678 | * We do the basic set up of the interface structure. The SCC | |
679 | * requires several custom handlers so we override the default | |
680 | * ide DMA handlers appropriately. | |
681 | */ | |
682 | ||
683 | static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |
684 | { | |
685 | struct scc_ports *ports = ide_get_hwifdata(hwif); | |
686 | ||
589b0626 | 687 | ports->hwif = hwif; |
bde18a2e KI |
688 | |
689 | hwif->dma_command = hwif->dma_base; | |
690 | hwif->dma_status = hwif->dma_base + 0x04; | |
691 | hwif->dma_prdtable = hwif->dma_base + 0x08; | |
692 | ||
0ecdca26 BZ |
693 | /* PTERADD */ |
694 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); | |
bde18a2e | 695 | |
0ecdca26 | 696 | hwif->dma_setup = scc_dma_setup; |
bde18a2e | 697 | hwif->ide_dma_end = scc_ide_dma_end; |
06a9952b | 698 | hwif->ide_dma_test_irq = scc_dma_test_irq; |
bde18a2e | 699 | |
5f8b6c34 BZ |
700 | if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) |
701 | hwif->ultra_mask = ATA_UDMA6; /* 133MHz */ | |
702 | else | |
703 | hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ | |
bde18a2e KI |
704 | } |
705 | ||
ac95beed BZ |
706 | static const struct ide_port_ops scc_port_ops = { |
707 | .set_pio_mode = scc_set_pio_mode, | |
708 | .set_dma_mode = scc_set_dma_mode, | |
709 | .udma_filter = scc_udma_filter, | |
710 | .cable_detect = scc_cable_detect, | |
711 | }; | |
712 | ||
bde18a2e KI |
713 | #define DECLARE_SCC_DEV(name_str) \ |
714 | { \ | |
715 | .name = name_str, \ | |
bde18a2e KI |
716 | .init_iops = init_iops_scc, \ |
717 | .init_hwif = init_hwif_scc, \ | |
ac95beed | 718 | .port_ops = &scc_port_ops, \ |
5e71d9c5 | 719 | .host_flags = IDE_HFLAG_SINGLE, \ |
4099d143 | 720 | .pio_mask = ATA_PIO4, \ |
bde18a2e KI |
721 | } |
722 | ||
85620436 | 723 | static const struct ide_port_info scc_chipsets[] __devinitdata = { |
bde18a2e KI |
724 | /* 0 */ DECLARE_SCC_DEV("sccIDE"), |
725 | }; | |
726 | ||
727 | /** | |
728 | * scc_init_one - pci layer discovery entry | |
729 | * @dev: PCI device | |
730 | * @id: ident table entry | |
731 | * | |
732 | * Called by the PCI code when it finds an SCC PATA controller. | |
733 | * We then use the IDE PCI generic helper to do most of the work. | |
734 | */ | |
735 | ||
736 | static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
737 | { | |
039788e1 | 738 | return init_setup_scc(dev, &scc_chipsets[id->driver_data]); |
bde18a2e KI |
739 | } |
740 | ||
741 | /** | |
742 | * scc_remove - pci layer remove entry | |
743 | * @dev: PCI device | |
744 | * | |
745 | * Called by the PCI code when it removes an SCC PATA controller. | |
746 | */ | |
747 | ||
748 | static void __devexit scc_remove(struct pci_dev *dev) | |
749 | { | |
750 | struct scc_ports *ports = pci_get_drvdata(dev); | |
589b0626 | 751 | ide_hwif_t *hwif = ports->hwif; |
bde18a2e KI |
752 | |
753 | if (hwif->dmatable_cpu) { | |
36501650 BZ |
754 | pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES, |
755 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
bde18a2e KI |
756 | hwif->dmatable_cpu = NULL; |
757 | } | |
758 | ||
93de00fd | 759 | ide_unregister(hwif->index); |
bde18a2e KI |
760 | |
761 | hwif->chipset = ide_unknown; | |
762 | iounmap((void*)ports->dma); | |
763 | iounmap((void*)ports->ctl); | |
0d1bad21 | 764 | pci_release_selected_regions(dev, (1 << 2) - 1); |
bde18a2e KI |
765 | memset(ports, 0, sizeof(*ports)); |
766 | } | |
767 | ||
9cbcc5e3 BZ |
768 | static const struct pci_device_id scc_pci_tbl[] = { |
769 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 }, | |
bde18a2e KI |
770 | { 0, }, |
771 | }; | |
772 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
773 | ||
774 | static struct pci_driver driver = { | |
775 | .name = "SCC IDE", | |
776 | .id_table = scc_pci_tbl, | |
777 | .probe = scc_init_one, | |
778 | .remove = scc_remove, | |
779 | }; | |
780 | ||
781 | static int scc_ide_init(void) | |
782 | { | |
783 | return ide_pci_register_driver(&driver); | |
784 | } | |
785 | ||
786 | module_init(scc_ide_init); | |
787 | /* -- No exit code? | |
788 | static void scc_ide_exit(void) | |
789 | { | |
790 | ide_pci_unregister_driver(&driver); | |
791 | } | |
792 | module_exit(scc_ide_exit); | |
793 | */ | |
794 | ||
795 | ||
796 | MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); | |
797 | MODULE_LICENSE("GPL"); |