Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-2000 Michel Aubry |
3 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
4 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * Portions copyright (c) 2001 Sun Microsystems |
7 | * | |
8 | * | |
9 | * RCC/ServerWorks IDE driver for Linux | |
10 | * | |
11 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
12 | * supports UDMA mode 2 (33 MB/s) | |
13 | * | |
14 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
15 | * all revisions support UDMA mode 4 (66 MB/s) | |
16 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
17 | * | |
18 | * *** The CSB5 does not provide ANY register *** | |
19 | * *** to detect 80-conductor cable presence. *** | |
20 | * | |
21 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
22 | * | |
84f57fbc NS |
23 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
24 | * controller same as the CSB6. Single channel ATA100 only. | |
25 | * | |
1da177e4 LT |
26 | * Documentation: |
27 | * Available under NDA only. Errata info very hard to get. | |
28 | * | |
29 | */ | |
30 | ||
1da177e4 LT |
31 | #include <linux/types.h> |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
1da177e4 LT |
34 | #include <linux/pci.h> |
35 | #include <linux/hdreg.h> | |
36 | #include <linux/ide.h> | |
37 | #include <linux/init.h> | |
1da177e4 LT |
38 | |
39 | #include <asm/io.h> | |
40 | ||
ced3ec8a BZ |
41 | #define DRV_NAME "serverworks" |
42 | ||
1da177e4 LT |
43 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ |
44 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
45 | ||
46 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
47 | * can overrun their FIFOs when used with the CSB5 */ | |
48 | static const char *svwks_bad_ata100[] = { | |
49 | "ST320011A", | |
50 | "ST340016A", | |
51 | "ST360021A", | |
52 | "ST380021A", | |
53 | NULL | |
54 | }; | |
55 | ||
1da177e4 LT |
56 | static struct pci_dev *isa_dev; |
57 | ||
58 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
59 | { | |
60 | while (*list) | |
61 | if (!strcmp(*list++, drive->id->model)) | |
62 | return 1; | |
63 | return 0; | |
64 | } | |
65 | ||
2d5eaa6d | 66 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 | 67 | { |
36501650 | 68 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
2d5eaa6d | 69 | u8 mask = 0; |
1da177e4 | 70 | |
84f57fbc | 71 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 72 | return 0x1f; |
1da177e4 LT |
73 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
74 | u32 reg = 0; | |
75 | if (isa_dev) | |
76 | pci_read_config_dword(isa_dev, 0x64, ®); | |
77 | ||
78 | /* | |
79 | * Don't enable UDMA on disk devices for the moment | |
80 | */ | |
81 | if(drive->media == ide_disk) | |
82 | return 0; | |
83 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 84 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
44c10138 | 85 | } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 86 | return 0x07; |
44c10138 | 87 | } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 88 | u8 btr = 0, mode; |
1da177e4 LT |
89 | pci_read_config_byte(dev, 0x5A, &btr); |
90 | mode = btr & 0x3; | |
2d5eaa6d | 91 | |
1da177e4 LT |
92 | /* If someone decides to do UDMA133 on CSB5 the same |
93 | issue will bite so be inclusive */ | |
94 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
95 | mode = 2; | |
2d5eaa6d BZ |
96 | |
97 | switch(mode) { | |
0c824b51 | 98 | case 3: mask = 0x3f; break; |
2d5eaa6d BZ |
99 | case 2: mask = 0x1f; break; |
100 | case 1: mask = 0x07; break; | |
101 | default: mask = 0x00; break; | |
102 | } | |
1da177e4 LT |
103 | } |
104 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
105 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
106 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
107 | mask = 0x1f; |
108 | ||
109 | return mask; | |
1da177e4 LT |
110 | } |
111 | ||
112 | static u8 svwks_csb_check (struct pci_dev *dev) | |
113 | { | |
114 | switch (dev->device) { | |
115 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
116 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
117 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 118 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
119 | return 1; |
120 | default: | |
121 | break; | |
122 | } | |
123 | return 0; | |
124 | } | |
1880a8d7 | 125 | |
88b2b32b | 126 | static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1880a8d7 BZ |
127 | { |
128 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
129 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
130 | ||
36501650 | 131 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
1880a8d7 BZ |
132 | |
133 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); | |
134 | ||
135 | if (svwks_csb_check(dev)) { | |
136 | u16 csb_pio = 0; | |
137 | ||
138 | pci_read_config_word(dev, 0x4a, &csb_pio); | |
139 | ||
140 | csb_pio &= ~(0x0f << (4 * drive->dn)); | |
141 | csb_pio |= (pio << (4 * drive->dn)); | |
142 | ||
143 | pci_write_config_word(dev, 0x4a, csb_pio); | |
144 | } | |
145 | } | |
146 | ||
88b2b32b | 147 | static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 148 | { |
f201f504 AC |
149 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
150 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
f201f504 | 151 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; |
1da177e4 LT |
152 | |
153 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 154 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 155 | u8 unit = (drive->select.b.unit & 0x01); |
1880a8d7 BZ |
156 | |
157 | u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; | |
158 | ||
1da177e4 | 159 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
1da177e4 LT |
160 | pci_read_config_byte(dev, 0x54, &ultra_enable); |
161 | ||
1da177e4 LT |
162 | ultra_timing &= ~(0x0F << (4*unit)); |
163 | ultra_enable &= ~(0x01 << drive->dn); | |
1da177e4 | 164 | |
7b971df1 BZ |
165 | if (speed >= XFER_UDMA_0) { |
166 | dma_timing |= dma_modes[2]; | |
167 | ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit)); | |
168 | ultra_enable |= (0x01 << drive->dn); | |
169 | } else if (speed >= XFER_MW_DMA_0) | |
170 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; | |
1da177e4 | 171 | |
1da177e4 LT |
172 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); |
173 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
174 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
1da177e4 LT |
175 | } |
176 | ||
a326b02b | 177 | static unsigned int __devinit init_chipset_svwks(struct pci_dev *dev) |
1da177e4 LT |
178 | { |
179 | unsigned int reg; | |
180 | u8 btr; | |
181 | ||
1da177e4 LT |
182 | /* force Master Latency Timer value to 64 PCICLKs */ |
183 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
184 | ||
185 | /* OSB4 : South Bridge and IDE */ | |
186 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 187 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
188 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
189 | if (isa_dev) { | |
190 | pci_read_config_dword(isa_dev, 0x64, ®); | |
191 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
192 | if(!(reg & 0x00004000)) | |
a326b02b BZ |
193 | printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS " |
194 | "enabled.\n", pci_name(dev)); | |
1da177e4 LT |
195 | reg |= 0x00004000; /* enable UDMA/33 support */ |
196 | pci_write_config_dword(isa_dev, 0x64, reg); | |
197 | } | |
198 | } | |
199 | ||
200 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
201 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
202 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
203 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
204 | ||
205 | /* Third Channel Test */ | |
206 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
207 | struct pci_dev * findev = NULL; | |
208 | u32 reg4c = 0; | |
970a6136 | 209 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
210 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
211 | if (findev) { | |
212 | pci_read_config_dword(findev, 0x4C, ®4c); | |
213 | reg4c &= ~0x000007FF; | |
214 | reg4c |= 0x00000040; | |
215 | reg4c |= 0x00000020; | |
216 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 217 | pci_dev_put(findev); |
1da177e4 LT |
218 | } |
219 | outb_p(0x06, 0x0c00); | |
220 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
221 | } else { |
222 | struct pci_dev * findev = NULL; | |
223 | u8 reg41 = 0; | |
224 | ||
970a6136 | 225 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
226 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
227 | if (findev) { | |
228 | pci_read_config_byte(findev, 0x41, ®41); | |
229 | reg41 &= ~0x40; | |
230 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 231 | pci_dev_put(findev); |
1da177e4 LT |
232 | } |
233 | /* | |
234 | * This is a device pin issue on CSB6. | |
235 | * Since there will be a future raid mode, | |
236 | * early versions of the chipset require the | |
237 | * interrupt pin to be set, and it is a compatibility | |
238 | * mode issue. | |
239 | */ | |
240 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
241 | dev->irq = 0; | |
242 | } | |
243 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
244 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
245 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
246 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
247 | /* setup the UDMA Control register | |
248 | * | |
249 | * 1. clear bit 6 to enable DMA | |
250 | * 2. enable DMA modes with bits 0-1 | |
251 | * 00 : legacy | |
252 | * 01 : udma2 | |
253 | * 10 : udma2/udma4 | |
254 | * 11 : udma2/udma4/udma5 | |
255 | */ | |
256 | pci_read_config_byte(dev, 0x5A, &btr); | |
257 | btr &= ~0x40; | |
258 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
259 | btr |= 0x2; | |
260 | else | |
44c10138 | 261 | btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
1da177e4 LT |
262 | pci_write_config_byte(dev, 0x5A, btr); |
263 | } | |
84f57fbc NS |
264 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
265 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
266 | pci_read_config_byte(dev, 0x5A, &btr); | |
267 | btr &= ~0x40; | |
268 | btr |= 0x3; | |
269 | pci_write_config_byte(dev, 0x5A, btr); | |
270 | } | |
1da177e4 | 271 | |
f201f504 | 272 | return dev->irq; |
1da177e4 LT |
273 | } |
274 | ||
49521f97 | 275 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 276 | { |
49521f97 | 277 | return ATA_CBL_PATA80; |
1da177e4 LT |
278 | } |
279 | ||
280 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
281 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
282 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
283 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
284 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
285 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
286 | */ | |
49521f97 | 287 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 | 288 | { |
36501650 BZ |
289 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
290 | ||
1da177e4 LT |
291 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && |
292 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
293 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
294 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
295 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
296 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
297 | return ATA_CBL_PATA40; | |
1da177e4 LT |
298 | } |
299 | ||
300 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
301 | * detect issue by attaching the drives directly to the board. | |
302 | * This check follows the Dell precedent (how scary is that?!) | |
303 | * | |
304 | * WARNING: this only works on Alpine hardware! | |
305 | */ | |
49521f97 | 306 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 | 307 | { |
36501650 BZ |
308 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
309 | ||
1da177e4 LT |
310 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && |
311 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
312 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
313 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
314 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
315 | return ATA_CBL_PATA40; | |
1da177e4 LT |
316 | } |
317 | ||
ac95beed | 318 | static u8 __devinit svwks_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 319 | { |
36501650 | 320 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 321 | |
1da177e4 LT |
322 | /* Server Works */ |
323 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
324 | return ata66_svwks_svwks (hwif); | |
325 | ||
326 | /* Dell PowerEdge */ | |
327 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
328 | return ata66_svwks_dell (hwif); | |
329 | ||
330 | /* Cobalt Alpine */ | |
331 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
332 | return ata66_svwks_cobalt (hwif); | |
333 | ||
f201f504 AC |
334 | /* Per Specified Design by OEM, and ASIC Architect */ |
335 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
336 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 337 | return ATA_CBL_PATA80; |
f201f504 | 338 | |
49521f97 | 339 | return ATA_CBL_PATA40; |
1da177e4 LT |
340 | } |
341 | ||
ac95beed BZ |
342 | static const struct ide_port_ops osb4_port_ops = { |
343 | .set_pio_mode = svwks_set_pio_mode, | |
344 | .set_dma_mode = svwks_set_dma_mode, | |
345 | .udma_filter = svwks_udma_filter, | |
346 | }; | |
1da177e4 | 347 | |
ac95beed BZ |
348 | static const struct ide_port_ops svwks_port_ops = { |
349 | .set_pio_mode = svwks_set_pio_mode, | |
350 | .set_dma_mode = svwks_set_dma_mode, | |
351 | .udma_filter = svwks_udma_filter, | |
352 | .cable_detect = svwks_cable_detect, | |
353 | }; | |
1da177e4 | 354 | |
3b2a5c71 | 355 | #define IDE_HFLAGS_SVWKS IDE_HFLAG_LEGACY_IRQS |
4db90a14 | 356 | |
85620436 | 357 | static const struct ide_port_info serverworks_chipsets[] __devinitdata = { |
ced3ec8a BZ |
358 | { /* 0: OSB4 */ |
359 | .name = DRV_NAME, | |
1da177e4 | 360 | .init_chipset = init_chipset_svwks, |
ac95beed | 361 | .port_ops = &osb4_port_ops, |
4db90a14 | 362 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 363 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
364 | .mwdma_mask = ATA_MWDMA2, |
365 | .udma_mask = 0x00, /* UDMA is problematic on OSB4 */ | |
ced3ec8a BZ |
366 | }, |
367 | { /* 1: CSB5 */ | |
368 | .name = DRV_NAME, | |
1da177e4 | 369 | .init_chipset = init_chipset_svwks, |
ac95beed | 370 | .port_ops = &svwks_port_ops, |
4db90a14 | 371 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 372 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
373 | .mwdma_mask = ATA_MWDMA2, |
374 | .udma_mask = ATA_UDMA5, | |
ced3ec8a BZ |
375 | }, |
376 | { /* 2: CSB6 */ | |
377 | .name = DRV_NAME, | |
1da177e4 | 378 | .init_chipset = init_chipset_svwks, |
ac95beed | 379 | .port_ops = &svwks_port_ops, |
4db90a14 | 380 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 381 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
382 | .mwdma_mask = ATA_MWDMA2, |
383 | .udma_mask = ATA_UDMA5, | |
ced3ec8a BZ |
384 | }, |
385 | { /* 3: CSB6-2 */ | |
386 | .name = DRV_NAME, | |
1da177e4 | 387 | .init_chipset = init_chipset_svwks, |
ac95beed | 388 | .port_ops = &svwks_port_ops, |
4db90a14 | 389 | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE, |
4099d143 | 390 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
391 | .mwdma_mask = ATA_MWDMA2, |
392 | .udma_mask = ATA_UDMA5, | |
ced3ec8a BZ |
393 | }, |
394 | { /* 4: HT1000 */ | |
395 | .name = DRV_NAME, | |
84f57fbc | 396 | .init_chipset = init_chipset_svwks, |
ac95beed | 397 | .port_ops = &svwks_port_ops, |
4db90a14 | 398 | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE, |
4099d143 | 399 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
400 | .mwdma_mask = ATA_MWDMA2, |
401 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
402 | } |
403 | }; | |
404 | ||
405 | /** | |
406 | * svwks_init_one - called when a OSB/CSB is found | |
407 | * @dev: the svwks device | |
408 | * @id: the matching pci id | |
409 | * | |
410 | * Called when the PCI registration layer (or the IDE initialization) | |
411 | * finds a device matching our IDE device tables. | |
412 | */ | |
413 | ||
414 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
415 | { | |
039788e1 | 416 | struct ide_port_info d; |
7ed58297 BZ |
417 | u8 idx = id->driver_data; |
418 | ||
419 | d = serverworks_chipsets[idx]; | |
420 | ||
8ac2b42a BZ |
421 | if (idx == 1) |
422 | d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; | |
423 | else if (idx == 2 || idx == 3) { | |
7ed58297 BZ |
424 | if ((PCI_FUNC(dev->devfn) & 1) == 0) { |
425 | if (pci_resource_start(dev, 0) != 0x01f1) | |
5e71d9c5 | 426 | d.host_flags |= IDE_HFLAG_NON_BOOTABLE; |
7ed58297 BZ |
427 | d.host_flags |= IDE_HFLAG_SINGLE; |
428 | } else | |
429 | d.host_flags &= ~IDE_HFLAG_SINGLE; | |
430 | } | |
1da177e4 | 431 | |
6cdf6eb3 | 432 | return ide_pci_init_one(dev, &d, NULL); |
1da177e4 LT |
433 | } |
434 | ||
9cbcc5e3 BZ |
435 | static const struct pci_device_id svwks_pci_tbl[] = { |
436 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 }, | |
437 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 }, | |
438 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 }, | |
439 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 }, | |
440 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 }, | |
1da177e4 LT |
441 | { 0, }, |
442 | }; | |
443 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
444 | ||
445 | static struct pci_driver driver = { | |
446 | .name = "Serverworks_IDE", | |
447 | .id_table = svwks_pci_tbl, | |
448 | .probe = svwks_init_one, | |
bc2c9a80 | 449 | .remove = ide_pci_remove, |
1da177e4 LT |
450 | }; |
451 | ||
82ab1eec | 452 | static int __init svwks_ide_init(void) |
1da177e4 LT |
453 | { |
454 | return ide_pci_register_driver(&driver); | |
455 | } | |
456 | ||
bc2c9a80 BZ |
457 | static void __exit svwks_ide_exit(void) |
458 | { | |
459 | pci_unregister_driver(&driver); | |
460 | } | |
461 | ||
1da177e4 | 462 | module_init(svwks_ide_init); |
bc2c9a80 | 463 | module_exit(svwks_ide_exit); |
1da177e4 LT |
464 | |
465 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
466 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
467 | MODULE_LICENSE("GPL"); |