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1da177e4 | 1 | /* |
b740d884 | 2 | * linux/drivers/ide/pci/serverworks.c Version 0.20 Jun 3 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry | |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
6 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * Portions copyright (c) 2001 Sun Microsystems |
9 | * | |
10 | * | |
11 | * RCC/ServerWorks IDE driver for Linux | |
12 | * | |
13 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
14 | * supports UDMA mode 2 (33 MB/s) | |
15 | * | |
16 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
17 | * all revisions support UDMA mode 4 (66 MB/s) | |
18 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
19 | * | |
20 | * *** The CSB5 does not provide ANY register *** | |
21 | * *** to detect 80-conductor cable presence. *** | |
22 | * | |
23 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
24 | * | |
84f57fbc NS |
25 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
26 | * controller same as the CSB6. Single channel ATA100 only. | |
27 | * | |
1da177e4 LT |
28 | * Documentation: |
29 | * Available under NDA only. Errata info very hard to get. | |
30 | * | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/types.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/hdreg.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/delay.h> | |
42 | ||
43 | #include <asm/io.h> | |
44 | ||
45 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
46 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
47 | ||
48 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
49 | * can overrun their FIFOs when used with the CSB5 */ | |
50 | static const char *svwks_bad_ata100[] = { | |
51 | "ST320011A", | |
52 | "ST340016A", | |
53 | "ST360021A", | |
54 | "ST380021A", | |
55 | NULL | |
56 | }; | |
57 | ||
58 | static u8 svwks_revision = 0; | |
59 | static struct pci_dev *isa_dev; | |
60 | ||
61 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
62 | { | |
63 | while (*list) | |
64 | if (!strcmp(*list++, drive->id->model)) | |
65 | return 1; | |
66 | return 0; | |
67 | } | |
68 | ||
2d5eaa6d | 69 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 LT |
70 | { |
71 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
2d5eaa6d | 72 | u8 mask = 0; |
1da177e4 LT |
73 | |
74 | if (!svwks_revision) | |
75 | pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision); | |
76 | ||
84f57fbc | 77 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 78 | return 0x1f; |
1da177e4 LT |
79 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
80 | u32 reg = 0; | |
81 | if (isa_dev) | |
82 | pci_read_config_dword(isa_dev, 0x64, ®); | |
83 | ||
84 | /* | |
85 | * Don't enable UDMA on disk devices for the moment | |
86 | */ | |
87 | if(drive->media == ide_disk) | |
88 | return 0; | |
89 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 90 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
1da177e4 | 91 | } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 92 | return 0x07; |
1da177e4 | 93 | } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 94 | u8 btr = 0, mode; |
1da177e4 LT |
95 | pci_read_config_byte(dev, 0x5A, &btr); |
96 | mode = btr & 0x3; | |
2d5eaa6d | 97 | |
1da177e4 LT |
98 | /* If someone decides to do UDMA133 on CSB5 the same |
99 | issue will bite so be inclusive */ | |
100 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
101 | mode = 2; | |
2d5eaa6d BZ |
102 | |
103 | switch(mode) { | |
104 | case 2: mask = 0x1f; break; | |
105 | case 1: mask = 0x07; break; | |
106 | default: mask = 0x00; break; | |
107 | } | |
1da177e4 LT |
108 | } |
109 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
110 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
111 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
112 | mask = 0x1f; |
113 | ||
114 | return mask; | |
1da177e4 LT |
115 | } |
116 | ||
117 | static u8 svwks_csb_check (struct pci_dev *dev) | |
118 | { | |
119 | switch (dev->device) { | |
120 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
121 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
122 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 123 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
124 | return 1; |
125 | default: | |
126 | break; | |
127 | } | |
128 | return 0; | |
129 | } | |
130 | static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
131 | { | |
f201f504 AC |
132 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
133 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
134 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
135 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
136 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; | |
1da177e4 LT |
137 | |
138 | ide_hwif_t *hwif = HWIF(drive); | |
139 | struct pci_dev *dev = hwif->pci_dev; | |
9445de76 BZ |
140 | u8 speed = ide_rate_filter(drive, xferspeed); |
141 | u8 pio = ide_get_best_pio_mode(drive, 255, 4, NULL); | |
1da177e4 LT |
142 | u8 unit = (drive->select.b.unit & 0x01); |
143 | u8 csb5 = svwks_csb_check(dev); | |
144 | u8 ultra_enable = 0, ultra_timing = 0; | |
145 | u8 dma_timing = 0, pio_timing = 0; | |
146 | u16 csb5_pio = 0; | |
147 | ||
1da177e4 LT |
148 | /* If we are about to put a disk into UDMA mode we screwed up. |
149 | Our code assumes we never _ever_ do this on an OSB4 */ | |
150 | ||
151 | if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 && | |
152 | drive->media == ide_disk && speed >= XFER_UDMA_0) | |
153 | BUG(); | |
b740d884 | 154 | |
1da177e4 LT |
155 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
156 | pci_read_config_word(dev, 0x4A, &csb5_pio); | |
157 | pci_read_config_byte(dev, 0x54, &ultra_enable); | |
158 | ||
1da177e4 LT |
159 | ultra_timing &= ~(0x0F << (4*unit)); |
160 | ultra_enable &= ~(0x01 << drive->dn); | |
161 | csb5_pio &= ~(0x0F << (4*drive->dn)); | |
162 | ||
163 | switch(speed) { | |
164 | case XFER_PIO_4: | |
165 | case XFER_PIO_3: | |
166 | case XFER_PIO_2: | |
167 | case XFER_PIO_1: | |
168 | case XFER_PIO_0: | |
169 | pio_timing |= pio_modes[speed - XFER_PIO_0]; | |
170 | csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn)); | |
171 | break; | |
172 | ||
173 | case XFER_MW_DMA_2: | |
174 | case XFER_MW_DMA_1: | |
175 | case XFER_MW_DMA_0: | |
9445de76 BZ |
176 | /* |
177 | * TODO: always setup PIO mode so this won't be needed | |
178 | */ | |
1da177e4 LT |
179 | pio_timing |= pio_modes[pio]; |
180 | csb5_pio |= (pio << (4*drive->dn)); | |
181 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; | |
182 | break; | |
183 | ||
184 | case XFER_UDMA_5: | |
185 | case XFER_UDMA_4: | |
186 | case XFER_UDMA_3: | |
187 | case XFER_UDMA_2: | |
188 | case XFER_UDMA_1: | |
189 | case XFER_UDMA_0: | |
9445de76 BZ |
190 | /* |
191 | * TODO: always setup PIO mode so this won't be needed | |
192 | */ | |
1da177e4 LT |
193 | pio_timing |= pio_modes[pio]; |
194 | csb5_pio |= (pio << (4*drive->dn)); | |
195 | dma_timing |= dma_modes[2]; | |
196 | ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit)); | |
197 | ultra_enable |= (0x01 << drive->dn); | |
198 | default: | |
199 | break; | |
200 | } | |
201 | ||
202 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing); | |
203 | if (csb5) | |
204 | pci_write_config_word(dev, 0x4A, csb5_pio); | |
205 | ||
206 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); | |
207 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
208 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
209 | ||
210 | return (ide_config_drive_speed(drive, speed)); | |
211 | } | |
212 | ||
1da177e4 LT |
213 | static void svwks_tune_drive (ide_drive_t *drive, u8 pio) |
214 | { | |
9445de76 BZ |
215 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
216 | (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
217 | } |
218 | ||
1da177e4 LT |
219 | static int svwks_config_drive_xfer_rate (ide_drive_t *drive) |
220 | { | |
1da177e4 LT |
221 | drive->init_speed = 0; |
222 | ||
bd203b57 | 223 | if (ide_tune_dma(drive)) |
3608b5d7 | 224 | return 0; |
1da177e4 | 225 | |
d8f4469d | 226 | if (ide_use_fast_pio(drive)) |
9445de76 | 227 | svwks_tune_drive(drive, 255); |
d8f4469d | 228 | |
3608b5d7 | 229 | return -1; |
1da177e4 LT |
230 | } |
231 | ||
1da177e4 LT |
232 | static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) |
233 | { | |
234 | unsigned int reg; | |
235 | u8 btr; | |
236 | ||
237 | /* save revision id to determine DMA capability */ | |
238 | pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision); | |
239 | ||
240 | /* force Master Latency Timer value to 64 PCICLKs */ | |
241 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
242 | ||
243 | /* OSB4 : South Bridge and IDE */ | |
244 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 245 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
246 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
247 | if (isa_dev) { | |
248 | pci_read_config_dword(isa_dev, 0x64, ®); | |
249 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
250 | if(!(reg & 0x00004000)) | |
251 | printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name); | |
252 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
253 | pci_write_config_dword(isa_dev, 0x64, reg); | |
254 | } | |
255 | } | |
256 | ||
257 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
258 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
259 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
260 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
261 | ||
262 | /* Third Channel Test */ | |
263 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
264 | struct pci_dev * findev = NULL; | |
265 | u32 reg4c = 0; | |
970a6136 | 266 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
267 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
268 | if (findev) { | |
269 | pci_read_config_dword(findev, 0x4C, ®4c); | |
270 | reg4c &= ~0x000007FF; | |
271 | reg4c |= 0x00000040; | |
272 | reg4c |= 0x00000020; | |
273 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 274 | pci_dev_put(findev); |
1da177e4 LT |
275 | } |
276 | outb_p(0x06, 0x0c00); | |
277 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
278 | } else { |
279 | struct pci_dev * findev = NULL; | |
280 | u8 reg41 = 0; | |
281 | ||
970a6136 | 282 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
283 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
284 | if (findev) { | |
285 | pci_read_config_byte(findev, 0x41, ®41); | |
286 | reg41 &= ~0x40; | |
287 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 288 | pci_dev_put(findev); |
1da177e4 LT |
289 | } |
290 | /* | |
291 | * This is a device pin issue on CSB6. | |
292 | * Since there will be a future raid mode, | |
293 | * early versions of the chipset require the | |
294 | * interrupt pin to be set, and it is a compatibility | |
295 | * mode issue. | |
296 | */ | |
297 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
298 | dev->irq = 0; | |
299 | } | |
300 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
301 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
302 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
303 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
304 | /* setup the UDMA Control register | |
305 | * | |
306 | * 1. clear bit 6 to enable DMA | |
307 | * 2. enable DMA modes with bits 0-1 | |
308 | * 00 : legacy | |
309 | * 01 : udma2 | |
310 | * 10 : udma2/udma4 | |
311 | * 11 : udma2/udma4/udma5 | |
312 | */ | |
313 | pci_read_config_byte(dev, 0x5A, &btr); | |
314 | btr &= ~0x40; | |
315 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
316 | btr |= 0x2; | |
317 | else | |
318 | btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; | |
319 | pci_write_config_byte(dev, 0x5A, btr); | |
320 | } | |
84f57fbc NS |
321 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
322 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
323 | pci_read_config_byte(dev, 0x5A, &btr); | |
324 | btr &= ~0x40; | |
325 | btr |= 0x3; | |
326 | pci_write_config_byte(dev, 0x5A, btr); | |
327 | } | |
1da177e4 | 328 | |
f201f504 | 329 | return dev->irq; |
1da177e4 LT |
330 | } |
331 | ||
49521f97 | 332 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 333 | { |
49521f97 | 334 | return ATA_CBL_PATA80; |
1da177e4 LT |
335 | } |
336 | ||
337 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
338 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
339 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
340 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
341 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
342 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
343 | */ | |
49521f97 | 344 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 LT |
345 | { |
346 | struct pci_dev *dev = hwif->pci_dev; | |
347 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
348 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
349 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
350 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
351 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
352 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
353 | return ATA_CBL_PATA40; | |
1da177e4 LT |
354 | } |
355 | ||
356 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
357 | * detect issue by attaching the drives directly to the board. | |
358 | * This check follows the Dell precedent (how scary is that?!) | |
359 | * | |
360 | * WARNING: this only works on Alpine hardware! | |
361 | */ | |
49521f97 | 362 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 LT |
363 | { |
364 | struct pci_dev *dev = hwif->pci_dev; | |
365 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && | |
366 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
367 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
368 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
369 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
370 | return ATA_CBL_PATA40; | |
1da177e4 LT |
371 | } |
372 | ||
49521f97 | 373 | static u8 __devinit ata66_svwks(ide_hwif_t *hwif) |
1da177e4 LT |
374 | { |
375 | struct pci_dev *dev = hwif->pci_dev; | |
376 | ||
1da177e4 LT |
377 | /* Server Works */ |
378 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
379 | return ata66_svwks_svwks (hwif); | |
380 | ||
381 | /* Dell PowerEdge */ | |
382 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
383 | return ata66_svwks_dell (hwif); | |
384 | ||
385 | /* Cobalt Alpine */ | |
386 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
387 | return ata66_svwks_cobalt (hwif); | |
388 | ||
f201f504 AC |
389 | /* Per Specified Design by OEM, and ASIC Architect */ |
390 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
391 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 392 | return ATA_CBL_PATA80; |
f201f504 | 393 | |
49521f97 | 394 | return ATA_CBL_PATA40; |
1da177e4 LT |
395 | } |
396 | ||
1da177e4 LT |
397 | static void __devinit init_hwif_svwks (ide_hwif_t *hwif) |
398 | { | |
399 | u8 dma_stat = 0; | |
400 | ||
401 | if (!hwif->irq) | |
402 | hwif->irq = hwif->channel ? 15 : 14; | |
403 | ||
404 | hwif->tuneproc = &svwks_tune_drive; | |
405 | hwif->speedproc = &svwks_tune_chipset; | |
2d5eaa6d | 406 | hwif->udma_filter = &svwks_udma_filter; |
1da177e4 LT |
407 | |
408 | hwif->atapi_dma = 1; | |
409 | ||
410 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) | |
411 | hwif->ultra_mask = 0x3f; | |
412 | ||
413 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
414 | |
415 | hwif->autodma = 0; | |
416 | ||
417 | if (!hwif->dma_base) { | |
418 | hwif->drives[0].autotune = 1; | |
419 | hwif->drives[1].autotune = 1; | |
420 | return; | |
421 | } | |
422 | ||
423 | hwif->ide_dma_check = &svwks_config_drive_xfer_rate; | |
946f8e4a | 424 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
49521f97 BZ |
425 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
426 | hwif->cbl = ata66_svwks(hwif); | |
946f8e4a | 427 | } |
1da177e4 LT |
428 | if (!noautodma) |
429 | hwif->autodma = 1; | |
430 | ||
0ecdca26 | 431 | dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
432 | hwif->drives[0].autodma = (dma_stat & 0x20); |
433 | hwif->drives[1].autodma = (dma_stat & 0x40); | |
434 | hwif->drives[0].autotune = (!(dma_stat & 0x20)); | |
435 | hwif->drives[1].autotune = (!(dma_stat & 0x40)); | |
1da177e4 LT |
436 | } |
437 | ||
1da177e4 LT |
438 | static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) |
439 | { | |
440 | return ide_setup_pci_device(dev, d); | |
441 | } | |
442 | ||
bb732d7b | 443 | static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 LT |
444 | { |
445 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
446 | d->bootable = NEVER_BOARD; | |
447 | if (dev->resource[0].start == 0x01f1) | |
448 | d->bootable = ON_BOARD; | |
449 | } | |
1da177e4 LT |
450 | |
451 | d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE || | |
452 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) && | |
453 | (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2; | |
454 | ||
455 | return ide_setup_pci_device(dev, d); | |
456 | } | |
457 | ||
458 | static ide_pci_device_t serverworks_chipsets[] __devinitdata = { | |
459 | { /* 0 */ | |
460 | .name = "SvrWks OSB4", | |
461 | .init_setup = init_setup_svwks, | |
462 | .init_chipset = init_chipset_svwks, | |
463 | .init_hwif = init_hwif_svwks, | |
464 | .channels = 2, | |
465 | .autodma = AUTODMA, | |
466 | .bootable = ON_BOARD, | |
467 | },{ /* 1 */ | |
468 | .name = "SvrWks CSB5", | |
469 | .init_setup = init_setup_svwks, | |
470 | .init_chipset = init_chipset_svwks, | |
471 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
472 | .channels = 2, |
473 | .autodma = AUTODMA, | |
474 | .bootable = ON_BOARD, | |
475 | },{ /* 2 */ | |
476 | .name = "SvrWks CSB6", | |
477 | .init_setup = init_setup_csb6, | |
478 | .init_chipset = init_chipset_svwks, | |
479 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
480 | .channels = 2, |
481 | .autodma = AUTODMA, | |
482 | .bootable = ON_BOARD, | |
483 | },{ /* 3 */ | |
484 | .name = "SvrWks CSB6", | |
485 | .init_setup = init_setup_csb6, | |
486 | .init_chipset = init_chipset_svwks, | |
487 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
488 | .channels = 1, /* 2 */ |
489 | .autodma = AUTODMA, | |
490 | .bootable = ON_BOARD, | |
84f57fbc NS |
491 | },{ /* 4 */ |
492 | .name = "SvrWks HT1000", | |
493 | .init_setup = init_setup_svwks, | |
494 | .init_chipset = init_chipset_svwks, | |
495 | .init_hwif = init_hwif_svwks, | |
84f57fbc NS |
496 | .channels = 1, /* 2 */ |
497 | .autodma = AUTODMA, | |
498 | .bootable = ON_BOARD, | |
1da177e4 LT |
499 | } |
500 | }; | |
501 | ||
502 | /** | |
503 | * svwks_init_one - called when a OSB/CSB is found | |
504 | * @dev: the svwks device | |
505 | * @id: the matching pci id | |
506 | * | |
507 | * Called when the PCI registration layer (or the IDE initialization) | |
508 | * finds a device matching our IDE device tables. | |
509 | */ | |
510 | ||
511 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
512 | { | |
513 | ide_pci_device_t *d = &serverworks_chipsets[id->driver_data]; | |
514 | ||
515 | return d->init_setup(dev, d); | |
516 | } | |
517 | ||
518 | static struct pci_device_id svwks_pci_tbl[] = { | |
28a2a3f5 AC |
519 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
520 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
521 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
522 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
523 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
1da177e4 LT |
524 | { 0, }, |
525 | }; | |
526 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
527 | ||
528 | static struct pci_driver driver = { | |
529 | .name = "Serverworks_IDE", | |
530 | .id_table = svwks_pci_tbl, | |
531 | .probe = svwks_init_one, | |
532 | }; | |
533 | ||
82ab1eec | 534 | static int __init svwks_ide_init(void) |
1da177e4 LT |
535 | { |
536 | return ide_pci_register_driver(&driver); | |
537 | } | |
538 | ||
539 | module_init(svwks_ide_init); | |
540 | ||
541 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
542 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
543 | MODULE_LICENSE("GPL"); |