Commit | Line | Data |
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1da177e4 | 1 | /* |
8e60d376 | 2 | * linux/drivers/ide/pci/siimage.c Version 1.12 Mar 10 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 6 | * Copyright (C) 2007 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * May be copied or modified under the terms of the GNU General Public License | |
9 | * | |
bf4c796d JG |
10 | * Documentation for CMD680: |
11 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
12 | * | |
13 | * Documentation for SiI 3112: | |
14 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
15 | * | |
16 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
17 | * |
18 | * | |
19 | * FAQ Items: | |
20 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
21 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
22 | * | |
23 | * If you are using WD drives with SATA bridges you must set the | |
24 | * drive to "Single". "Master" will hang | |
25 | * | |
26 | * If you have strange problems with nVidia chipset systems please | |
27 | * see the SI support documentation and update your system BIOS | |
28 | * if neccessary | |
8693d3e4 AC |
29 | * |
30 | * The Dell DRAC4 has some interesting features including effectively hot | |
31 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
32 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
33 | * smarter code in libata. | |
1da177e4 LT |
34 | */ |
35 | ||
1da177e4 LT |
36 | #include <linux/types.h> |
37 | #include <linux/module.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/hdreg.h> | |
41 | #include <linux/ide.h> | |
42 | #include <linux/init.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | ||
1da177e4 LT |
46 | /** |
47 | * pdev_is_sata - check if device is SATA | |
48 | * @pdev: PCI device to check | |
49 | * | |
50 | * Returns true if this is a SATA controller | |
51 | */ | |
52 | ||
53 | static int pdev_is_sata(struct pci_dev *pdev) | |
54 | { | |
55 | switch(pdev->device) | |
56 | { | |
57 | case PCI_DEVICE_ID_SII_3112: | |
58 | case PCI_DEVICE_ID_SII_1210SA: | |
59 | return 1; | |
60 | case PCI_DEVICE_ID_SII_680: | |
61 | return 0; | |
62 | } | |
63 | BUG(); | |
64 | return 0; | |
65 | } | |
66 | ||
67 | /** | |
68 | * is_sata - check if hwif is SATA | |
69 | * @hwif: interface to check | |
70 | * | |
71 | * Returns true if this is a SATA controller | |
72 | */ | |
73 | ||
74 | static inline int is_sata(ide_hwif_t *hwif) | |
75 | { | |
76 | return pdev_is_sata(hwif->pci_dev); | |
77 | } | |
78 | ||
79 | /** | |
80 | * siimage_selreg - return register base | |
81 | * @hwif: interface | |
82 | * @r: config offset | |
83 | * | |
84 | * Turn a config register offset into the right address in either | |
85 | * PCI space or MMIO space to access the control register in question | |
86 | * Thankfully this is a configuration operation so isnt performance | |
87 | * criticial. | |
88 | */ | |
89 | ||
90 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
91 | { | |
92 | unsigned long base = (unsigned long)hwif->hwif_data; | |
93 | base += 0xA0 + r; | |
94 | if(hwif->mmio) | |
95 | base += (hwif->channel << 6); | |
96 | else | |
97 | base += (hwif->channel << 4); | |
98 | return base; | |
99 | } | |
100 | ||
101 | /** | |
102 | * siimage_seldev - return register base | |
103 | * @hwif: interface | |
104 | * @r: config offset | |
105 | * | |
106 | * Turn a config register offset into the right address in either | |
107 | * PCI space or MMIO space to access the control register in question | |
108 | * including accounting for the unit shift. | |
109 | */ | |
110 | ||
111 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
112 | { | |
113 | ide_hwif_t *hwif = HWIF(drive); | |
114 | unsigned long base = (unsigned long)hwif->hwif_data; | |
115 | base += 0xA0 + r; | |
116 | if(hwif->mmio) | |
117 | base += (hwif->channel << 6); | |
118 | else | |
119 | base += (hwif->channel << 4); | |
120 | base |= drive->select.b.unit << drive->select.b.unit; | |
121 | return base; | |
122 | } | |
123 | ||
124 | /** | |
2d5eaa6d BZ |
125 | * sil_udma_filter - compute UDMA mask |
126 | * @drive: IDE device | |
127 | * | |
128 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 129 | * |
1da177e4 | 130 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 131 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 132 | */ |
2d5eaa6d BZ |
133 | |
134 | static u8 sil_udma_filter(ide_drive_t *drive) | |
1da177e4 | 135 | { |
2d5eaa6d | 136 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 137 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 138 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
139 | |
140 | if (hwif->mmio) | |
141 | scsc = hwif->INB(base + 0x4A); | |
142 | else | |
143 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
144 | ||
2d5eaa6d BZ |
145 | if (is_sata(hwif)) { |
146 | mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f; | |
147 | goto out; | |
1da177e4 | 148 | } |
2d5eaa6d | 149 | |
1da177e4 | 150 | if ((scsc & 0x30) == 0x10) /* 133 */ |
2d5eaa6d | 151 | mask = 0x7f; |
1da177e4 | 152 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
2d5eaa6d | 153 | mask = 0x7f; |
1da177e4 | 154 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
2d5eaa6d | 155 | mask = 0x3f; |
1da177e4 LT |
156 | else /* Disabled ? */ |
157 | BUG(); | |
2d5eaa6d BZ |
158 | out: |
159 | return mask; | |
1da177e4 LT |
160 | } |
161 | ||
162 | /** | |
163 | * siimage_taskfile_timing - turn timing data to a mode | |
164 | * @hwif: interface to query | |
165 | * | |
166 | * Read the timing data for the interface and return the | |
167 | * mode that is being used. | |
168 | */ | |
169 | ||
170 | static byte siimage_taskfile_timing (ide_hwif_t *hwif) | |
171 | { | |
172 | u16 timing = 0x328a; | |
173 | unsigned long addr = siimage_selreg(hwif, 2); | |
174 | ||
175 | if (hwif->mmio) | |
176 | timing = hwif->INW(addr); | |
177 | else | |
178 | pci_read_config_word(hwif->pci_dev, addr, &timing); | |
179 | ||
180 | switch (timing) { | |
181 | case 0x10c1: return 4; | |
182 | case 0x10c3: return 3; | |
183 | case 0x1104: | |
184 | case 0x1281: return 2; | |
185 | case 0x2283: return 1; | |
186 | case 0x328a: | |
187 | default: return 0; | |
188 | } | |
189 | } | |
190 | ||
191 | /** | |
192 | * simmage_tuneproc - tune a drive | |
193 | * @drive: drive to tune | |
194 | * @mode_wanted: the target operating mode | |
195 | * | |
196 | * Load the timing settings for this device mode into the | |
197 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
198 | * monitoring (bit 9). The TF timing is bits 31:16 | |
199 | */ | |
200 | ||
201 | static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted) | |
202 | { | |
203 | ide_hwif_t *hwif = HWIF(drive); | |
204 | u32 speedt = 0; | |
205 | u16 speedp = 0; | |
206 | unsigned long addr = siimage_seldev(drive, 0x04); | |
207 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
208 | ||
209 | /* cheat for now and use the docs */ | |
075cb655 SS |
210 | switch (mode_wanted) { |
211 | case 4: | |
212 | speedp = 0x10c1; | |
213 | speedt = 0x10c1; | |
214 | break; | |
215 | case 3: | |
216 | speedp = 0x10c3; | |
217 | speedt = 0x10c3; | |
218 | break; | |
219 | case 2: | |
220 | speedp = 0x1104; | |
221 | speedt = 0x1281; | |
222 | break; | |
223 | case 1: | |
224 | speedp = 0x2283; | |
225 | speedt = 0x2283; | |
226 | break; | |
227 | case 0: | |
228 | default: | |
229 | speedp = 0x328a; | |
230 | speedt = 0x328a; | |
231 | break; | |
1da177e4 | 232 | } |
075cb655 SS |
233 | |
234 | if (hwif->mmio) { | |
235 | hwif->OUTW(speedp, addr); | |
236 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 LT |
237 | /* Now set up IORDY */ |
238 | if(mode_wanted == 3 || mode_wanted == 4) | |
239 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); | |
240 | else | |
241 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
075cb655 | 242 | } else { |
1da177e4 LT |
243 | pci_write_config_word(hwif->pci_dev, addr, speedp); |
244 | pci_write_config_word(hwif->pci_dev, tfaddr, speedt); | |
245 | pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp); | |
246 | speedp &= ~0x200; | |
247 | /* Set IORDY for mode 3 or 4 */ | |
248 | if(mode_wanted == 3 || mode_wanted == 4) | |
249 | speedp |= 0x200; | |
250 | pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp); | |
251 | } | |
252 | } | |
253 | ||
254 | /** | |
255 | * config_siimage_chipset_for_pio - set drive timings | |
256 | * @drive: drive to tune | |
257 | * @speed we want | |
258 | * | |
259 | * Compute the best pio mode we can for a given device. Also honour | |
260 | * the timings for the driver when dealing with mixed devices. Some | |
261 | * of this is ugly but its all wrapped up here | |
262 | * | |
263 | * The SI680 can also do VDMA - we need to start using that | |
264 | * | |
265 | * FIXME: we use the BIOS channel timings to avoid driving the task | |
266 | * files too fast at the disk. We need to compute the master/slave | |
267 | * drive PIO mode properly so that we can up the speed on a hotplug | |
268 | * system. | |
269 | */ | |
270 | ||
271 | static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed) | |
272 | { | |
273 | u8 channel_timings = siimage_taskfile_timing(HWIF(drive)); | |
274 | u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); | |
275 | ||
276 | /* WARNING PIO timing mess is going to happen b/w devices, argh */ | |
277 | if ((channel_timings != set_pio) && (set_pio > channel_timings)) | |
278 | set_pio = channel_timings; | |
279 | ||
280 | siimage_tuneproc(drive, set_pio); | |
281 | speed = XFER_PIO_0 + set_pio; | |
282 | if (set_speed) | |
283 | (void) ide_config_drive_speed(drive, speed); | |
284 | } | |
285 | ||
1da177e4 LT |
286 | /** |
287 | * siimage_tune_chipset - set controller timings | |
288 | * @drive: Drive to set up | |
289 | * @xferspeed: speed we want to achieve | |
290 | * | |
291 | * Tune the SII chipset for the desired mode. If we can't achieve | |
292 | * the desired mode then tune for a lower one, but ultimately | |
293 | * make the thing work. | |
294 | */ | |
295 | ||
296 | static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed) | |
297 | { | |
298 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
299 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
300 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
301 | ||
302 | ide_hwif_t *hwif = HWIF(drive); | |
303 | u16 ultra = 0, multi = 0; | |
304 | u8 mode = 0, unit = drive->select.b.unit; | |
2d5eaa6d | 305 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
306 | unsigned long base = (unsigned long)hwif->hwif_data; |
307 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
308 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
309 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
310 | ||
311 | unsigned long ma = siimage_seldev(drive, 0x08); | |
312 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
313 | ||
314 | if (hwif->mmio) { | |
315 | scsc = hwif->INB(base + 0x4A); | |
316 | mode = hwif->INB(base + addr_mask); | |
317 | multi = hwif->INW(ma); | |
318 | ultra = hwif->INW(ua); | |
319 | } else { | |
320 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
321 | pci_read_config_byte(hwif->pci_dev, addr_mask, &mode); | |
322 | pci_read_config_word(hwif->pci_dev, ma, &multi); | |
323 | pci_read_config_word(hwif->pci_dev, ua, &ultra); | |
324 | } | |
325 | ||
326 | mode &= ~((unit) ? 0x30 : 0x03); | |
327 | ultra &= ~0x3F; | |
328 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
329 | ||
330 | scsc = is_sata(hwif) ? 1 : scsc; | |
331 | ||
332 | switch(speed) { | |
333 | case XFER_PIO_4: | |
334 | case XFER_PIO_3: | |
335 | case XFER_PIO_2: | |
336 | case XFER_PIO_1: | |
337 | case XFER_PIO_0: | |
338 | siimage_tuneproc(drive, (speed - XFER_PIO_0)); | |
339 | mode |= ((unit) ? 0x10 : 0x01); | |
340 | break; | |
341 | case XFER_MW_DMA_2: | |
342 | case XFER_MW_DMA_1: | |
343 | case XFER_MW_DMA_0: | |
344 | multi = dma[speed - XFER_MW_DMA_0]; | |
345 | mode |= ((unit) ? 0x20 : 0x02); | |
346 | config_siimage_chipset_for_pio(drive, 0); | |
347 | break; | |
348 | case XFER_UDMA_6: | |
349 | case XFER_UDMA_5: | |
350 | case XFER_UDMA_4: | |
351 | case XFER_UDMA_3: | |
352 | case XFER_UDMA_2: | |
353 | case XFER_UDMA_1: | |
354 | case XFER_UDMA_0: | |
355 | multi = dma[2]; | |
356 | ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : | |
357 | (ultra5[speed - XFER_UDMA_0])); | |
358 | mode |= ((unit) ? 0x30 : 0x03); | |
359 | config_siimage_chipset_for_pio(drive, 0); | |
360 | break; | |
361 | default: | |
362 | return 1; | |
363 | } | |
364 | ||
365 | if (hwif->mmio) { | |
366 | hwif->OUTB(mode, base + addr_mask); | |
367 | hwif->OUTW(multi, ma); | |
368 | hwif->OUTW(ultra, ua); | |
369 | } else { | |
370 | pci_write_config_byte(hwif->pci_dev, addr_mask, mode); | |
371 | pci_write_config_word(hwif->pci_dev, ma, multi); | |
372 | pci_write_config_word(hwif->pci_dev, ua, ultra); | |
373 | } | |
374 | return (ide_config_drive_speed(drive, speed)); | |
375 | } | |
376 | ||
377 | /** | |
378 | * config_chipset_for_dma - configure for DMA | |
379 | * @drive: drive to configure | |
380 | * | |
381 | * Called by the IDE layer when it wants the timings set up. | |
382 | * For the CMD680 we also need to set up the PIO timings and | |
383 | * enable DMA. | |
384 | */ | |
385 | ||
386 | static int config_chipset_for_dma (ide_drive_t *drive) | |
387 | { | |
2d5eaa6d | 388 | u8 speed = ide_max_dma_mode(drive); |
1da177e4 | 389 | |
1da177e4 LT |
390 | if (!speed) |
391 | return 0; | |
392 | ||
056a697b | 393 | if (siimage_tune_chipset(drive, speed)) |
1da177e4 LT |
394 | return 0; |
395 | ||
1da177e4 LT |
396 | return ide_dma_enable(drive); |
397 | } | |
398 | ||
399 | /** | |
400 | * siimage_configure_drive_for_dma - set up for DMA transfers | |
401 | * @drive: drive we are going to set up | |
402 | * | |
403 | * Set up the drive for DMA, tune the controller and drive as | |
404 | * required. If the drive isn't suitable for DMA or we hit | |
405 | * other problems then we will drop down to PIO and set up | |
406 | * PIO appropriately | |
407 | */ | |
408 | ||
409 | static int siimage_config_drive_for_dma (ide_drive_t *drive) | |
410 | { | |
7569e8dc | 411 | if (ide_use_dma(drive) && config_chipset_for_dma(drive)) |
3608b5d7 | 412 | return 0; |
1da177e4 | 413 | |
d8f4469d | 414 | if (ide_use_fast_pio(drive)) |
8e60d376 | 415 | config_siimage_chipset_for_pio(drive, 1); |
d8f4469d | 416 | |
3608b5d7 | 417 | return -1; |
1da177e4 LT |
418 | } |
419 | ||
420 | /* returns 1 if dma irq issued, 0 otherwise */ | |
421 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
422 | { | |
423 | ide_hwif_t *hwif = HWIF(drive); | |
424 | u8 dma_altstat = 0; | |
425 | unsigned long addr = siimage_selreg(hwif, 1); | |
426 | ||
427 | /* return 1 if INTR asserted */ | |
428 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
429 | return 1; | |
430 | ||
431 | /* return 1 if Device INTR asserted */ | |
432 | pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat); | |
433 | if (dma_altstat & 8) | |
434 | return 0; //return 1; | |
435 | return 0; | |
436 | } | |
437 | ||
1da177e4 LT |
438 | /** |
439 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
440 | * @drive: drive we are testing | |
441 | * | |
442 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
443 | * SATA status interrupts, if so we clean them up and continue. | |
444 | */ | |
445 | ||
446 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
447 | { | |
448 | ide_hwif_t *hwif = HWIF(drive); | |
449 | unsigned long base = (unsigned long)hwif->hwif_data; | |
450 | unsigned long addr = siimage_selreg(hwif, 0x1); | |
451 | ||
452 | if (SATA_ERROR_REG) { | |
0ecdca26 | 453 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
454 | u8 watchdog = 0; |
455 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
456 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
457 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 458 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
459 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
460 | "watchdog = %d, %s\n", | |
461 | drive->name, sata_error, watchdog, | |
462 | __FUNCTION__); | |
1da177e4 LT |
463 | |
464 | } else { | |
465 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
466 | } | |
467 | ext_stat >>= 16; | |
468 | ||
469 | if (!(ext_stat & 0x0404) && !watchdog) | |
470 | return 0; | |
471 | } | |
472 | ||
473 | /* return 1 if INTR asserted */ | |
0ecdca26 | 474 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
475 | return 1; |
476 | ||
477 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 478 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
479 | return 0; //return 1; |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | /** | |
485 | * siimage_busproc - bus isolation ioctl | |
486 | * @drive: drive to isolate/restore | |
487 | * @state: bus state to set | |
488 | * | |
489 | * Used by the SII3112 to handle bus isolation. As this is a | |
490 | * SATA controller the work required is quite limited, we | |
491 | * just have to clean up the statistics | |
492 | */ | |
493 | ||
494 | static int siimage_busproc (ide_drive_t * drive, int state) | |
495 | { | |
496 | ide_hwif_t *hwif = HWIF(drive); | |
497 | u32 stat_config = 0; | |
498 | unsigned long addr = siimage_selreg(hwif, 0); | |
499 | ||
0ecdca26 BZ |
500 | if (hwif->mmio) |
501 | stat_config = readl((void __iomem *)addr); | |
502 | else | |
1da177e4 LT |
503 | pci_read_config_dword(hwif->pci_dev, addr, &stat_config); |
504 | ||
505 | switch (state) { | |
506 | case BUSSTATE_ON: | |
507 | hwif->drives[0].failures = 0; | |
508 | hwif->drives[1].failures = 0; | |
509 | break; | |
510 | case BUSSTATE_OFF: | |
511 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
512 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
513 | break; | |
514 | case BUSSTATE_TRISTATE: | |
515 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
516 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
517 | break; | |
518 | default: | |
519 | return -EINVAL; | |
520 | } | |
521 | hwif->bus_state = state; | |
522 | return 0; | |
523 | } | |
524 | ||
525 | /** | |
526 | * siimage_reset_poll - wait for sata reset | |
527 | * @drive: drive we are resetting | |
528 | * | |
529 | * Poll the SATA phy and see whether it has come back from the dead | |
530 | * yet. | |
531 | */ | |
532 | ||
533 | static int siimage_reset_poll (ide_drive_t *drive) | |
534 | { | |
535 | if (SATA_STATUS_REG) { | |
536 | ide_hwif_t *hwif = HWIF(drive); | |
537 | ||
0ecdca26 BZ |
538 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
539 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 540 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 541 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
542 | HWGROUP(drive)->polling = 0; |
543 | return ide_started; | |
544 | } | |
545 | return 0; | |
546 | } else { | |
547 | return 0; | |
548 | } | |
549 | } | |
550 | ||
551 | /** | |
552 | * siimage_pre_reset - reset hook | |
553 | * @drive: IDE device being reset | |
554 | * | |
555 | * For the SATA devices we need to handle recalibration/geometry | |
556 | * differently | |
557 | */ | |
558 | ||
559 | static void siimage_pre_reset (ide_drive_t *drive) | |
560 | { | |
561 | if (drive->media != ide_disk) | |
562 | return; | |
563 | ||
564 | if (is_sata(HWIF(drive))) | |
565 | { | |
566 | drive->special.b.set_geometry = 0; | |
567 | drive->special.b.recalibrate = 0; | |
568 | } | |
569 | } | |
570 | ||
571 | /** | |
572 | * siimage_reset - reset a device on an siimage controller | |
573 | * @drive: drive to reset | |
574 | * | |
575 | * Perform a controller level reset fo the device. For | |
576 | * SATA we must also check the PHY. | |
577 | */ | |
578 | ||
579 | static void siimage_reset (ide_drive_t *drive) | |
580 | { | |
581 | ide_hwif_t *hwif = HWIF(drive); | |
582 | u8 reset = 0; | |
583 | unsigned long addr = siimage_selreg(hwif, 0); | |
584 | ||
585 | if (hwif->mmio) { | |
586 | reset = hwif->INB(addr); | |
587 | hwif->OUTB((reset|0x03), addr); | |
588 | /* FIXME:posting */ | |
589 | udelay(25); | |
590 | hwif->OUTB(reset, addr); | |
591 | (void) hwif->INB(addr); | |
592 | } else { | |
593 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
594 | pci_write_config_byte(hwif->pci_dev, addr, reset|0x03); | |
595 | udelay(25); | |
596 | pci_write_config_byte(hwif->pci_dev, addr, reset); | |
597 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
598 | } | |
599 | ||
600 | if (SATA_STATUS_REG) { | |
0ecdca26 BZ |
601 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
602 | u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); | |
1da177e4 LT |
603 | printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", |
604 | hwif->name, sata_stat, __FUNCTION__); | |
605 | if (!(sata_stat)) { | |
606 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", | |
607 | hwif->name, sata_stat); | |
608 | drive->failures++; | |
609 | } | |
610 | } | |
611 | ||
612 | } | |
613 | ||
614 | /** | |
615 | * proc_reports_siimage - add siimage controller to proc | |
616 | * @dev: PCI device | |
617 | * @clocking: SCSC value | |
618 | * @name: controller name | |
619 | * | |
620 | * Report the clocking mode of the controller and add it to | |
621 | * the /proc interface layer | |
622 | */ | |
623 | ||
624 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
625 | { | |
626 | if (!pdev_is_sata(dev)) { | |
627 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
628 | clocking &= 0x03; | |
629 | switch (clocking) { | |
630 | case 0x03: printk("DISABLED!\n"); break; | |
631 | case 0x02: printk("== 2X PCI\n"); break; | |
632 | case 0x01: printk("== 133\n"); break; | |
633 | case 0x00: printk("== 100\n"); break; | |
634 | } | |
635 | } | |
636 | } | |
637 | ||
638 | /** | |
639 | * setup_mmio_siimage - switch an SI controller into MMIO | |
640 | * @dev: PCI device we are configuring | |
641 | * @name: device name | |
642 | * | |
643 | * Attempt to put the device into mmio mode. There are some slight | |
644 | * complications here with certain systems where the mmio bar isnt | |
645 | * mapped so we have to be sure we can fall back to I/O. | |
646 | */ | |
647 | ||
648 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
649 | { | |
650 | unsigned long bar5 = pci_resource_start(dev, 5); | |
651 | unsigned long barsize = pci_resource_len(dev, 5); | |
652 | u8 tmpbyte = 0; | |
653 | void __iomem *ioaddr; | |
d868dd19 | 654 | u32 tmp, irq_mask; |
1da177e4 LT |
655 | |
656 | /* | |
657 | * Drop back to PIO if we can't map the mmio. Some | |
658 | * systems seem to get terminally confused in the PCI | |
659 | * spaces. | |
660 | */ | |
661 | ||
662 | if(!request_mem_region(bar5, barsize, name)) | |
663 | { | |
664 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | ioaddr = ioremap(bar5, barsize); | |
669 | ||
670 | if (ioaddr == NULL) | |
671 | { | |
672 | release_mem_region(bar5, barsize); | |
673 | return 0; | |
674 | } | |
675 | ||
676 | pci_set_master(dev); | |
677 | pci_set_drvdata(dev, (void *) ioaddr); | |
678 | ||
679 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
680 | /* make sure IDE0/1 interrupts are not masked */ |
681 | irq_mask = (1 << 22) | (1 << 23); | |
682 | tmp = readl(ioaddr + 0x48); | |
683 | if (tmp & irq_mask) { | |
684 | tmp &= ~irq_mask; | |
685 | writel(tmp, ioaddr + 0x48); | |
686 | readl(ioaddr + 0x48); /* flush */ | |
687 | } | |
1da177e4 LT |
688 | writel(0, ioaddr + 0x148); |
689 | writel(0, ioaddr + 0x1C8); | |
690 | } | |
691 | ||
692 | writeb(0, ioaddr + 0xB4); | |
693 | writeb(0, ioaddr + 0xF4); | |
694 | tmpbyte = readb(ioaddr + 0x4A); | |
695 | ||
696 | switch(tmpbyte & 0x30) { | |
697 | case 0x00: | |
698 | /* In 100 MHz clocking, try and switch to 133 */ | |
699 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
700 | break; | |
701 | case 0x10: | |
702 | /* On 133Mhz clocking */ | |
703 | break; | |
704 | case 0x20: | |
705 | /* On PCIx2 clocking */ | |
706 | break; | |
707 | case 0x30: | |
708 | /* Clocking is disabled */ | |
709 | /* 133 clock attempt to force it on */ | |
710 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
711 | break; | |
712 | } | |
713 | ||
714 | writeb( 0x72, ioaddr + 0xA1); | |
715 | writew( 0x328A, ioaddr + 0xA2); | |
716 | writel(0x62DD62DD, ioaddr + 0xA4); | |
717 | writel(0x43924392, ioaddr + 0xA8); | |
718 | writel(0x40094009, ioaddr + 0xAC); | |
719 | writeb( 0x72, ioaddr + 0xE1); | |
720 | writew( 0x328A, ioaddr + 0xE2); | |
721 | writel(0x62DD62DD, ioaddr + 0xE4); | |
722 | writel(0x43924392, ioaddr + 0xE8); | |
723 | writel(0x40094009, ioaddr + 0xEC); | |
724 | ||
725 | if (pdev_is_sata(dev)) { | |
726 | writel(0xFFFF0000, ioaddr + 0x108); | |
727 | writel(0xFFFF0000, ioaddr + 0x188); | |
728 | writel(0x00680000, ioaddr + 0x148); | |
729 | writel(0x00680000, ioaddr + 0x1C8); | |
730 | } | |
731 | ||
732 | tmpbyte = readb(ioaddr + 0x4A); | |
733 | ||
734 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
735 | return 1; | |
736 | } | |
737 | ||
738 | /** | |
739 | * init_chipset_siimage - set up an SI device | |
740 | * @dev: PCI device | |
741 | * @name: device name | |
742 | * | |
743 | * Perform the initial PCI set up for this device. Attempt to switch | |
744 | * to 133MHz clocking if the system isn't already set up to do it. | |
745 | */ | |
746 | ||
747 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
748 | { | |
749 | u32 class_rev = 0; | |
750 | u8 tmpbyte = 0; | |
751 | u8 BA5_EN = 0; | |
752 | ||
753 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
754 | class_rev &= 0xff; | |
755 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
756 | ||
757 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
758 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
759 | if (setup_mmio_siimage(dev, name)) { | |
760 | return 0; | |
761 | } | |
762 | } | |
763 | ||
764 | pci_write_config_byte(dev, 0x80, 0x00); | |
765 | pci_write_config_byte(dev, 0x84, 0x00); | |
766 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
767 | switch(tmpbyte & 0x30) { | |
768 | case 0x00: | |
769 | /* 133 clock attempt to force it on */ | |
770 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
771 | case 0x30: | |
772 | /* if clocking is disabled */ | |
773 | /* 133 clock attempt to force it on */ | |
774 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
775 | case 0x10: | |
776 | /* 133 already */ | |
777 | break; | |
778 | case 0x20: | |
779 | /* BIOS set PCI x2 clocking */ | |
780 | break; | |
781 | } | |
782 | ||
783 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
784 | ||
785 | pci_write_config_byte(dev, 0xA1, 0x72); | |
786 | pci_write_config_word(dev, 0xA2, 0x328A); | |
787 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
788 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
789 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
790 | pci_write_config_byte(dev, 0xB1, 0x72); | |
791 | pci_write_config_word(dev, 0xB2, 0x328A); | |
792 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
793 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
794 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
795 | ||
796 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
797 | return 0; | |
798 | } | |
799 | ||
800 | /** | |
801 | * init_mmio_iops_siimage - set up the iops for MMIO | |
802 | * @hwif: interface to set up | |
803 | * | |
804 | * The basic setup here is fairly simple, we can use standard MMIO | |
805 | * operations. However we do have to set the taskfile register offsets | |
806 | * by hand as there isnt a standard defined layout for them this | |
807 | * time. | |
808 | * | |
809 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 810 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
811 | */ |
812 | ||
813 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
814 | { | |
815 | struct pci_dev *dev = hwif->pci_dev; | |
816 | void *addr = pci_get_drvdata(dev); | |
817 | u8 ch = hwif->channel; | |
818 | hw_regs_t hw; | |
819 | unsigned long base; | |
820 | ||
821 | /* | |
822 | * Fill in the basic HWIF bits | |
823 | */ | |
824 | ||
825 | default_hwif_mmiops(hwif); | |
826 | hwif->hwif_data = addr; | |
827 | ||
828 | /* | |
829 | * Now set up the hw. We have to do this ourselves as | |
830 | * the MMIO layout isnt the same as the the standard port | |
831 | * based I/O | |
832 | */ | |
833 | ||
834 | memset(&hw, 0, sizeof(hw_regs_t)); | |
835 | ||
836 | base = (unsigned long)addr; | |
837 | if (ch) | |
838 | base += 0xC0; | |
839 | else | |
840 | base += 0x80; | |
841 | ||
842 | /* | |
843 | * The buffered task file doesn't have status/control | |
844 | * so we can't currently use it sanely since we want to | |
845 | * use LBA48 mode. | |
846 | */ | |
1da177e4 LT |
847 | hw.io_ports[IDE_DATA_OFFSET] = base; |
848 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
849 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
850 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
851 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
852 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
853 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
854 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
855 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
856 | ||
857 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
858 | ||
859 | if (pdev_is_sata(dev)) { | |
860 | base = (unsigned long)addr; | |
861 | if (ch) | |
862 | base += 0x80; | |
863 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
864 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
865 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
866 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
867 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
868 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
869 | } | |
870 | ||
871 | hw.irq = hwif->pci_dev->irq; | |
872 | ||
873 | memcpy(&hwif->hw, &hw, sizeof(hw)); | |
874 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports)); | |
875 | ||
876 | hwif->irq = hw.irq; | |
877 | ||
878 | base = (unsigned long) addr; | |
879 | ||
1da177e4 | 880 | hwif->dma_base = base + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
881 | |
882 | hwif->mmio = 1; | |
1da177e4 LT |
883 | } |
884 | ||
885 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
886 | { | |
887 | const char *s = &drive->id->model[0]; | |
888 | unsigned len; | |
889 | ||
890 | if (!drive->present) | |
891 | return 0; | |
892 | ||
893 | len = strnlen(s, sizeof(drive->id->model)); | |
894 | ||
895 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
896 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
897 | (!memcmp(s + len - 3, "ASL", 3))) { | |
898 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
899 | "errata fix\n", drive->name); | |
900 | return 1; | |
901 | } | |
902 | } | |
903 | return 0; | |
904 | } | |
905 | ||
906 | /** | |
907 | * siimage_fixup - post probe fixups | |
908 | * @hwif: interface to fix up | |
909 | * | |
910 | * Called after drive probe we use this to decide whether the | |
911 | * Seagate fixup must be applied. This used to be in init_iops but | |
912 | * that can occur before we know what drives are present. | |
913 | */ | |
914 | ||
915 | static void __devinit siimage_fixup(ide_hwif_t *hwif) | |
916 | { | |
917 | /* Try and raise the rqsize */ | |
918 | if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0])) | |
919 | hwif->rqsize = 128; | |
920 | } | |
921 | ||
922 | /** | |
923 | * init_iops_siimage - set up iops | |
924 | * @hwif: interface to set up | |
925 | * | |
926 | * Do the basic setup for the SIIMAGE hardware interface | |
927 | * and then do the MMIO setup if we can. This is the first | |
928 | * look in we get for setting up the hwif so that we | |
929 | * can get the iops right before using them. | |
930 | */ | |
931 | ||
932 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
933 | { | |
934 | struct pci_dev *dev = hwif->pci_dev; | |
935 | u32 class_rev = 0; | |
936 | ||
937 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
938 | class_rev &= 0xff; | |
939 | ||
940 | hwif->hwif_data = NULL; | |
941 | ||
942 | /* Pessimal until we finish probing */ | |
943 | hwif->rqsize = 15; | |
944 | ||
945 | if (pci_get_drvdata(dev) == NULL) | |
946 | return; | |
947 | init_mmio_iops_siimage(hwif); | |
948 | } | |
949 | ||
950 | /** | |
951 | * ata66_siimage - check for 80 pin cable | |
952 | * @hwif: interface to check | |
953 | * | |
954 | * Check for the presence of an ATA66 capable cable on the | |
955 | * interface. | |
956 | */ | |
957 | ||
958 | static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif) | |
959 | { | |
960 | unsigned long addr = siimage_selreg(hwif, 0); | |
961 | if (pci_get_drvdata(hwif->pci_dev) == NULL) { | |
962 | u8 ata66 = 0; | |
963 | pci_read_config_byte(hwif->pci_dev, addr, &ata66); | |
964 | return (ata66 & 0x01) ? 1 : 0; | |
965 | } | |
966 | ||
967 | return (hwif->INB(addr) & 0x01) ? 1 : 0; | |
968 | } | |
969 | ||
970 | /** | |
971 | * init_hwif_siimage - set up hwif structs | |
972 | * @hwif: interface to set up | |
973 | * | |
974 | * We do the basic set up of the interface structure. The SIIMAGE | |
975 | * requires several custom handlers so we override the default | |
976 | * ide DMA handlers appropriately | |
977 | */ | |
978 | ||
979 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
980 | { | |
981 | hwif->autodma = 0; | |
982 | ||
983 | hwif->resetproc = &siimage_reset; | |
984 | hwif->speedproc = &siimage_tune_chipset; | |
985 | hwif->tuneproc = &siimage_tuneproc; | |
986 | hwif->reset_poll = &siimage_reset_poll; | |
987 | hwif->pre_reset = &siimage_pre_reset; | |
2d5eaa6d | 988 | hwif->udma_filter = &sil_udma_filter; |
1da177e4 | 989 | |
19c1ef5f AC |
990 | if(is_sata(hwif)) { |
991 | static int first = 1; | |
992 | ||
1da177e4 LT |
993 | hwif->busproc = &siimage_busproc; |
994 | ||
19c1ef5f AC |
995 | if (first) { |
996 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
997 | first = 0; | |
998 | } | |
999 | } | |
1da177e4 LT |
1000 | if (!hwif->dma_base) { |
1001 | hwif->drives[0].autotune = 1; | |
1002 | hwif->drives[1].autotune = 1; | |
1003 | return; | |
1004 | } | |
1005 | ||
1006 | hwif->ultra_mask = 0x7f; | |
1007 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
1008 | |
1009 | if (!is_sata(hwif)) | |
1010 | hwif->atapi_dma = 1; | |
1011 | ||
1012 | hwif->ide_dma_check = &siimage_config_drive_for_dma; | |
1013 | if (!(hwif->udma_four)) | |
1014 | hwif->udma_four = ata66_siimage(hwif); | |
1015 | ||
1016 | if (hwif->mmio) { | |
1017 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
1018 | } else { | |
1019 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * The BIOS often doesn't set up DMA on this controller | |
1024 | * so we always do it. | |
1025 | */ | |
1026 | ||
1027 | hwif->autodma = 1; | |
1028 | hwif->drives[0].autodma = hwif->autodma; | |
1029 | hwif->drives[1].autodma = hwif->autodma; | |
1030 | } | |
1031 | ||
1032 | #define DECLARE_SII_DEV(name_str) \ | |
1033 | { \ | |
1034 | .name = name_str, \ | |
1035 | .init_chipset = init_chipset_siimage, \ | |
1036 | .init_iops = init_iops_siimage, \ | |
1037 | .init_hwif = init_hwif_siimage, \ | |
1038 | .fixup = siimage_fixup, \ | |
1039 | .channels = 2, \ | |
1040 | .autodma = AUTODMA, \ | |
1041 | .bootable = ON_BOARD, \ | |
1042 | } | |
1043 | ||
1044 | static ide_pci_device_t siimage_chipsets[] __devinitdata = { | |
1045 | /* 0 */ DECLARE_SII_DEV("SiI680"), | |
1046 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
1047 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
1048 | }; | |
1049 | ||
1050 | /** | |
1051 | * siimage_init_one - pci layer discovery entry | |
1052 | * @dev: PCI device | |
1053 | * @id: ident table entry | |
1054 | * | |
1055 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
1056 | * We then use the IDE PCI generic helper to do most of the work. | |
1057 | */ | |
1058 | ||
1059 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
1060 | { | |
1061 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
1062 | } | |
1063 | ||
1064 | static struct pci_device_id siimage_pci_tbl[] = { | |
28a2a3f5 | 1065 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 | 1066 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
28a2a3f5 AC |
1067 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1068 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
1da177e4 LT |
1069 | #endif |
1070 | { 0, }, | |
1071 | }; | |
1072 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
1073 | ||
1074 | static struct pci_driver driver = { | |
1075 | .name = "SiI_IDE", | |
1076 | .id_table = siimage_pci_tbl, | |
1077 | .probe = siimage_init_one, | |
1078 | }; | |
1079 | ||
82ab1eec | 1080 | static int __init siimage_ide_init(void) |
1da177e4 LT |
1081 | { |
1082 | return ide_pci_register_driver(&driver); | |
1083 | } | |
1084 | ||
1085 | module_init(siimage_ide_init); | |
1086 | ||
1087 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
1088 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
1089 | MODULE_LICENSE("GPL"); |