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1da177e4 | 1 | /* |
0d3be723 | 2 | * linux/drivers/ide/pci/sis5513.c Version 0.27 Jul 14, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
6 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
6b8cf772 BZ |
7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
8 | * | |
1da177e4 LT |
9 | * May be copied or modified under the terms of the GNU General Public License |
10 | * | |
11 | * | |
12 | * Thanks : | |
13 | * | |
14 | * SiS Taiwan : for direct support and hardware. | |
15 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
16 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
17 | * for checking code correctness, providing patches. | |
18 | * | |
19 | * | |
20 | * Original tests and design on the SiS620 chipset. | |
21 | * ATA100 tests and design on the SiS735 chipset. | |
22 | * ATA16/33 support from specs | |
23 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
24 | * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz> | |
25 | * | |
26 | * Documentation: | |
27 | * SiS chipset documentation available under NDA to companies only | |
28 | * (not to individuals). | |
29 | */ | |
30 | ||
31 | /* | |
32 | * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original | |
33 | * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511 | |
34 | * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip. | |
35 | * | |
36 | * Later SiS chipsets integrated the 5513 functionality into the NorthBridge, | |
37 | * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We | |
38 | * can figure out that we have a more modern and more capable 5513 by looking | |
39 | * for the respective NorthBridge IDs. | |
40 | * | |
41 | * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513 | |
42 | * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI | |
43 | * ID, while the now ATA-133 capable 5513 still has the same PCI ID. | |
44 | * Fortunately the 5513 can be 'unmasked' by fiddling with some config space | |
45 | * bits, changing its device id to the true one - 5517 for 961 and 5518 for | |
46 | * 962/963. | |
47 | */ | |
48 | ||
1da177e4 LT |
49 | #include <linux/types.h> |
50 | #include <linux/module.h> | |
51 | #include <linux/kernel.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/timer.h> | |
54 | #include <linux/mm.h> | |
55 | #include <linux/ioport.h> | |
56 | #include <linux/blkdev.h> | |
57 | #include <linux/hdreg.h> | |
58 | ||
59 | #include <linux/interrupt.h> | |
60 | #include <linux/pci.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/ide.h> | |
63 | ||
64 | #include <asm/irq.h> | |
65 | ||
66 | #include "ide-timing.h" | |
67 | ||
68 | #define DISPLAY_SIS_TIMINGS | |
69 | ||
70 | /* registers layout and init values are chipset family dependant */ | |
71 | ||
72 | #define ATA_16 0x01 | |
73 | #define ATA_33 0x02 | |
74 | #define ATA_66 0x03 | |
75 | #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout | |
76 | #define ATA_100 0x05 | |
77 | #define ATA_133a 0x06 // SiS961b with 133 support | |
78 | #define ATA_133 0x07 // SiS962/963 | |
79 | ||
80 | static u8 chipset_family; | |
81 | ||
82 | /* | |
83 | * Devices supported | |
84 | */ | |
85 | static const struct { | |
86 | const char *name; | |
87 | u16 host_id; | |
88 | u8 chipset_family; | |
89 | u8 flags; | |
90 | } SiSHostChipInfo[] = { | |
47d4b906 DW |
91 | { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 }, |
92 | { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 }, | |
14351f8e | 93 | { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 }, |
1da177e4 LT |
94 | { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 }, |
95 | { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 }, | |
96 | { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 }, | |
97 | { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 }, | |
98 | { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 }, | |
99 | ||
100 | { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a }, | |
101 | { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a }, | |
102 | ||
103 | { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 }, | |
104 | { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 }, | |
105 | { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 }, | |
106 | { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 }, | |
107 | { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 }, | |
108 | ||
109 | { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 }, | |
110 | { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 }, | |
111 | { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 }, | |
112 | { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 }, | |
113 | { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 }, | |
114 | { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 }, | |
115 | ||
116 | { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 }, | |
117 | { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 }, | |
d266ab88 | 118 | { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 }, |
1da177e4 LT |
119 | { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 }, |
120 | }; | |
121 | ||
122 | /* Cycle time bits and values vary across chip dma capabilities | |
123 | These three arrays hold the register layout and the values to set. | |
124 | Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ | |
125 | ||
126 | /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ | |
127 | static u8 cycle_time_offset[] = {0,0,5,4,4,0,0}; | |
128 | static u8 cycle_time_range[] = {0,0,2,3,3,4,4}; | |
129 | static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
130 | {0,0,0,0,0,0,0}, /* no udma */ | |
131 | {0,0,0,0,0,0,0}, /* no udma */ | |
132 | {3,2,1,0,0,0,0}, /* ATA_33 */ | |
133 | {7,5,3,2,1,0,0}, /* ATA_66 */ | |
134 | {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */ | |
135 | {11,7,5,4,2,1,0}, /* ATA_100 */ | |
136 | {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */ | |
137 | {15,10,7,5,3,2,1}, /* ATA_133 */ | |
138 | }; | |
139 | /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 | |
140 | See SiS962 data sheet for more detail */ | |
141 | static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
142 | {0,0,0,0,0,0,0}, /* no udma */ | |
143 | {0,0,0,0,0,0,0}, /* no udma */ | |
144 | {2,1,1,0,0,0,0}, | |
145 | {4,3,2,1,0,0,0}, | |
146 | {4,3,2,1,0,0,0}, | |
147 | {6,4,3,1,1,1,0}, | |
148 | {9,6,4,2,2,2,2}, | |
149 | {9,6,4,2,2,2,2}, | |
150 | }; | |
151 | /* Initialize time, Active time, Recovery time vary across | |
152 | IDE clock settings. These 3 arrays hold the register value | |
153 | for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ | |
154 | static u8 ini_time_value[][8] = { | |
155 | {0,0,0,0,0,0,0,0}, | |
156 | {0,0,0,0,0,0,0,0}, | |
157 | {2,1,0,0,0,1,0,0}, | |
158 | {4,3,1,1,1,3,1,1}, | |
159 | {4,3,1,1,1,3,1,1}, | |
160 | {6,4,2,2,2,4,2,2}, | |
161 | {9,6,3,3,3,6,3,3}, | |
162 | {9,6,3,3,3,6,3,3}, | |
163 | }; | |
164 | static u8 act_time_value[][8] = { | |
165 | {0,0,0,0,0,0,0,0}, | |
166 | {0,0,0,0,0,0,0,0}, | |
167 | {9,9,9,2,2,7,2,2}, | |
168 | {19,19,19,5,4,14,5,4}, | |
169 | {19,19,19,5,4,14,5,4}, | |
170 | {28,28,28,7,6,21,7,6}, | |
171 | {38,38,38,10,9,28,10,9}, | |
172 | {38,38,38,10,9,28,10,9}, | |
173 | }; | |
174 | static u8 rco_time_value[][8] = { | |
175 | {0,0,0,0,0,0,0,0}, | |
176 | {0,0,0,0,0,0,0,0}, | |
177 | {9,2,0,2,0,7,1,1}, | |
178 | {19,5,1,5,2,16,3,2}, | |
179 | {19,5,1,5,2,16,3,2}, | |
180 | {30,9,3,9,4,25,6,4}, | |
181 | {40,12,4,12,5,34,12,5}, | |
182 | {40,12,4,12,5,34,12,5}, | |
183 | }; | |
184 | ||
185 | /* | |
186 | * Printing configuration | |
187 | */ | |
188 | /* Used for chipset type printing at boot time */ | |
189 | static char* chipset_capability[] = { | |
190 | "ATA", "ATA 16", | |
191 | "ATA 33", "ATA 66", | |
192 | "ATA 100 (1st gen)", "ATA 100 (2nd gen)", | |
193 | "ATA 133 (1st gen)", "ATA 133 (2nd gen)" | |
194 | }; | |
195 | ||
ecfd80e4 | 196 | #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
1da177e4 LT |
197 | #include <linux/stat.h> |
198 | #include <linux/proc_fs.h> | |
199 | ||
200 | static u8 sis_proc = 0; | |
201 | ||
202 | static struct pci_dev *bmide_dev; | |
203 | ||
204 | static char* cable_type[] = { | |
205 | "80 pins", | |
206 | "40 pins" | |
207 | }; | |
208 | ||
209 | static char* recovery_time[] ={ | |
210 | "12 PCICLK", "1 PCICLK", | |
211 | "2 PCICLK", "3 PCICLK", | |
212 | "4 PCICLK", "5 PCICLCK", | |
213 | "6 PCICLK", "7 PCICLCK", | |
214 | "8 PCICLK", "9 PCICLCK", | |
215 | "10 PCICLK", "11 PCICLK", | |
216 | "13 PCICLK", "14 PCICLK", | |
217 | "15 PCICLK", "15 PCICLK" | |
218 | }; | |
219 | ||
220 | static char* active_time[] = { | |
221 | "8 PCICLK", "1 PCICLCK", | |
222 | "2 PCICLK", "3 PCICLK", | |
223 | "4 PCICLK", "5 PCICLK", | |
224 | "6 PCICLK", "12 PCICLK" | |
225 | }; | |
226 | ||
227 | static char* cycle_time[] = { | |
228 | "Reserved", "2 CLK", | |
229 | "3 CLK", "4 CLK", | |
230 | "5 CLK", "6 CLK", | |
231 | "7 CLK", "8 CLK", | |
232 | "9 CLK", "10 CLK", | |
233 | "11 CLK", "12 CLK", | |
234 | "13 CLK", "14 CLK", | |
235 | "15 CLK", "16 CLK" | |
236 | }; | |
237 | ||
238 | /* Generic add master or slave info function */ | |
239 | static char* get_drives_info (char *buffer, u8 pos) | |
240 | { | |
241 | u8 reg00, reg01, reg10, reg11; /* timing registers */ | |
242 | u32 regdw0, regdw1; | |
243 | char* p = buffer; | |
244 | ||
245 | /* Postwrite/Prefetch */ | |
246 | if (chipset_family < ATA_133) { | |
247 | pci_read_config_byte(bmide_dev, 0x4b, ®00); | |
248 | p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n", | |
249 | pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled", | |
250 | (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled"); | |
251 | p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n", | |
252 | (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled", | |
253 | (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled"); | |
254 | pci_read_config_byte(bmide_dev, 0x40+2*pos, ®00); | |
255 | pci_read_config_byte(bmide_dev, 0x41+2*pos, ®01); | |
256 | pci_read_config_byte(bmide_dev, 0x44+2*pos, ®10); | |
257 | pci_read_config_byte(bmide_dev, 0x45+2*pos, ®11); | |
258 | } else { | |
259 | u32 reg54h; | |
260 | u8 drive_pci = 0x40; | |
261 | pci_read_config_dword(bmide_dev, 0x54, ®54h); | |
262 | if (reg54h & 0x40000000) { | |
263 | // Configuration space remapped to 0x70 | |
264 | drive_pci = 0x70; | |
265 | } | |
266 | pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, ®dw0); | |
267 | pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, ®dw1); | |
268 | ||
269 | p += sprintf(p, "Drive %d:\n", pos); | |
270 | } | |
271 | ||
272 | ||
273 | /* UDMA */ | |
274 | if (chipset_family >= ATA_133) { | |
275 | p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n", | |
276 | (regdw0 & 0x04) ? "Enabled" : "Disabled", | |
277 | (regdw1 & 0x04) ? "Enabled" : "Disabled"); | |
278 | p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n", | |
279 | cycle_time[(regdw0 & 0xF0) >> 4], | |
280 | cycle_time[(regdw1 & 0xF0) >> 4]); | |
281 | } else if (chipset_family >= ATA_33) { | |
282 | p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n", | |
283 | (reg01 & 0x80) ? "Enabled" : "Disabled", | |
284 | (reg11 & 0x80) ? "Enabled" : "Disabled"); | |
285 | ||
286 | p += sprintf(p, " UDMA Cycle Time "); | |
287 | switch(chipset_family) { | |
288 | case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break; | |
289 | case ATA_66: | |
290 | case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break; | |
291 | case ATA_100: | |
292 | case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break; | |
293 | default: p += sprintf(p, "?"); break; | |
294 | } | |
295 | p += sprintf(p, " \t UDMA Cycle Time "); | |
296 | switch(chipset_family) { | |
297 | case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break; | |
298 | case ATA_66: | |
299 | case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break; | |
300 | case ATA_100: | |
301 | case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break; | |
302 | default: p += sprintf(p, "?"); break; | |
303 | } | |
304 | p += sprintf(p, "\n"); | |
305 | } | |
306 | ||
307 | ||
308 | if (chipset_family < ATA_133) { /* else case TODO */ | |
309 | ||
310 | /* Data Active */ | |
311 | p += sprintf(p, " Data Active Time "); | |
312 | switch(chipset_family) { | |
313 | case ATA_16: /* confirmed */ | |
314 | case ATA_33: | |
315 | case ATA_66: | |
316 | case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break; | |
317 | case ATA_100: | |
318 | case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break; | |
319 | default: p += sprintf(p, "?"); break; | |
320 | } | |
321 | p += sprintf(p, " \t Data Active Time "); | |
322 | switch(chipset_family) { | |
323 | case ATA_16: | |
324 | case ATA_33: | |
325 | case ATA_66: | |
326 | case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break; | |
327 | case ATA_100: | |
328 | case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break; | |
329 | default: p += sprintf(p, "?"); break; | |
330 | } | |
331 | p += sprintf(p, "\n"); | |
332 | ||
333 | /* Data Recovery */ | |
334 | /* warning: may need (reg&0x07) for pre ATA66 chips */ | |
335 | p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n", | |
336 | recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]); | |
337 | } | |
338 | ||
339 | return p; | |
340 | } | |
341 | ||
342 | static char* get_masters_info(char* buffer) | |
343 | { | |
344 | return get_drives_info(buffer, 0); | |
345 | } | |
346 | ||
347 | static char* get_slaves_info(char* buffer) | |
348 | { | |
349 | return get_drives_info(buffer, 1); | |
350 | } | |
351 | ||
352 | /* Main get_info, called on /proc/ide/sis reads */ | |
353 | static int sis_get_info (char *buffer, char **addr, off_t offset, int count) | |
354 | { | |
355 | char *p = buffer; | |
356 | int len; | |
357 | u8 reg; | |
358 | u16 reg2, reg3; | |
359 | ||
360 | p += sprintf(p, "\nSiS 5513 "); | |
361 | switch(chipset_family) { | |
362 | case ATA_16: p += sprintf(p, "DMA 16"); break; | |
363 | case ATA_33: p += sprintf(p, "Ultra 33"); break; | |
364 | case ATA_66: p += sprintf(p, "Ultra 66"); break; | |
365 | case ATA_100a: | |
366 | case ATA_100: p += sprintf(p, "Ultra 100"); break; | |
367 | case ATA_133a: | |
368 | case ATA_133: p += sprintf(p, "Ultra 133"); break; | |
369 | default: p+= sprintf(p, "Unknown???"); break; | |
370 | } | |
371 | p += sprintf(p, " chipset\n"); | |
372 | p += sprintf(p, "--------------- Primary Channel " | |
373 | "---------------- Secondary Channel " | |
374 | "-------------\n"); | |
375 | ||
376 | /* Status */ | |
377 | pci_read_config_byte(bmide_dev, 0x4a, ®); | |
378 | if (chipset_family == ATA_133) { | |
379 | pci_read_config_word(bmide_dev, 0x50, ®2); | |
380 | pci_read_config_word(bmide_dev, 0x52, ®3); | |
381 | } | |
382 | p += sprintf(p, "Channel Status: "); | |
383 | if (chipset_family < ATA_66) { | |
384 | p += sprintf(p, "%s \t \t \t \t %s\n", | |
385 | (reg & 0x04) ? "On" : "Off", | |
386 | (reg & 0x02) ? "On" : "Off"); | |
387 | } else if (chipset_family < ATA_133) { | |
388 | p += sprintf(p, "%s \t \t \t \t %s \n", | |
389 | (reg & 0x02) ? "On" : "Off", | |
390 | (reg & 0x04) ? "On" : "Off"); | |
391 | } else { /* ATA_133 */ | |
392 | p += sprintf(p, "%s \t \t \t \t %s \n", | |
393 | (reg2 & 0x02) ? "On" : "Off", | |
394 | (reg3 & 0x02) ? "On" : "Off"); | |
395 | } | |
396 | ||
397 | /* Operation Mode */ | |
398 | pci_read_config_byte(bmide_dev, 0x09, ®); | |
399 | p += sprintf(p, "Operation Mode: %s \t \t \t %s \n", | |
400 | (reg & 0x01) ? "Native" : "Compatible", | |
401 | (reg & 0x04) ? "Native" : "Compatible"); | |
402 | ||
403 | /* 80-pin cable ? */ | |
404 | if (chipset_family >= ATA_133) { | |
405 | p += sprintf(p, "Cable Type: %s \t \t \t %s\n", | |
406 | (reg2 & 0x01) ? cable_type[1] : cable_type[0], | |
407 | (reg3 & 0x01) ? cable_type[1] : cable_type[0]); | |
408 | } else if (chipset_family > ATA_33) { | |
409 | pci_read_config_byte(bmide_dev, 0x48, ®); | |
410 | p += sprintf(p, "Cable Type: %s \t \t \t %s\n", | |
411 | (reg & 0x10) ? cable_type[1] : cable_type[0], | |
412 | (reg & 0x20) ? cable_type[1] : cable_type[0]); | |
413 | } | |
414 | ||
415 | /* Prefetch Count */ | |
416 | if (chipset_family < ATA_133) { | |
417 | pci_read_config_word(bmide_dev, 0x4c, ®2); | |
418 | pci_read_config_word(bmide_dev, 0x4e, ®3); | |
419 | p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n", | |
420 | reg2, reg3); | |
421 | } | |
422 | ||
423 | p = get_masters_info(p); | |
424 | p = get_slaves_info(p); | |
425 | ||
426 | len = (p - buffer) - offset; | |
427 | *addr = buffer + offset; | |
428 | ||
429 | return len > count ? count : len; | |
430 | } | |
ecfd80e4 | 431 | #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ |
1da177e4 | 432 | |
1da177e4 LT |
433 | /* |
434 | * Configuration functions | |
435 | */ | |
436 | /* Enables per-drive prefetch and postwrite */ | |
437 | static void config_drive_art_rwp (ide_drive_t *drive) | |
438 | { | |
439 | ide_hwif_t *hwif = HWIF(drive); | |
440 | struct pci_dev *dev = hwif->pci_dev; | |
441 | ||
442 | u8 reg4bh = 0; | |
443 | u8 rw_prefetch = (0x11 << drive->dn); | |
444 | ||
445 | if (drive->media != ide_disk) | |
446 | return; | |
447 | pci_read_config_byte(dev, 0x4b, ®4bh); | |
448 | ||
449 | if ((reg4bh & rw_prefetch) != rw_prefetch) | |
450 | pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch); | |
451 | } | |
452 | ||
1da177e4 | 453 | /* Set per-drive active and recovery time */ |
88b2b32b | 454 | static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
455 | { |
456 | ide_hwif_t *hwif = HWIF(drive); | |
457 | struct pci_dev *dev = hwif->pci_dev; | |
458 | ||
6b8cf772 | 459 | u8 drive_pci, test1, test2; |
1da177e4 LT |
460 | |
461 | config_drive_art_rwp(drive); | |
1da177e4 LT |
462 | |
463 | /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */ | |
464 | drive_pci = 0x40; | |
465 | /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */ | |
466 | if (chipset_family >= ATA_133) { | |
467 | u32 reg54h; | |
468 | pci_read_config_dword(dev, 0x54, ®54h); | |
469 | if (reg54h & 0x40000000) drive_pci = 0x70; | |
470 | drive_pci += ((drive->dn)*0x4); | |
471 | } else { | |
472 | drive_pci += ((drive->dn)*0x2); | |
473 | } | |
474 | ||
475 | /* register layout changed with newer ATA100 chips */ | |
476 | if (chipset_family < ATA_100) { | |
477 | pci_read_config_byte(dev, drive_pci, &test1); | |
478 | pci_read_config_byte(dev, drive_pci+1, &test2); | |
479 | ||
480 | /* Clear active and recovery timings */ | |
481 | test1 &= ~0x0F; | |
482 | test2 &= ~0x07; | |
483 | ||
6b8cf772 | 484 | switch(pio) { |
1da177e4 LT |
485 | case 4: test1 |= 0x01; test2 |= 0x03; break; |
486 | case 3: test1 |= 0x03; test2 |= 0x03; break; | |
487 | case 2: test1 |= 0x04; test2 |= 0x04; break; | |
488 | case 1: test1 |= 0x07; test2 |= 0x06; break; | |
6b8cf772 | 489 | case 0: /* PIO0: register setting == X000 */ |
1da177e4 LT |
490 | default: break; |
491 | } | |
492 | pci_write_config_byte(dev, drive_pci, test1); | |
493 | pci_write_config_byte(dev, drive_pci+1, test2); | |
494 | } else if (chipset_family < ATA_133) { | |
6b8cf772 | 495 | switch(pio) { /* active recovery |
1da177e4 LT |
496 | v v */ |
497 | case 4: test1 = 0x30|0x01; break; | |
498 | case 3: test1 = 0x30|0x03; break; | |
499 | case 2: test1 = 0x40|0x04; break; | |
500 | case 1: test1 = 0x60|0x07; break; | |
d266ab88 | 501 | case 0: test1 = 0x00; break; |
1da177e4 LT |
502 | default: break; |
503 | } | |
504 | pci_write_config_byte(dev, drive_pci, test1); | |
505 | } else { /* ATA_133 */ | |
506 | u32 test3; | |
507 | pci_read_config_dword(dev, drive_pci, &test3); | |
508 | test3 &= 0xc0c00fff; | |
509 | if (test3 & 0x08) { | |
6b8cf772 BZ |
510 | test3 |= ini_time_value[ATA_133][pio] << 12; |
511 | test3 |= act_time_value[ATA_133][pio] << 16; | |
512 | test3 |= rco_time_value[ATA_133][pio] << 24; | |
1da177e4 | 513 | } else { |
6b8cf772 BZ |
514 | test3 |= ini_time_value[ATA_100][pio] << 12; |
515 | test3 |= act_time_value[ATA_100][pio] << 16; | |
516 | test3 |= rco_time_value[ATA_100][pio] << 24; | |
1da177e4 LT |
517 | } |
518 | pci_write_config_dword(dev, drive_pci, test3); | |
519 | } | |
520 | } | |
521 | ||
88b2b32b | 522 | static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
523 | { |
524 | ide_hwif_t *hwif = HWIF(drive); | |
525 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 | 526 | u32 regdw; |
f212ff28 | 527 | u8 drive_pci, reg; |
1da177e4 | 528 | |
88b2b32b | 529 | /* See sis_set_pio_mode() for drive PCI config registers */ |
1da177e4 LT |
530 | drive_pci = 0x40; |
531 | if (chipset_family >= ATA_133) { | |
532 | u32 reg54h; | |
533 | pci_read_config_dword(dev, 0x54, ®54h); | |
534 | if (reg54h & 0x40000000) drive_pci = 0x70; | |
535 | drive_pci += ((drive->dn)*0x4); | |
536 | pci_read_config_dword(dev, (unsigned long)drive_pci, ®dw); | |
537 | /* Disable UDMA bit for non UDMA modes on UDMA chips */ | |
538 | if (speed < XFER_UDMA_0) { | |
539 | regdw &= 0xfffffffb; | |
540 | pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); | |
541 | } | |
542 | ||
543 | } else { | |
544 | drive_pci += ((drive->dn)*0x2); | |
545 | pci_read_config_byte(dev, drive_pci+1, ®); | |
546 | /* Disable UDMA bit for non UDMA modes on UDMA chips */ | |
547 | if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) { | |
548 | reg &= 0x7F; | |
549 | pci_write_config_byte(dev, drive_pci+1, reg); | |
550 | } | |
551 | } | |
552 | ||
553 | /* Config chip for mode */ | |
554 | switch(speed) { | |
555 | case XFER_UDMA_6: | |
556 | case XFER_UDMA_5: | |
557 | case XFER_UDMA_4: | |
558 | case XFER_UDMA_3: | |
559 | case XFER_UDMA_2: | |
560 | case XFER_UDMA_1: | |
561 | case XFER_UDMA_0: | |
562 | if (chipset_family >= ATA_133) { | |
563 | regdw |= 0x04; | |
564 | regdw &= 0xfffff00f; | |
565 | /* check if ATA133 enable */ | |
566 | if (regdw & 0x08) { | |
567 | regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4; | |
568 | regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8; | |
569 | } else { | |
1da177e4 LT |
570 | regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4; |
571 | regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8; | |
572 | } | |
573 | pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); | |
574 | } else { | |
575 | /* Force the UDMA bit on if we want to use UDMA */ | |
576 | reg |= 0x80; | |
577 | /* clean reg cycle time bits */ | |
578 | reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family])) | |
579 | << cycle_time_offset[chipset_family]); | |
580 | /* set reg cycle time bits */ | |
581 | reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0] | |
582 | << cycle_time_offset[chipset_family]; | |
583 | pci_write_config_byte(dev, drive_pci+1, reg); | |
584 | } | |
585 | break; | |
586 | case XFER_MW_DMA_2: | |
587 | case XFER_MW_DMA_1: | |
588 | case XFER_MW_DMA_0: | |
589 | case XFER_SW_DMA_2: | |
590 | case XFER_SW_DMA_1: | |
591 | case XFER_SW_DMA_0: | |
592 | break; | |
6b8cf772 BZ |
593 | default: |
594 | BUG(); | |
595 | break; | |
1da177e4 | 596 | } |
1da177e4 LT |
597 | } |
598 | ||
ac4a3065 | 599 | static int sis5513_config_xfer_rate(ide_drive_t *drive) |
1da177e4 | 600 | { |
6b8cf772 BZ |
601 | /* |
602 | * TODO: always set PIO mode and remove this | |
603 | */ | |
26bcb879 | 604 | ide_set_max_pio(drive); |
ac4a3065 | 605 | |
1da177e4 LT |
606 | drive->init_speed = 0; |
607 | ||
29e744d0 | 608 | if (ide_tune_dma(drive)) |
3608b5d7 | 609 | return 0; |
1da177e4 | 610 | |
d8f4469d | 611 | if (ide_use_fast_pio(drive)) |
26bcb879 | 612 | ide_set_max_pio(drive); |
d8f4469d | 613 | |
3608b5d7 | 614 | return -1; |
1da177e4 LT |
615 | } |
616 | ||
3160d541 BZ |
617 | static u8 sis5513_ata133_udma_filter(ide_drive_t *drive) |
618 | { | |
619 | struct pci_dev *dev = drive->hwif->pci_dev; | |
620 | int drive_pci; | |
621 | u32 reg54 = 0, regdw = 0; | |
622 | ||
623 | pci_read_config_dword(dev, 0x54, ®54); | |
624 | drive_pci = ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4; | |
625 | pci_read_config_dword(dev, drive_pci, ®dw); | |
626 | ||
627 | /* if ATA133 disable, we should not set speed above UDMA5 */ | |
628 | return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5; | |
629 | } | |
630 | ||
1da177e4 | 631 | /* Chip detection and general config */ |
2b0c4bed | 632 | static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name) |
1da177e4 LT |
633 | { |
634 | struct pci_dev *host; | |
635 | int i = 0; | |
636 | ||
637 | chipset_family = 0; | |
638 | ||
639 | for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) { | |
640 | ||
40cddf2c | 641 | host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL); |
1da177e4 LT |
642 | |
643 | if (!host) | |
644 | continue; | |
645 | ||
646 | chipset_family = SiSHostChipInfo[i].chipset_family; | |
647 | ||
648 | /* Special case for SiS630 : 630S/ET is ATA_100a */ | |
649 | if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) { | |
44c10138 | 650 | if (host->revision >= 0x30) |
1da177e4 LT |
651 | chipset_family = ATA_100a; |
652 | } | |
40cddf2c | 653 | pci_dev_put(host); |
1da177e4 LT |
654 | |
655 | printk(KERN_INFO "SIS5513: %s %s controller\n", | |
656 | SiSHostChipInfo[i].name, chipset_capability[chipset_family]); | |
657 | } | |
658 | ||
659 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
660 | ||
661 | u32 idemisc; | |
662 | u16 trueid; | |
663 | ||
664 | /* Disable ID masking and register remapping */ | |
665 | pci_read_config_dword(dev, 0x54, &idemisc); | |
666 | pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff)); | |
667 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
668 | pci_write_config_dword(dev, 0x54, idemisc); | |
669 | ||
670 | if (trueid == 0x5518) { | |
671 | printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n"); | |
672 | chipset_family = ATA_133; | |
673 | ||
674 | /* Check for 5513 compability mapping | |
675 | * We must use this, else the port enabled code will fail, | |
676 | * as it expects the enablebits at 0x4a. | |
677 | */ | |
678 | if ((idemisc & 0x40000000) == 0) { | |
679 | pci_write_config_dword(dev, 0x54, idemisc | 0x40000000); | |
680 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
686 | ||
687 | struct pci_dev *lpc_bridge; | |
688 | u16 trueid; | |
689 | u8 prefctl; | |
690 | u8 idecfg; | |
1da177e4 LT |
691 | |
692 | pci_read_config_byte(dev, 0x4a, &idecfg); | |
693 | pci_write_config_byte(dev, 0x4a, idecfg | 0x10); | |
694 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
695 | pci_write_config_byte(dev, 0x4a, idecfg); | |
696 | ||
697 | if (trueid == 0x5517) { /* SiS 961/961B */ | |
698 | ||
b1489009 | 699 | lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */ |
1da177e4 | 700 | pci_read_config_byte(dev, 0x49, &prefctl); |
b1489009 | 701 | pci_dev_put(lpc_bridge); |
1da177e4 | 702 | |
44c10138 | 703 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
1da177e4 LT |
704 | printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n"); |
705 | chipset_family = ATA_133a; | |
706 | } else { | |
707 | printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n"); | |
708 | chipset_family = ATA_100; | |
709 | } | |
710 | } | |
711 | } | |
712 | ||
713 | if (!chipset_family) | |
714 | return -1; | |
715 | ||
716 | /* Make general config ops here | |
717 | 1/ tell IDE channels to operate in Compatibility mode only | |
718 | 2/ tell old chips to allow per drive IDE timings */ | |
719 | ||
720 | { | |
721 | u8 reg; | |
722 | u16 regw; | |
723 | ||
724 | switch(chipset_family) { | |
725 | case ATA_133: | |
726 | /* SiS962 operation mode */ | |
727 | pci_read_config_word(dev, 0x50, ®w); | |
728 | if (regw & 0x08) | |
729 | pci_write_config_word(dev, 0x50, regw&0xfff7); | |
730 | pci_read_config_word(dev, 0x52, ®w); | |
731 | if (regw & 0x08) | |
732 | pci_write_config_word(dev, 0x52, regw&0xfff7); | |
733 | break; | |
734 | case ATA_133a: | |
735 | case ATA_100: | |
736 | /* Fixup latency */ | |
737 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); | |
738 | /* Set compatibility bit */ | |
739 | pci_read_config_byte(dev, 0x49, ®); | |
740 | if (!(reg & 0x01)) { | |
741 | pci_write_config_byte(dev, 0x49, reg|0x01); | |
742 | } | |
743 | break; | |
744 | case ATA_100a: | |
745 | case ATA_66: | |
746 | /* Fixup latency */ | |
747 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10); | |
748 | ||
749 | /* On ATA_66 chips the bit was elsewhere */ | |
750 | pci_read_config_byte(dev, 0x52, ®); | |
751 | if (!(reg & 0x04)) { | |
752 | pci_write_config_byte(dev, 0x52, reg|0x04); | |
753 | } | |
754 | break; | |
755 | case ATA_33: | |
756 | /* On ATA_33 we didn't have a single bit to set */ | |
757 | pci_read_config_byte(dev, 0x09, ®); | |
758 | if ((reg & 0x0f) != 0x00) { | |
759 | pci_write_config_byte(dev, 0x09, reg&0xf0); | |
760 | } | |
761 | case ATA_16: | |
762 | /* force per drive recovery and active timings | |
763 | needed on ATA_33 and below chips */ | |
764 | pci_read_config_byte(dev, 0x52, ®); | |
765 | if (!(reg & 0x08)) { | |
766 | pci_write_config_byte(dev, 0x52, reg|0x08); | |
767 | } | |
768 | break; | |
769 | } | |
770 | ||
ecfd80e4 | 771 | #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
1da177e4 LT |
772 | if (!sis_proc) { |
773 | sis_proc = 1; | |
774 | bmide_dev = dev; | |
775 | ide_pci_create_host_proc("sis", sis_get_info); | |
776 | } | |
777 | #endif | |
778 | } | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
f2befd9e BZ |
783 | struct sis_laptop { |
784 | u16 device; | |
785 | u16 subvendor; | |
786 | u16 subdevice; | |
787 | }; | |
788 | ||
789 | static const struct sis_laptop sis_laptop[] = { | |
790 | /* devid, subvendor, subdev */ | |
791 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
1955f681 | 792 | { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */ |
f2befd9e BZ |
793 | /* end marker */ |
794 | { 0, } | |
795 | }; | |
796 | ||
49521f97 | 797 | static u8 __devinit ata66_sis5513(ide_hwif_t *hwif) |
1da177e4 | 798 | { |
f2befd9e BZ |
799 | struct pci_dev *pdev = hwif->pci_dev; |
800 | const struct sis_laptop *lap = &sis_laptop[0]; | |
1da177e4 LT |
801 | u8 ata66 = 0; |
802 | ||
f2befd9e BZ |
803 | while (lap->device) { |
804 | if (lap->device == pdev->device && | |
805 | lap->subvendor == pdev->subsystem_vendor && | |
806 | lap->subdevice == pdev->subsystem_device) | |
807 | return ATA_CBL_PATA40_SHORT; | |
808 | lap++; | |
809 | } | |
810 | ||
1da177e4 LT |
811 | if (chipset_family >= ATA_133) { |
812 | u16 regw = 0; | |
813 | u16 reg_addr = hwif->channel ? 0x52: 0x50; | |
814 | pci_read_config_word(hwif->pci_dev, reg_addr, ®w); | |
815 | ata66 = (regw & 0x8000) ? 0 : 1; | |
816 | } else if (chipset_family >= ATA_66) { | |
817 | u8 reg48h = 0; | |
818 | u8 mask = hwif->channel ? 0x20 : 0x10; | |
819 | pci_read_config_byte(hwif->pci_dev, 0x48, ®48h); | |
820 | ata66 = (reg48h & mask) ? 0 : 1; | |
821 | } | |
49521f97 BZ |
822 | |
823 | return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | |
1da177e4 LT |
824 | } |
825 | ||
2b0c4bed | 826 | static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif) |
1da177e4 | 827 | { |
18137207 BZ |
828 | u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; |
829 | ||
1da177e4 LT |
830 | hwif->autodma = 0; |
831 | ||
832 | if (!hwif->irq) | |
833 | hwif->irq = hwif->channel ? 15 : 14; | |
834 | ||
26bcb879 | 835 | hwif->set_pio_mode = &sis_set_pio_mode; |
88b2b32b | 836 | hwif->set_dma_mode = &sis_set_dma_mode; |
1da177e4 | 837 | |
3160d541 BZ |
838 | if (chipset_family >= ATA_133) |
839 | hwif->udma_filter = sis5513_ata133_udma_filter; | |
840 | ||
1da177e4 LT |
841 | if (!(hwif->dma_base)) { |
842 | hwif->drives[0].autotune = 1; | |
843 | hwif->drives[1].autotune = 1; | |
844 | return; | |
845 | } | |
846 | ||
847 | hwif->atapi_dma = 1; | |
18137207 BZ |
848 | |
849 | hwif->ultra_mask = udma_rates[chipset_family]; | |
1da177e4 LT |
850 | hwif->mwdma_mask = 0x07; |
851 | hwif->swdma_mask = 0x07; | |
852 | ||
853 | if (!chipset_family) | |
854 | return; | |
855 | ||
49521f97 BZ |
856 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
857 | hwif->cbl = ata66_sis5513(hwif); | |
1da177e4 LT |
858 | |
859 | if (chipset_family > ATA_16) { | |
860 | hwif->ide_dma_check = &sis5513_config_xfer_rate; | |
861 | if (!noautodma) | |
862 | hwif->autodma = 1; | |
863 | } | |
864 | hwif->drives[0].autodma = hwif->autodma; | |
865 | hwif->drives[1].autodma = hwif->autodma; | |
866 | return; | |
867 | } | |
868 | ||
869 | static ide_pci_device_t sis5513_chipset __devinitdata = { | |
870 | .name = "SIS5513", | |
871 | .init_chipset = init_chipset_sis5513, | |
872 | .init_hwif = init_hwif_sis5513, | |
1da177e4 LT |
873 | .autodma = NOAUTODMA, |
874 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
875 | .bootable = ON_BOARD, | |
4099d143 | 876 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
877 | }; |
878 | ||
879 | static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
880 | { | |
881 | return ide_setup_pci_device(dev, &sis5513_chipset); | |
882 | } | |
883 | ||
884 | static struct pci_device_id sis5513_pci_tbl[] = { | |
885 | { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
886 | { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
4c6c914e | 887 | { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 LT |
888 | { 0, }, |
889 | }; | |
890 | MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl); | |
891 | ||
892 | static struct pci_driver driver = { | |
893 | .name = "SIS_IDE", | |
894 | .id_table = sis5513_pci_tbl, | |
895 | .probe = sis5513_init_one, | |
896 | }; | |
897 | ||
82ab1eec | 898 | static int __init sis5513_ide_init(void) |
1da177e4 LT |
899 | { |
900 | return ide_pci_register_driver(&driver); | |
901 | } | |
902 | ||
903 | module_init(sis5513_ide_init); | |
904 | ||
905 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); | |
906 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); | |
907 | MODULE_LICENSE("GPL"); | |
908 | ||
909 | /* | |
910 | * TODO: | |
911 | * - CLEANUP | |
912 | * - Use drivers/ide/ide-timing.h ! | |
913 | * - More checks in the config registers (force values instead of | |
914 | * relying on the BIOS setting them correctly). | |
915 | * - Further optimisations ? | |
916 | * . for example ATA66+ regs 0x48 & 0x4A | |
917 | */ |