Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sl82c105.c | |
3 | * | |
4 | * SL82C105/Winbond 553 IDE driver | |
5 | * | |
6 | * Maintainer unknown. | |
7 | * | |
8 | * Drive tuning added from Rebel.com's kernel sources | |
9 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
10 | * | |
11 | * Merge in Russell's HW workarounds, fix various problems | |
12 | * with the timing registers setup. | |
13 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
14 | * |
15 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/blkdev.h> | |
26 | #include <linux/hdreg.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/ide.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/dma.h> | |
32 | ||
33 | #undef DEBUG | |
34 | ||
35 | #ifdef DEBUG | |
36 | #define DBG(arg) printk arg | |
37 | #else | |
38 | #define DBG(fmt,...) | |
39 | #endif | |
40 | /* | |
41 | * SL82C105 PCI config register 0x40 bits. | |
42 | */ | |
43 | #define CTRL_IDE_IRQB (1 << 30) | |
44 | #define CTRL_IDE_IRQA (1 << 28) | |
45 | #define CTRL_LEGIRQ (1 << 11) | |
46 | #define CTRL_P1F16 (1 << 5) | |
47 | #define CTRL_P1EN (1 << 4) | |
48 | #define CTRL_P0F16 (1 << 1) | |
49 | #define CTRL_P0EN (1 << 0) | |
50 | ||
51 | /* | |
e93df705 SS |
52 | * Convert a PIO mode and cycle time to the required on/off times |
53 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 54 | */ |
7dd00083 | 55 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 56 | { |
e93df705 | 57 | unsigned int cmd_on, cmd_off; |
2229833c | 58 | u8 iordy = 0; |
1da177e4 | 59 | |
7dd00083 BZ |
60 | cmd_on = (ide_pio_timings[pio].active_time + 29) / 30; |
61 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; | |
1da177e4 | 62 | |
1da177e4 LT |
63 | if (cmd_on == 0) |
64 | cmd_on = 1; | |
65 | ||
1da177e4 LT |
66 | if (cmd_off == 0) |
67 | cmd_off = 1; | |
68 | ||
7dd00083 | 69 | if (pio > 2 || ide_dev_has_iordy(drive->id)) |
2229833c BZ |
70 | iordy = 0x40; |
71 | ||
72 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
73 | } |
74 | ||
75 | /* | |
e93df705 | 76 | * Configure the chipset for PIO mode. |
1da177e4 | 77 | */ |
e93df705 | 78 | static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio) |
1da177e4 | 79 | { |
e93df705 SS |
80 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
81 | int reg = 0x44 + drive->dn * 4; | |
e93df705 | 82 | u16 drv_ctrl; |
1da177e4 | 83 | |
e93df705 | 84 | DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 | 85 | |
2134758d | 86 | pio = ide_get_best_pio_mode(drive, pio, 5); |
1da177e4 | 87 | |
7dd00083 | 88 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
89 | |
90 | /* | |
91 | * Store the PIO timings so that we can restore them | |
92 | * in case DMA will be turned off... | |
93 | */ | |
94 | drive->drive_data &= 0xffff0000; | |
95 | drive->drive_data |= drv_ctrl; | |
1da177e4 | 96 | |
e93df705 | 97 | if (!drive->using_dma) { |
1da177e4 LT |
98 | /* |
99 | * If we are actually using MW DMA, then we can not | |
100 | * reprogram the interface drive control register. | |
101 | */ | |
e93df705 SS |
102 | pci_write_config_word(dev, reg, drv_ctrl); |
103 | pci_read_config_word (dev, reg, &drv_ctrl); | |
1da177e4 | 104 | } |
e93df705 SS |
105 | |
106 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
107 | ide_xfer_verbose(pio + XFER_PIO_0), |
108 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
e93df705 SS |
109 | |
110 | return pio; | |
1da177e4 LT |
111 | } |
112 | ||
46cedc9b SS |
113 | /* |
114 | * Configure the drive and chipset for a new transfer speed. | |
115 | */ | |
116 | static int sl82c105_tune_chipset(ide_drive_t *drive, u8 speed) | |
117 | { | |
118 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
119 | u16 drv_ctrl; | |
120 | ||
121 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | |
122 | drive->name, ide_xfer_verbose(speed))); | |
123 | ||
124 | speed = ide_rate_filter(drive, speed); | |
125 | ||
126 | switch (speed) { | |
127 | case XFER_MW_DMA_2: | |
128 | case XFER_MW_DMA_1: | |
129 | case XFER_MW_DMA_0: | |
130 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; | |
131 | ||
132 | /* | |
133 | * Store the DMA timings so that we can actually program | |
134 | * them when DMA will be turned on... | |
135 | */ | |
136 | drive->drive_data &= 0x0000ffff; | |
137 | drive->drive_data |= (unsigned long)drv_ctrl << 16; | |
138 | ||
139 | /* | |
140 | * If we are already using DMA, we just reprogram | |
141 | * the drive control register. | |
142 | */ | |
143 | if (drive->using_dma) { | |
144 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
145 | int reg = 0x44 + drive->dn * 4; | |
146 | ||
147 | pci_write_config_word(dev, reg, drv_ctrl); | |
148 | } | |
149 | break; | |
150 | case XFER_PIO_5: | |
151 | case XFER_PIO_4: | |
152 | case XFER_PIO_3: | |
153 | case XFER_PIO_2: | |
154 | case XFER_PIO_1: | |
155 | case XFER_PIO_0: | |
156 | (void) sl82c105_tune_pio(drive, speed - XFER_PIO_0); | |
157 | break; | |
158 | default: | |
159 | return -1; | |
160 | } | |
161 | ||
162 | return ide_config_drive_speed(drive, speed); | |
163 | } | |
164 | ||
1da177e4 | 165 | /* |
688a87d1 | 166 | * Check to see if the drive and chipset are capable of DMA mode. |
1da177e4 | 167 | */ |
688a87d1 | 168 | static int sl82c105_ide_dma_check(ide_drive_t *drive) |
1da177e4 | 169 | { |
688a87d1 | 170 | DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name)); |
1da177e4 | 171 | |
4728d546 | 172 | if (ide_tune_dma(drive)) |
688a87d1 | 173 | return 0; |
1da177e4 | 174 | |
3608b5d7 | 175 | return -1; |
1da177e4 LT |
176 | } |
177 | ||
178 | /* | |
179 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
180 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
181 | * when the drive wants to report an error condition). | |
182 | * | |
183 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
184 | * state machine. We need to kick this to work around various bugs. | |
185 | */ | |
186 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
187 | { | |
188 | u16 val; | |
189 | ||
190 | pci_read_config_word(dev, 0x7e, &val); | |
191 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
192 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
193 | } | |
194 | ||
195 | /* | |
196 | * If we get an IRQ timeout, it might be that the DMA state machine | |
197 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
198 | * | |
199 | * This function is called when the IDE timer expires, the drive | |
200 | * indicates that it is READY, and we were waiting for DMA to complete. | |
201 | */ | |
841d2a9b | 202 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 203 | { |
688a87d1 SS |
204 | ide_hwif_t *hwif = HWIF(drive); |
205 | struct pci_dev *dev = hwif->pci_dev; | |
206 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
207 | u8 dma_cmd; | |
1da177e4 | 208 | |
688a87d1 | 209 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
210 | |
211 | /* | |
212 | * Check the raw interrupt from the drive. | |
213 | */ | |
214 | pci_read_config_dword(dev, 0x40, &val); | |
215 | if (val & mask) | |
216 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
217 | ||
218 | /* | |
219 | * Was DMA enabled? If so, disable it - we're resetting the | |
220 | * host. The IDE layer will be handling the drive for us. | |
221 | */ | |
688a87d1 SS |
222 | dma_cmd = inb(hwif->dma_command); |
223 | if (dma_cmd & 1) { | |
224 | outb(dma_cmd & ~1, hwif->dma_command); | |
1da177e4 LT |
225 | printk("sl82c105: DMA was enabled\n"); |
226 | } | |
227 | ||
228 | sl82c105_reset_host(dev); | |
1da177e4 LT |
229 | } |
230 | ||
231 | /* | |
232 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
233 | * Winbond recommend that the DMA state machine is reset prior to | |
234 | * setting the bus master DMA enable bit. | |
235 | * | |
236 | * The generic IDE core will have disabled the BMEN bit before this | |
237 | * function is called. | |
238 | */ | |
688a87d1 | 239 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 240 | { |
688a87d1 SS |
241 | ide_hwif_t *hwif = HWIF(drive); |
242 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
243 | |
244 | sl82c105_reset_host(dev); | |
245 | ide_dma_start(drive); | |
246 | } | |
247 | ||
c283f5db | 248 | static void sl82c105_dma_timeout(ide_drive_t *drive) |
1da177e4 | 249 | { |
c283f5db | 250 | DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name)); |
1da177e4 | 251 | |
c283f5db SS |
252 | sl82c105_reset_host(HWIF(drive)->pci_dev); |
253 | ide_dma_timeout(drive); | |
1da177e4 LT |
254 | } |
255 | ||
688a87d1 | 256 | static int sl82c105_ide_dma_on(ide_drive_t *drive) |
1da177e4 | 257 | { |
688a87d1 SS |
258 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
259 | int rc, reg = 0x44 + drive->dn * 4; | |
260 | ||
1da177e4 LT |
261 | DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name)); |
262 | ||
688a87d1 SS |
263 | rc = __ide_dma_on(drive); |
264 | if (rc == 0) { | |
46cedc9b | 265 | pci_write_config_word(dev, reg, drive->drive_data >> 16); |
688a87d1 SS |
266 | |
267 | printk(KERN_INFO "%s: DMA enabled\n", drive->name); | |
268 | } | |
269 | return rc; | |
1da177e4 LT |
270 | } |
271 | ||
7469aaf6 | 272 | static void sl82c105_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 273 | { |
e93df705 SS |
274 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
275 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 276 | |
7469aaf6 BZ |
277 | DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name)); |
278 | ||
e93df705 SS |
279 | pci_write_config_word(dev, reg, drive->drive_data); |
280 | ||
7469aaf6 | 281 | ide_dma_off_quietly(drive); |
1da177e4 LT |
282 | } |
283 | ||
284 | /* | |
285 | * Ok, that is nasty, but we must make sure the DMA timings | |
286 | * won't be used for a PIO access. The solution here is | |
287 | * to make sure the 16 bits mode is diabled on the channel | |
288 | * when DMA is enabled, thus causing the chip to use PIO0 | |
289 | * timings for those operations. | |
290 | */ | |
291 | static void sl82c105_selectproc(ide_drive_t *drive) | |
292 | { | |
688a87d1 SS |
293 | ide_hwif_t *hwif = HWIF(drive); |
294 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
295 | u32 val, old, mask; |
296 | ||
297 | //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); | |
298 | ||
299 | mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16; | |
dd607d23 | 300 | old = val = (u32)pci_get_drvdata(dev); |
1da177e4 LT |
301 | if (drive->using_dma) |
302 | val &= ~mask; | |
303 | else | |
304 | val |= mask; | |
305 | if (old != val) { | |
306 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 307 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
308 | } |
309 | } | |
310 | ||
311 | /* | |
312 | * ATA reset will clear the 16 bits mode in the control | |
313 | * register, we need to update our cache | |
314 | */ | |
315 | static void sl82c105_resetproc(ide_drive_t *drive) | |
316 | { | |
dd607d23 | 317 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
1da177e4 LT |
318 | u32 val; |
319 | ||
320 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
321 | ||
322 | pci_read_config_dword(dev, 0x40, &val); | |
dd607d23 | 323 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
324 | } |
325 | ||
326 | /* | |
327 | * We only deal with PIO mode here - DMA mode 'using_dma' is not | |
328 | * initialised at the point that this function is called. | |
329 | */ | |
e93df705 | 330 | static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio) |
1da177e4 | 331 | { |
e93df705 | 332 | DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 | 333 | |
e93df705 SS |
334 | pio = sl82c105_tune_pio(drive, pio); |
335 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
336 | } |
337 | ||
338 | /* | |
339 | * Return the revision of the Winbond bridge | |
340 | * which this function is part of. | |
341 | */ | |
342 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
343 | { | |
344 | struct pci_dev *bridge; | |
1da177e4 LT |
345 | |
346 | /* | |
347 | * The bridge should be part of the same device, but function 0. | |
348 | */ | |
640b31bf | 349 | bridge = pci_get_bus_and_slot(dev->bus->number, |
1da177e4 LT |
350 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
351 | if (!bridge) | |
352 | return -1; | |
353 | ||
354 | /* | |
355 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
356 | */ | |
357 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
358 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
359 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
360 | pci_dev_put(bridge); | |
1da177e4 | 361 | return -1; |
640b31bf | 362 | } |
1da177e4 LT |
363 | /* |
364 | * We need to find function 0's revision, not function 1 | |
365 | */ | |
640b31bf | 366 | pci_dev_put(bridge); |
1da177e4 | 367 | |
44c10138 | 368 | return bridge->revision; |
1da177e4 LT |
369 | } |
370 | ||
371 | /* | |
372 | * Enable the PCI device | |
373 | * | |
374 | * --BenH: It's arch fixup code that should enable channels that | |
375 | * have not been enabled by firmware. I decided we can still enable | |
376 | * channel 0 here at least, but channel 1 has to be enabled by | |
377 | * firmware or arch code. We still set both to 16 bits mode. | |
378 | */ | |
34a62246 | 379 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
380 | { |
381 | u32 val; | |
382 | ||
383 | DBG(("init_chipset_sl82c105()\n")); | |
384 | ||
385 | pci_read_config_dword(dev, 0x40, &val); | |
386 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
387 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 388 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
389 | |
390 | return dev->irq; | |
391 | } | |
392 | ||
1da177e4 | 393 | /* |
688a87d1 | 394 | * Initialise IDE channel |
1da177e4 | 395 | */ |
34a62246 | 396 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 397 | { |
9648f552 | 398 | unsigned int rev; |
dd607d23 | 399 | |
1da177e4 LT |
400 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
401 | ||
e93df705 | 402 | hwif->tuneproc = &sl82c105_tune_drive; |
46cedc9b | 403 | hwif->speedproc = &sl82c105_tune_chipset; |
e93df705 SS |
404 | hwif->selectproc = &sl82c105_selectproc; |
405 | hwif->resetproc = &sl82c105_resetproc; | |
406 | ||
407 | /* | |
408 | * We support 32-bit I/O on this interface, and | |
409 | * it doesn't have problems with interrupts. | |
410 | */ | |
411 | hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1; | |
412 | hwif->drives[0].unmask = hwif->drives[1].unmask = 1; | |
dd607d23 SS |
413 | |
414 | /* | |
dd607d23 SS |
415 | * We always autotune PIO, this is done before DMA is checked, |
416 | * so there's no risk of accidentally disabling DMA | |
417 | */ | |
e93df705 | 418 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1da177e4 | 419 | |
1da177e4 LT |
420 | if (!hwif->dma_base) |
421 | return; | |
422 | ||
9648f552 RK |
423 | rev = sl82c105_bridge_revision(hwif->pci_dev); |
424 | if (rev <= 5) { | |
425 | /* | |
426 | * Never ever EVER under any circumstances enable | |
427 | * DMA when the bridge is this old. | |
428 | */ | |
688a87d1 SS |
429 | printk(" %s: Winbond W83C553 bridge revision %d, " |
430 | "BM-DMA disabled\n", hwif->name, rev); | |
431 | return; | |
9648f552 | 432 | } |
688a87d1 SS |
433 | |
434 | hwif->atapi_dma = 1; | |
46cedc9b | 435 | hwif->mwdma_mask = 0x07; |
688a87d1 SS |
436 | |
437 | hwif->ide_dma_check = &sl82c105_ide_dma_check; | |
438 | hwif->ide_dma_on = &sl82c105_ide_dma_on; | |
439 | hwif->dma_off_quietly = &sl82c105_dma_off_quietly; | |
841d2a9b | 440 | hwif->dma_lost_irq = &sl82c105_dma_lost_irq; |
688a87d1 | 441 | hwif->dma_start = &sl82c105_dma_start; |
c283f5db | 442 | hwif->dma_timeout = &sl82c105_dma_timeout; |
688a87d1 SS |
443 | |
444 | if (!noautodma) | |
445 | hwif->autodma = 1; | |
446 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; | |
447 | ||
448 | if (hwif->mate) | |
449 | hwif->serialized = hwif->mate->serialized = 1; | |
1da177e4 LT |
450 | } |
451 | ||
452 | static ide_pci_device_t sl82c105_chipset __devinitdata = { | |
453 | .name = "W82C105", | |
454 | .init_chipset = init_chipset_sl82c105, | |
455 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 LT |
456 | .autodma = NOAUTODMA, |
457 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, | |
458 | .bootable = ON_BOARD, | |
459 | }; | |
460 | ||
461 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
462 | { | |
463 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
464 | } | |
465 | ||
466 | static struct pci_device_id sl82c105_pci_tbl[] = { | |
f201f504 | 467 | { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0}, |
1da177e4 LT |
468 | { 0, }, |
469 | }; | |
470 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
471 | ||
472 | static struct pci_driver driver = { | |
473 | .name = "W82C105_IDE", | |
474 | .id_table = sl82c105_pci_tbl, | |
475 | .probe = sl82c105_init_one, | |
476 | }; | |
477 | ||
82ab1eec | 478 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
479 | { |
480 | return ide_pci_register_driver(&driver); | |
481 | } | |
482 | ||
483 | module_init(sl82c105_ide_init); | |
484 | ||
485 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
486 | MODULE_LICENSE("GPL"); |