Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sl82c105.c | |
3 | * | |
4 | * SL82C105/Winbond 553 IDE driver | |
5 | * | |
6 | * Maintainer unknown. | |
7 | * | |
8 | * Drive tuning added from Rebel.com's kernel sources | |
9 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
10 | * | |
11 | * Merge in Russell's HW workarounds, fix various problems | |
12 | * with the timing registers setup. | |
13 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
14 | * |
15 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
6ae8b1ef | 16 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
17 | */ |
18 | ||
1da177e4 LT |
19 | #include <linux/types.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/blkdev.h> | |
27 | #include <linux/hdreg.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/ide.h> | |
30 | ||
31 | #include <asm/io.h> | |
32 | #include <asm/dma.h> | |
33 | ||
34 | #undef DEBUG | |
35 | ||
36 | #ifdef DEBUG | |
37 | #define DBG(arg) printk arg | |
38 | #else | |
39 | #define DBG(fmt,...) | |
40 | #endif | |
41 | /* | |
42 | * SL82C105 PCI config register 0x40 bits. | |
43 | */ | |
44 | #define CTRL_IDE_IRQB (1 << 30) | |
45 | #define CTRL_IDE_IRQA (1 << 28) | |
46 | #define CTRL_LEGIRQ (1 << 11) | |
47 | #define CTRL_P1F16 (1 << 5) | |
48 | #define CTRL_P1EN (1 << 4) | |
49 | #define CTRL_P0F16 (1 << 1) | |
50 | #define CTRL_P0EN (1 << 0) | |
51 | ||
52 | /* | |
e93df705 SS |
53 | * Convert a PIO mode and cycle time to the required on/off times |
54 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 55 | */ |
7dd00083 | 56 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 57 | { |
e93df705 | 58 | unsigned int cmd_on, cmd_off; |
2229833c | 59 | u8 iordy = 0; |
1da177e4 | 60 | |
7dd00083 BZ |
61 | cmd_on = (ide_pio_timings[pio].active_time + 29) / 30; |
62 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; | |
1da177e4 | 63 | |
1da177e4 LT |
64 | if (cmd_on == 0) |
65 | cmd_on = 1; | |
66 | ||
1da177e4 LT |
67 | if (cmd_off == 0) |
68 | cmd_off = 1; | |
69 | ||
7dd00083 | 70 | if (pio > 2 || ide_dev_has_iordy(drive->id)) |
2229833c BZ |
71 | iordy = 0x40; |
72 | ||
73 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
74 | } |
75 | ||
76 | /* | |
e93df705 | 77 | * Configure the chipset for PIO mode. |
1da177e4 | 78 | */ |
88b2b32b | 79 | static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 80 | { |
e93df705 SS |
81 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
82 | int reg = 0x44 + drive->dn * 4; | |
e93df705 | 83 | u16 drv_ctrl; |
1da177e4 | 84 | |
7dd00083 | 85 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
86 | |
87 | /* | |
88 | * Store the PIO timings so that we can restore them | |
89 | * in case DMA will be turned off... | |
90 | */ | |
91 | drive->drive_data &= 0xffff0000; | |
92 | drive->drive_data |= drv_ctrl; | |
1da177e4 | 93 | |
6ae8b1ef BZ |
94 | pci_write_config_word(dev, reg, drv_ctrl); |
95 | pci_read_config_word (dev, reg, &drv_ctrl); | |
e93df705 SS |
96 | |
97 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
98 | ide_xfer_verbose(pio + XFER_PIO_0), |
99 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
1da177e4 LT |
100 | } |
101 | ||
46cedc9b | 102 | /* |
88b2b32b | 103 | * Configure the chipset for DMA mode. |
46cedc9b | 104 | */ |
88b2b32b | 105 | static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) |
46cedc9b SS |
106 | { |
107 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
108 | u16 drv_ctrl; | |
109 | ||
110 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | |
111 | drive->name, ide_xfer_verbose(speed))); | |
112 | ||
4db90a14 | 113 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
46cedc9b | 114 | |
4db90a14 BZ |
115 | /* |
116 | * Store the DMA timings so that we can actually program | |
117 | * them when DMA will be turned on... | |
118 | */ | |
119 | drive->drive_data &= 0x0000ffff; | |
120 | drive->drive_data |= (unsigned long)drv_ctrl << 16; | |
46cedc9b SS |
121 | } |
122 | ||
1da177e4 LT |
123 | /* |
124 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
125 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
126 | * when the drive wants to report an error condition). | |
127 | * | |
128 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
129 | * state machine. We need to kick this to work around various bugs. | |
130 | */ | |
131 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
132 | { | |
133 | u16 val; | |
134 | ||
135 | pci_read_config_word(dev, 0x7e, &val); | |
136 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
137 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
138 | } | |
139 | ||
140 | /* | |
141 | * If we get an IRQ timeout, it might be that the DMA state machine | |
142 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
143 | * | |
144 | * This function is called when the IDE timer expires, the drive | |
145 | * indicates that it is READY, and we were waiting for DMA to complete. | |
146 | */ | |
841d2a9b | 147 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 148 | { |
688a87d1 SS |
149 | ide_hwif_t *hwif = HWIF(drive); |
150 | struct pci_dev *dev = hwif->pci_dev; | |
151 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
152 | u8 dma_cmd; | |
1da177e4 | 153 | |
688a87d1 | 154 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
155 | |
156 | /* | |
157 | * Check the raw interrupt from the drive. | |
158 | */ | |
159 | pci_read_config_dword(dev, 0x40, &val); | |
160 | if (val & mask) | |
161 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
162 | ||
163 | /* | |
164 | * Was DMA enabled? If so, disable it - we're resetting the | |
165 | * host. The IDE layer will be handling the drive for us. | |
166 | */ | |
688a87d1 SS |
167 | dma_cmd = inb(hwif->dma_command); |
168 | if (dma_cmd & 1) { | |
169 | outb(dma_cmd & ~1, hwif->dma_command); | |
1da177e4 LT |
170 | printk("sl82c105: DMA was enabled\n"); |
171 | } | |
172 | ||
173 | sl82c105_reset_host(dev); | |
1da177e4 LT |
174 | } |
175 | ||
176 | /* | |
177 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
178 | * Winbond recommend that the DMA state machine is reset prior to | |
179 | * setting the bus master DMA enable bit. | |
180 | * | |
181 | * The generic IDE core will have disabled the BMEN bit before this | |
182 | * function is called. | |
183 | */ | |
688a87d1 | 184 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 185 | { |
688a87d1 SS |
186 | ide_hwif_t *hwif = HWIF(drive); |
187 | struct pci_dev *dev = hwif->pci_dev; | |
6ae8b1ef BZ |
188 | int reg = 0x44 + drive->dn * 4; |
189 | ||
190 | DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name)); | |
191 | ||
192 | pci_write_config_word(dev, reg, drive->drive_data >> 16); | |
1da177e4 LT |
193 | |
194 | sl82c105_reset_host(dev); | |
195 | ide_dma_start(drive); | |
196 | } | |
197 | ||
c283f5db | 198 | static void sl82c105_dma_timeout(ide_drive_t *drive) |
1da177e4 | 199 | { |
c283f5db | 200 | DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name)); |
1da177e4 | 201 | |
c283f5db SS |
202 | sl82c105_reset_host(HWIF(drive)->pci_dev); |
203 | ide_dma_timeout(drive); | |
1da177e4 LT |
204 | } |
205 | ||
6ae8b1ef | 206 | static int sl82c105_dma_end(ide_drive_t *drive) |
1da177e4 | 207 | { |
e93df705 SS |
208 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
209 | int reg = 0x44 + drive->dn * 4; | |
6ae8b1ef BZ |
210 | int ret; |
211 | ||
212 | DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name)); | |
1da177e4 | 213 | |
6ae8b1ef | 214 | ret = __ide_dma_end(drive); |
7469aaf6 | 215 | |
e93df705 SS |
216 | pci_write_config_word(dev, reg, drive->drive_data); |
217 | ||
6ae8b1ef | 218 | return ret; |
1da177e4 LT |
219 | } |
220 | ||
221 | /* | |
222 | * Ok, that is nasty, but we must make sure the DMA timings | |
223 | * won't be used for a PIO access. The solution here is | |
224 | * to make sure the 16 bits mode is diabled on the channel | |
225 | * when DMA is enabled, thus causing the chip to use PIO0 | |
226 | * timings for those operations. | |
227 | */ | |
228 | static void sl82c105_selectproc(ide_drive_t *drive) | |
229 | { | |
688a87d1 SS |
230 | ide_hwif_t *hwif = HWIF(drive); |
231 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
232 | u32 val, old, mask; |
233 | ||
234 | //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); | |
235 | ||
236 | mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16; | |
dd607d23 | 237 | old = val = (u32)pci_get_drvdata(dev); |
1da177e4 LT |
238 | if (drive->using_dma) |
239 | val &= ~mask; | |
240 | else | |
241 | val |= mask; | |
242 | if (old != val) { | |
243 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 244 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
245 | } |
246 | } | |
247 | ||
248 | /* | |
249 | * ATA reset will clear the 16 bits mode in the control | |
250 | * register, we need to update our cache | |
251 | */ | |
252 | static void sl82c105_resetproc(ide_drive_t *drive) | |
253 | { | |
dd607d23 | 254 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
1da177e4 LT |
255 | u32 val; |
256 | ||
257 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
258 | ||
259 | pci_read_config_dword(dev, 0x40, &val); | |
dd607d23 | 260 | pci_set_drvdata(dev, (void *)val); |
1da177e4 | 261 | } |
1da177e4 LT |
262 | |
263 | /* | |
264 | * Return the revision of the Winbond bridge | |
265 | * which this function is part of. | |
266 | */ | |
267 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
268 | { | |
269 | struct pci_dev *bridge; | |
1da177e4 LT |
270 | |
271 | /* | |
272 | * The bridge should be part of the same device, but function 0. | |
273 | */ | |
640b31bf | 274 | bridge = pci_get_bus_and_slot(dev->bus->number, |
1da177e4 LT |
275 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
276 | if (!bridge) | |
277 | return -1; | |
278 | ||
279 | /* | |
280 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
281 | */ | |
282 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
283 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
284 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
285 | pci_dev_put(bridge); | |
1da177e4 | 286 | return -1; |
640b31bf | 287 | } |
1da177e4 LT |
288 | /* |
289 | * We need to find function 0's revision, not function 1 | |
290 | */ | |
640b31bf | 291 | pci_dev_put(bridge); |
1da177e4 | 292 | |
44c10138 | 293 | return bridge->revision; |
1da177e4 LT |
294 | } |
295 | ||
296 | /* | |
297 | * Enable the PCI device | |
298 | * | |
299 | * --BenH: It's arch fixup code that should enable channels that | |
300 | * have not been enabled by firmware. I decided we can still enable | |
301 | * channel 0 here at least, but channel 1 has to be enabled by | |
302 | * firmware or arch code. We still set both to 16 bits mode. | |
303 | */ | |
34a62246 | 304 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
305 | { |
306 | u32 val; | |
307 | ||
308 | DBG(("init_chipset_sl82c105()\n")); | |
309 | ||
310 | pci_read_config_dword(dev, 0x40, &val); | |
311 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
312 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 313 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
314 | |
315 | return dev->irq; | |
316 | } | |
317 | ||
1da177e4 | 318 | /* |
688a87d1 | 319 | * Initialise IDE channel |
1da177e4 | 320 | */ |
34a62246 | 321 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 322 | { |
9648f552 | 323 | unsigned int rev; |
dd607d23 | 324 | |
1da177e4 LT |
325 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
326 | ||
26bcb879 | 327 | hwif->set_pio_mode = &sl82c105_set_pio_mode; |
88b2b32b | 328 | hwif->set_dma_mode = &sl82c105_set_dma_mode; |
e93df705 SS |
329 | hwif->selectproc = &sl82c105_selectproc; |
330 | hwif->resetproc = &sl82c105_resetproc; | |
331 | ||
1da177e4 LT |
332 | if (!hwif->dma_base) |
333 | return; | |
334 | ||
9648f552 RK |
335 | rev = sl82c105_bridge_revision(hwif->pci_dev); |
336 | if (rev <= 5) { | |
337 | /* | |
338 | * Never ever EVER under any circumstances enable | |
339 | * DMA when the bridge is this old. | |
340 | */ | |
688a87d1 SS |
341 | printk(" %s: Winbond W83C553 bridge revision %d, " |
342 | "BM-DMA disabled\n", hwif->name, rev); | |
343 | return; | |
9648f552 | 344 | } |
688a87d1 | 345 | |
5f8b6c34 | 346 | hwif->mwdma_mask = ATA_MWDMA2; |
688a87d1 | 347 | |
841d2a9b | 348 | hwif->dma_lost_irq = &sl82c105_dma_lost_irq; |
688a87d1 | 349 | hwif->dma_start = &sl82c105_dma_start; |
6ae8b1ef | 350 | hwif->ide_dma_end = &sl82c105_dma_end; |
c283f5db | 351 | hwif->dma_timeout = &sl82c105_dma_timeout; |
688a87d1 | 352 | |
688a87d1 SS |
353 | if (hwif->mate) |
354 | hwif->serialized = hwif->mate->serialized = 1; | |
1da177e4 LT |
355 | } |
356 | ||
85620436 | 357 | static const struct ide_port_info sl82c105_chipset __devinitdata = { |
1da177e4 LT |
358 | .name = "W82C105", |
359 | .init_chipset = init_chipset_sl82c105, | |
360 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 | 361 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, |
caea7602 BZ |
362 | .host_flags = IDE_HFLAG_IO_32BIT | |
363 | IDE_HFLAG_UNMASK_IRQS | | |
364 | IDE_HFLAG_NO_AUTODMA | | |
365 | IDE_HFLAG_BOOTABLE, | |
4099d143 | 366 | .pio_mask = ATA_PIO5, |
1da177e4 LT |
367 | }; |
368 | ||
369 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
370 | { | |
371 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
372 | } | |
373 | ||
9cbcc5e3 BZ |
374 | static const struct pci_device_id sl82c105_pci_tbl[] = { |
375 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, | |
1da177e4 LT |
376 | { 0, }, |
377 | }; | |
378 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
379 | ||
380 | static struct pci_driver driver = { | |
381 | .name = "W82C105_IDE", | |
382 | .id_table = sl82c105_pci_tbl, | |
383 | .probe = sl82c105_init_one, | |
384 | }; | |
385 | ||
82ab1eec | 386 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
387 | { |
388 | return ide_pci_register_driver(&driver); | |
389 | } | |
390 | ||
391 | module_init(sl82c105_ide_init); | |
392 | ||
393 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
394 | MODULE_LICENSE("GPL"); |