Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SL82C105/Winbond 553 IDE driver |
3 | * | |
4 | * Maintainer unknown. | |
5 | * | |
6 | * Drive tuning added from Rebel.com's kernel sources | |
7 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
8 | * | |
9 | * Merge in Russell's HW workarounds, fix various problems | |
10 | * with the timing registers setup. | |
11 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
12 | * |
13 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
6ae8b1ef | 14 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
15 | */ |
16 | ||
1da177e4 LT |
17 | #include <linux/types.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
1da177e4 LT |
20 | #include <linux/hdreg.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/ide.h> | |
23 | ||
24 | #include <asm/io.h> | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
28 | #ifdef DEBUG | |
29 | #define DBG(arg) printk arg | |
30 | #else | |
31 | #define DBG(fmt,...) | |
32 | #endif | |
33 | /* | |
34 | * SL82C105 PCI config register 0x40 bits. | |
35 | */ | |
36 | #define CTRL_IDE_IRQB (1 << 30) | |
37 | #define CTRL_IDE_IRQA (1 << 28) | |
38 | #define CTRL_LEGIRQ (1 << 11) | |
39 | #define CTRL_P1F16 (1 << 5) | |
40 | #define CTRL_P1EN (1 << 4) | |
41 | #define CTRL_P0F16 (1 << 1) | |
42 | #define CTRL_P0EN (1 << 0) | |
43 | ||
44 | /* | |
e93df705 SS |
45 | * Convert a PIO mode and cycle time to the required on/off times |
46 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 47 | */ |
7dd00083 | 48 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 49 | { |
3f847571 | 50 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
e93df705 | 51 | unsigned int cmd_on, cmd_off; |
2229833c | 52 | u8 iordy = 0; |
1da177e4 | 53 | |
3f847571 | 54 | cmd_on = (t->active + 29) / 30; |
7dd00083 | 55 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; |
1da177e4 | 56 | |
1da177e4 LT |
57 | if (cmd_on == 0) |
58 | cmd_on = 1; | |
59 | ||
1da177e4 LT |
60 | if (cmd_off == 0) |
61 | cmd_off = 1; | |
62 | ||
7dd00083 | 63 | if (pio > 2 || ide_dev_has_iordy(drive->id)) |
2229833c BZ |
64 | iordy = 0x40; |
65 | ||
66 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
67 | } |
68 | ||
69 | /* | |
e93df705 | 70 | * Configure the chipset for PIO mode. |
1da177e4 | 71 | */ |
88b2b32b | 72 | static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 73 | { |
36501650 | 74 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
e93df705 | 75 | int reg = 0x44 + drive->dn * 4; |
e93df705 | 76 | u16 drv_ctrl; |
1da177e4 | 77 | |
7dd00083 | 78 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
79 | |
80 | /* | |
81 | * Store the PIO timings so that we can restore them | |
82 | * in case DMA will be turned off... | |
83 | */ | |
84 | drive->drive_data &= 0xffff0000; | |
85 | drive->drive_data |= drv_ctrl; | |
1da177e4 | 86 | |
6ae8b1ef BZ |
87 | pci_write_config_word(dev, reg, drv_ctrl); |
88 | pci_read_config_word (dev, reg, &drv_ctrl); | |
e93df705 SS |
89 | |
90 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
91 | ide_xfer_verbose(pio + XFER_PIO_0), |
92 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
1da177e4 LT |
93 | } |
94 | ||
46cedc9b | 95 | /* |
88b2b32b | 96 | * Configure the chipset for DMA mode. |
46cedc9b | 97 | */ |
88b2b32b | 98 | static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) |
46cedc9b SS |
99 | { |
100 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
101 | u16 drv_ctrl; | |
102 | ||
103 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | |
104 | drive->name, ide_xfer_verbose(speed))); | |
105 | ||
4db90a14 | 106 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
46cedc9b | 107 | |
4db90a14 BZ |
108 | /* |
109 | * Store the DMA timings so that we can actually program | |
110 | * them when DMA will be turned on... | |
111 | */ | |
112 | drive->drive_data &= 0x0000ffff; | |
113 | drive->drive_data |= (unsigned long)drv_ctrl << 16; | |
46cedc9b SS |
114 | } |
115 | ||
1da177e4 LT |
116 | /* |
117 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
118 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
119 | * when the drive wants to report an error condition). | |
120 | * | |
121 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
122 | * state machine. We need to kick this to work around various bugs. | |
123 | */ | |
124 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
125 | { | |
126 | u16 val; | |
127 | ||
128 | pci_read_config_word(dev, 0x7e, &val); | |
129 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
130 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
131 | } | |
132 | ||
133 | /* | |
134 | * If we get an IRQ timeout, it might be that the DMA state machine | |
135 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
136 | * | |
137 | * This function is called when the IDE timer expires, the drive | |
138 | * indicates that it is READY, and we were waiting for DMA to complete. | |
139 | */ | |
841d2a9b | 140 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 141 | { |
688a87d1 | 142 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 143 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
688a87d1 SS |
144 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; |
145 | u8 dma_cmd; | |
1da177e4 | 146 | |
688a87d1 | 147 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
148 | |
149 | /* | |
150 | * Check the raw interrupt from the drive. | |
151 | */ | |
152 | pci_read_config_dword(dev, 0x40, &val); | |
153 | if (val & mask) | |
154 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
155 | ||
156 | /* | |
157 | * Was DMA enabled? If so, disable it - we're resetting the | |
158 | * host. The IDE layer will be handling the drive for us. | |
159 | */ | |
cab7f8ed | 160 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
688a87d1 | 161 | if (dma_cmd & 1) { |
cab7f8ed | 162 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 LT |
163 | printk("sl82c105: DMA was enabled\n"); |
164 | } | |
165 | ||
166 | sl82c105_reset_host(dev); | |
1da177e4 LT |
167 | } |
168 | ||
169 | /* | |
170 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
171 | * Winbond recommend that the DMA state machine is reset prior to | |
172 | * setting the bus master DMA enable bit. | |
173 | * | |
174 | * The generic IDE core will have disabled the BMEN bit before this | |
175 | * function is called. | |
176 | */ | |
688a87d1 | 177 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 178 | { |
688a87d1 | 179 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 180 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
6ae8b1ef BZ |
181 | int reg = 0x44 + drive->dn * 4; |
182 | ||
eb63963a | 183 | DBG(("%s(drive:%s)\n", __func__, drive->name)); |
6ae8b1ef BZ |
184 | |
185 | pci_write_config_word(dev, reg, drive->drive_data >> 16); | |
1da177e4 LT |
186 | |
187 | sl82c105_reset_host(dev); | |
188 | ide_dma_start(drive); | |
189 | } | |
190 | ||
c283f5db | 191 | static void sl82c105_dma_timeout(ide_drive_t *drive) |
1da177e4 | 192 | { |
36501650 BZ |
193 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
194 | ||
c283f5db | 195 | DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name)); |
1da177e4 | 196 | |
36501650 | 197 | sl82c105_reset_host(dev); |
c283f5db | 198 | ide_dma_timeout(drive); |
1da177e4 LT |
199 | } |
200 | ||
6ae8b1ef | 201 | static int sl82c105_dma_end(ide_drive_t *drive) |
1da177e4 | 202 | { |
36501650 | 203 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
e93df705 | 204 | int reg = 0x44 + drive->dn * 4; |
6ae8b1ef BZ |
205 | int ret; |
206 | ||
eb63963a | 207 | DBG(("%s(drive:%s)\n", __func__, drive->name)); |
1da177e4 | 208 | |
6ae8b1ef | 209 | ret = __ide_dma_end(drive); |
7469aaf6 | 210 | |
e93df705 SS |
211 | pci_write_config_word(dev, reg, drive->drive_data); |
212 | ||
6ae8b1ef | 213 | return ret; |
1da177e4 LT |
214 | } |
215 | ||
1da177e4 LT |
216 | /* |
217 | * ATA reset will clear the 16 bits mode in the control | |
08590556 | 218 | * register, we need to reprogram it |
1da177e4 LT |
219 | */ |
220 | static void sl82c105_resetproc(ide_drive_t *drive) | |
221 | { | |
36501650 | 222 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
1da177e4 LT |
223 | u32 val; |
224 | ||
225 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
226 | ||
227 | pci_read_config_dword(dev, 0x40, &val); | |
08590556 BZ |
228 | val |= (CTRL_P1F16 | CTRL_P0F16); |
229 | pci_write_config_dword(dev, 0x40, val); | |
1da177e4 | 230 | } |
1da177e4 LT |
231 | |
232 | /* | |
233 | * Return the revision of the Winbond bridge | |
234 | * which this function is part of. | |
235 | */ | |
6c610641 | 236 | static u8 sl82c105_bridge_revision(struct pci_dev *dev) |
1da177e4 LT |
237 | { |
238 | struct pci_dev *bridge; | |
1da177e4 LT |
239 | |
240 | /* | |
241 | * The bridge should be part of the same device, but function 0. | |
242 | */ | |
640b31bf | 243 | bridge = pci_get_bus_and_slot(dev->bus->number, |
1da177e4 LT |
244 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
245 | if (!bridge) | |
246 | return -1; | |
247 | ||
248 | /* | |
249 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
250 | */ | |
251 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
252 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
253 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
254 | pci_dev_put(bridge); | |
1da177e4 | 255 | return -1; |
640b31bf | 256 | } |
1da177e4 LT |
257 | /* |
258 | * We need to find function 0's revision, not function 1 | |
259 | */ | |
640b31bf | 260 | pci_dev_put(bridge); |
1da177e4 | 261 | |
44c10138 | 262 | return bridge->revision; |
1da177e4 LT |
263 | } |
264 | ||
265 | /* | |
266 | * Enable the PCI device | |
267 | * | |
268 | * --BenH: It's arch fixup code that should enable channels that | |
269 | * have not been enabled by firmware. I decided we can still enable | |
270 | * channel 0 here at least, but channel 1 has to be enabled by | |
271 | * firmware or arch code. We still set both to 16 bits mode. | |
272 | */ | |
34a62246 | 273 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
274 | { |
275 | u32 val; | |
276 | ||
277 | DBG(("init_chipset_sl82c105()\n")); | |
278 | ||
279 | pci_read_config_dword(dev, 0x40, &val); | |
280 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
281 | pci_write_config_dword(dev, 0x40, val); | |
282 | ||
283 | return dev->irq; | |
284 | } | |
285 | ||
ac95beed BZ |
286 | static const struct ide_port_ops sl82c105_port_ops = { |
287 | .set_pio_mode = sl82c105_set_pio_mode, | |
288 | .set_dma_mode = sl82c105_set_dma_mode, | |
289 | .resetproc = sl82c105_resetproc, | |
290 | }; | |
291 | ||
f37afdac BZ |
292 | static const struct ide_dma_ops sl82c105_dma_ops = { |
293 | .dma_host_set = ide_dma_host_set, | |
294 | .dma_setup = ide_dma_setup, | |
295 | .dma_exec_cmd = ide_dma_exec_cmd, | |
5e37bdc0 BZ |
296 | .dma_start = sl82c105_dma_start, |
297 | .dma_end = sl82c105_dma_end, | |
f37afdac | 298 | .dma_test_irq = ide_dma_test_irq, |
5e37bdc0 BZ |
299 | .dma_lost_irq = sl82c105_dma_lost_irq, |
300 | .dma_timeout = sl82c105_dma_timeout, | |
301 | }; | |
302 | ||
85620436 | 303 | static const struct ide_port_info sl82c105_chipset __devinitdata = { |
1da177e4 LT |
304 | .name = "W82C105", |
305 | .init_chipset = init_chipset_sl82c105, | |
1da177e4 | 306 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, |
ac95beed | 307 | .port_ops = &sl82c105_port_ops, |
5e37bdc0 | 308 | .dma_ops = &sl82c105_dma_ops, |
caea7602 BZ |
309 | .host_flags = IDE_HFLAG_IO_32BIT | |
310 | IDE_HFLAG_UNMASK_IRQS | | |
5510b125 | 311 | /* FIXME: check for Compatibility mode in generic IDE PCI code */ |
7ef8df81 | 312 | #if defined(CONFIG_LOPEC) || defined(CONFIG_SANDPOINT) |
5510b125 BZ |
313 | IDE_HFLAG_FORCE_LEGACY_IRQS | |
314 | #endif | |
1fd18905 | 315 | IDE_HFLAG_SERIALIZE_DMA | |
5e71d9c5 | 316 | IDE_HFLAG_NO_AUTODMA, |
4099d143 | 317 | .pio_mask = ATA_PIO5, |
6c610641 | 318 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
319 | }; |
320 | ||
321 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
322 | { | |
6c610641 BZ |
323 | struct ide_port_info d = sl82c105_chipset; |
324 | u8 rev = sl82c105_bridge_revision(dev); | |
325 | ||
326 | if (rev <= 5) { | |
327 | /* | |
328 | * Never ever EVER under any circumstances enable | |
329 | * DMA when the bridge is this old. | |
330 | */ | |
331 | printk(KERN_INFO "W82C105_IDE: Winbond W83C553 bridge " | |
332 | "revision %d, BM-DMA disabled\n", rev); | |
5e37bdc0 | 333 | d.dma_ops = NULL; |
6c610641 | 334 | d.mwdma_mask = 0; |
1fd18905 | 335 | d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA; |
6c610641 BZ |
336 | } |
337 | ||
338 | return ide_setup_pci_device(dev, &d); | |
1da177e4 LT |
339 | } |
340 | ||
9cbcc5e3 BZ |
341 | static const struct pci_device_id sl82c105_pci_tbl[] = { |
342 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, | |
1da177e4 LT |
343 | { 0, }, |
344 | }; | |
345 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
346 | ||
347 | static struct pci_driver driver = { | |
348 | .name = "W82C105_IDE", | |
349 | .id_table = sl82c105_pci_tbl, | |
350 | .probe = sl82c105_init_one, | |
351 | }; | |
352 | ||
82ab1eec | 353 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
354 | { |
355 | return ide_pci_register_driver(&driver); | |
356 | } | |
357 | ||
358 | module_init(sl82c105_ide_init); | |
359 | ||
360 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
361 | MODULE_LICENSE("GPL"); |