[deliverable/linux.git] / drivers / ide / pci / slc90e66.c

/*
 *  linux/drivers/ide/pci/slc90e66.c	Version 0.18	Aug 9, 2007
 *
 *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
 * but this keeps the ISA-Bridge and slots alive.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
 	int control = 0;
				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	spin_lock_irqsave(&ide_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&ide_lock, flags);
}

static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int sitre = 0, a_speed	= 7 << (drive->dn * 4);
	int u_speed = 0, u_flag = 1 << drive->dn;
	u16			reg4042, reg44, reg48, reg4a;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_word(dev, 0x44, &reg44);
	pci_read_config_word(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);

	switch(speed) {
		case XFER_UDMA_4:	u_speed = 4 << (drive->dn * 4); break;
		case XFER_UDMA_3:	u_speed = 3 << (drive->dn * 4); break;
		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_SW_DMA_2:	break;
		default:		return;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_word(dev, 0x48, reg48|u_flag);
		/* FIXME: (reg4a & a_speed) ? */
		if ((reg4a & u_speed) != u_speed) {
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
			pci_read_config_word(dev, 0x4a, &reg4a);
			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
		}
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };
		u8 pio;

		if (reg48 & u_flag)
			pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);

		if (speed >= XFER_MW_DMA_0)
			pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
		else
			pio = 2; /* only SWDMA2 is allowed */

		slc90e66_set_pio_mode(drive, pio);
	}
}

static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
{
	u8 reg47 = 0;
	u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */

	if (!hwif->irq)
		hwif->irq = hwif->channel ? 15 : 14;

	hwif->set_pio_mode = &slc90e66_set_pio_mode;
	hwif->set_dma_mode = &slc90e66_set_dma_mode;

	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->ultra_mask = 0x1f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		/* bit[0(1)]: 0:80, 1:40 */
		hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

static ide_pci_device_t slc90e66_chipset __devinitdata = {
	.name		= "SLC90E66",
	.init_hwif	= init_hwif_slc90e66,
	.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
	.host_flags	= IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO4,
};

static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &slc90e66_chipset);
}

static const struct pci_device_id slc90e66_pci_tbl[] = {
	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);

static struct pci_driver driver = {
	.name		= "SLC90e66_IDE",
	.id_table	= slc90e66_pci_tbl,
	.probe		= slc90e66_init_one,
};

static int __init slc90e66_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(slc90e66_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1c54a93d	2	* linux/drivers/ide/pci/slc90e66.c Version 0.18 Aug 9, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
07af4276	5	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4	6	*
44854add	7	* This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
1da177e4 LT	8	* but this keeps the ISA-Bridge and slots alive.
	9	*
	10	*/
	11
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/ioport.h>
	16	#include <linux/pci.h>
	17	#include <linux/hdreg.h>
	18	#include <linux/ide.h>
	19	#include <linux/delay.h>
	20	#include <linux/init.h>
	21
	22	#include <asm/io.h>
	23
88b2b32b	24	static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	25	{
	26	ide_hwif_t *hwif = HWIF(drive);
	27	struct pci_dev *dev = hwif->pci_dev;
24e6458d	28	int is_slave = drive->dn & 1;
1da177e4 LT	29	int master_port = hwif->channel ? 0x42 : 0x40;
	30	int slave_port = 0x44;
	31	unsigned long flags;
	32	u16 master_data;
	33	u8 slave_data;
24e6458d SS	34	int control = 0;
24e6458d SS	35	/* ISP RTC */
f201f504	36	static const u8 timings[][2]= {
24e6458d SS	37	{ 0, 0 },
	38	{ 0, 0 },
	39	{ 1, 0 },
	40	{ 2, 1 },
	41	{ 2, 3 }, };
1da177e4	42
1da177e4 LT	43	spin_lock_irqsave(&ide_lock, flags);
1da177e4 LT	44	pci_read_config_word(dev, master_port, &master_data);
24e6458d SS	45
	46	if (pio > 1)
	47	control \|= 1; /* Programmable timing on */
	48	if (drive->media == ide_disk)
	49	control \|= 4; /* Prefetch, post write */
	50	if (pio > 2)
	51	control \|= 2; /* IORDY */
1da177e4	52	if (is_slave) {
24e6458d SS	53	master_data \|= 0x4000;
	54	master_data &= ~0x0070;
	55	if (pio > 1) {
07af4276 SS	56	/* Set PPE, IE and TIME */
07af4276 SS	57	master_data \|= control << 4;
24e6458d	58	}
1da177e4	59	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	60	slave_data &= hwif->channel ? 0x0f : 0xf0;
	61	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	62	(hwif->channel ? 4 : 0);
1da177e4	63	} else {
24e6458d SS	64	master_data &= ~0x3307;
24e6458d SS	65	if (pio > 1) {
1da177e4	66	/* enable PPE, IE and TIME */
07af4276	67	master_data \|= control;
24e6458d	68	}
07af4276	69	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	70	}
	71	pci_write_config_word(dev, master_port, master_data);
	72	if (is_slave)
	73	pci_write_config_byte(dev, slave_port, slave_data);
	74	spin_unlock_irqrestore(&ide_lock, flags);
	75	}
	76
88b2b32b	77	static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	78	{
	79	ide_hwif_t *hwif = HWIF(drive);
	80	struct pci_dev *dev = hwif->pci_dev;
	81	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	82	int sitre = 0, a_speed = 7 << (drive->dn * 4);
	83	int u_speed = 0, u_flag = 1 << drive->dn;
	84	u16 reg4042, reg44, reg48, reg4a;
	85
	86	pci_read_config_word(dev, maslave, &reg4042);
	87	sitre = (reg4042 & 0x4000) ? 1 : 0;
	88	pci_read_config_word(dev, 0x44, &reg44);
	89	pci_read_config_word(dev, 0x48, &reg48);
	90	pci_read_config_word(dev, 0x4a, &reg4a);
	91
	92	switch(speed) {
1da177e4 LT	93	case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
	94	case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
	95	case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
	96	case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
	97	case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
	98	case XFER_MW_DMA_2:
	99	case XFER_MW_DMA_1:
	100	case XFER_SW_DMA_2: break;
88b2b32b	101	default: return;
1da177e4 LT	102	}
	103
	104	if (speed >= XFER_UDMA_0) {
	105	if (!(reg48 & u_flag))
	106	pci_write_config_word(dev, 0x48, reg48\|u_flag);
	107	/* FIXME: (reg4a & a_speed) ? */
	108	if ((reg4a & u_speed) != u_speed) {
	109	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	110	pci_read_config_word(dev, 0x4a, &reg4a);
	111	pci_write_config_word(dev, 0x4a, reg4a\|u_speed);
	112	}
	113	} else {
8c91abf8	114	const u8 mwdma_to_pio[] = { 0, 3, 4 };
1c54a93d	115	u8 pio;
8c91abf8	116
1da177e4 LT	117	if (reg48 & u_flag)
	118	pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
	119	if (reg4a & a_speed)
	120	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
8c91abf8 BZ	121
	122	if (speed >= XFER_MW_DMA_0)
	123	pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
	124	else
	125	pio = 2; /* only SWDMA2 is allowed */
1da177e4	126
1c54a93d BZ	127	slc90e66_set_pio_mode(drive, pio);
1c54a93d BZ	128	}
1da177e4 LT	129	}
1da177e4 LT	130
97319630	131	static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
1da177e4 LT	132	{
	133	u8 reg47 = 0;
	134	u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
	135
1da177e4 LT	136	if (!hwif->irq)
	137	hwif->irq = hwif->channel ? 15 : 14;
	138
26bcb879	139	hwif->set_pio_mode = &slc90e66_set_pio_mode;
88b2b32b	140	hwif->set_dma_mode = &slc90e66_set_dma_mode;
1da177e4 LT	141
	142	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
	143
a7b888b2 BZ	144	hwif->drives[0].autotune = 1;
	145	hwif->drives[1].autotune = 1;
	146
	147	if (hwif->dma_base == 0)
1da177e4	148	return;
1da177e4	149
1da177e4	150	hwif->ultra_mask = 0x1f;
24e6458d SS	151	hwif->mwdma_mask = 0x06;
24e6458d SS	152	hwif->swdma_mask = 0x04;
1da177e4	153
49521f97	154	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1da177e4	155	/* bit[0(1)]: 0:80, 1:40 */
49521f97	156	hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	157	}
	158
	159	static ide_pci_device_t slc90e66_chipset __devinitdata = {
	160	.name = "SLC90E66",
	161	.init_hwif = init_hwif_slc90e66,
1da177e4	162	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
7cab14a7	163	.host_flags = IDE_HFLAG_BOOTABLE,
4099d143	164	.pio_mask = ATA_PIO4,
1da177e4 LT	165	};
	166
	167	static int __devinit slc90e66_init_one(struct pci_dev dev, const struct pci_device_id id)
	168	{
	169	return ide_setup_pci_device(dev, &slc90e66_chipset);
	170	}
	171
9cbcc5e3 BZ	172	static const struct pci_device_id slc90e66_pci_tbl[] = {
9cbcc5e3 BZ	173	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
1da177e4 LT	174	{ 0, },
	175	};
	176	MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
	177
	178	static struct pci_driver driver = {
	179	.name = "SLC90e66_IDE",
	180	.id_table = slc90e66_pci_tbl,
	181	.probe = slc90e66_init_one,
	182	};
	183
82ab1eec	184	static int __init slc90e66_ide_init(void)
1da177e4 LT	185	{
	186	return ide_pci_register_driver(&driver);
	187	}
	188
	189	module_init(slc90e66_ide_init);
	190
	191	MODULE_AUTHOR("Andre Hedrick");
	192	MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
	193	MODULE_LICENSE("GPL");