Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
75b1d975 | 3 | * Version 3.40 |
1da177e4 LT |
4 | * |
5 | * VIA IDE driver for Linux. Supported southbridges: | |
6 | * | |
7 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
8 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 9 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
10 | * |
11 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
75b1d975 | 12 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
13 | * |
14 | * Based on the work of: | |
15 | * Michel Aubry | |
16 | * Jeff Garzik | |
17 | * Andre Hedrick | |
18 | * | |
19 | * Documentation: | |
20 | * Obsolete device documentation publically available from via.com.tw | |
21 | * Current device documentation available under NDA only | |
22 | */ | |
23 | ||
24 | /* | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License version 2 as published by | |
27 | * the Free Software Foundation. | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/blkdev.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ide.h> | |
37 | #include <asm/io.h> | |
38 | ||
74a9d5f1 | 39 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
40 | #include <asm/processor.h> |
41 | #endif | |
42 | ||
43 | #include "ide-timing.h" | |
44 | ||
1da177e4 LT |
45 | #define VIA_IDE_ENABLE 0x40 |
46 | #define VIA_IDE_CONFIG 0x41 | |
47 | #define VIA_FIFO_CONFIG 0x43 | |
48 | #define VIA_MISC_1 0x44 | |
49 | #define VIA_MISC_2 0x45 | |
50 | #define VIA_MISC_3 0x46 | |
51 | #define VIA_DRIVE_TIMING 0x48 | |
52 | #define VIA_8BIT_TIMING 0x4e | |
53 | #define VIA_ADDRESS_SETUP 0x4c | |
54 | #define VIA_UDMA_TIMING 0x50 | |
55 | ||
75b1d975 BZ |
56 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
57 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
58 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
59 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
60 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
61 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
1da177e4 LT |
62 | |
63 | /* | |
64 | * VIA SouthBridge chips. | |
65 | */ | |
66 | ||
67 | static struct via_isa_bridge { | |
68 | char *name; | |
69 | u16 id; | |
70 | u8 rev_min; | |
71 | u8 rev_max; | |
75b1d975 BZ |
72 | u8 udma_mask; |
73 | u8 flags; | |
1da177e4 | 74 | } via_isa_bridges[] = { |
75b1d975 BZ |
75 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
76 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
77 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
78 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
79 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
80 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
81 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
82 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
83 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
84 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
85 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
86 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
87 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
88 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
89 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
90 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
91 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
92 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
93 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
94 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
95 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
96 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
97 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
1da177e4 LT |
98 | { NULL } |
99 | }; | |
100 | ||
1da177e4 | 101 | static unsigned int via_clock; |
75b1d975 | 102 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 103 | |
7462cbff DD |
104 | struct via82cxxx_dev |
105 | { | |
106 | struct via_isa_bridge *via_config; | |
107 | unsigned int via_80w; | |
108 | }; | |
109 | ||
1da177e4 LT |
110 | /** |
111 | * via_set_speed - write timing registers | |
112 | * @dev: PCI device | |
113 | * @dn: device | |
114 | * @timing: IDE timing data to use | |
115 | * | |
116 | * via_set_speed writes timing values to the chipset registers | |
117 | */ | |
118 | ||
7462cbff | 119 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 120 | { |
7462cbff | 121 | struct pci_dev *dev = hwif->pci_dev; |
cd36beec | 122 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
123 | u8 t; |
124 | ||
7462cbff | 125 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 LT |
126 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
127 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
128 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); | |
129 | } | |
130 | ||
131 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
132 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
133 | ||
134 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
135 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
136 | ||
75b1d975 BZ |
137 | switch (vdev->via_config->udma_mask) { |
138 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | |
139 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
140 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
141 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
142 | default: return; | |
1da177e4 LT |
143 | } |
144 | ||
145 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
146 | } | |
147 | ||
148 | /** | |
149 | * via_set_drive - configure transfer mode | |
150 | * @drive: Drive to set up | |
151 | * @speed: desired speed | |
152 | * | |
153 | * via_set_drive() computes timing values configures the drive and | |
154 | * the chipset to a desired transfer mode. It also can be called | |
155 | * by upper layers. | |
156 | */ | |
157 | ||
158 | static int via_set_drive(ide_drive_t *drive, u8 speed) | |
159 | { | |
160 | ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1); | |
cd36beec | 161 | struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev); |
1da177e4 LT |
162 | struct ide_timing t, p; |
163 | unsigned int T, UT; | |
164 | ||
165 | if (speed != XFER_PIO_SLOW) | |
166 | ide_config_drive_speed(drive, speed); | |
167 | ||
168 | T = 1000000000 / via_clock; | |
169 | ||
75b1d975 BZ |
170 | switch (vdev->via_config->udma_mask) { |
171 | case ATA_UDMA2: UT = T; break; | |
172 | case ATA_UDMA4: UT = T/2; break; | |
173 | case ATA_UDMA5: UT = T/3; break; | |
174 | case ATA_UDMA6: UT = T/4; break; | |
175 | default: UT = T; | |
1da177e4 LT |
176 | } |
177 | ||
178 | ide_timing_compute(drive, speed, &t, T, UT); | |
179 | ||
180 | if (peer->present) { | |
181 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
182 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
183 | } | |
184 | ||
7462cbff | 185 | via_set_speed(HWIF(drive), drive->dn, &t); |
1da177e4 LT |
186 | |
187 | if (!drive->init_speed) | |
188 | drive->init_speed = speed; | |
189 | drive->current_speed = speed; | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | /** | |
195 | * via82cxxx_tune_drive - PIO setup | |
196 | * @drive: drive to set up | |
197 | * @pio: mode to use (255 for 'best possible') | |
198 | * | |
199 | * A callback from the upper layers for PIO-only tuning. | |
200 | */ | |
201 | ||
202 | static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio) | |
203 | { | |
204 | if (pio == 255) { | |
75b1d975 | 205 | via_set_drive(drive, ide_find_best_pio_mode(drive)); |
1da177e4 LT |
206 | return; |
207 | } | |
208 | ||
209 | via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5)); | |
210 | } | |
211 | ||
212 | /** | |
213 | * via82cxxx_ide_dma_check - set up for DMA if possible | |
214 | * @drive: IDE drive to set up | |
215 | * | |
216 | * Set up the drive for the highest supported speed considering the | |
217 | * driver, controller and cable | |
218 | */ | |
219 | ||
220 | static int via82cxxx_ide_dma_check (ide_drive_t *drive) | |
221 | { | |
75b1d975 | 222 | u8 speed = ide_max_dma_mode(drive); |
1da177e4 | 223 | |
75b1d975 BZ |
224 | if (speed == 0) |
225 | speed = ide_find_best_pio_mode(drive); | |
1da177e4 LT |
226 | |
227 | via_set_drive(drive, speed); | |
228 | ||
229 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) | |
3608b5d7 BZ |
230 | return 0; |
231 | ||
232 | return -1; | |
7462cbff DD |
233 | } |
234 | ||
235 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) | |
236 | { | |
237 | struct via_isa_bridge *via_config; | |
238 | u8 t; | |
239 | ||
240 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 241 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
242 | !!(via_config->flags & VIA_BAD_ID), |
243 | via_config->id, NULL))) { | |
244 | ||
245 | pci_read_config_byte(*isa, PCI_REVISION_ID, &t); | |
246 | if (t >= via_config->rev_min && | |
247 | t <= via_config->rev_max) | |
248 | break; | |
652aa162 | 249 | pci_dev_put(*isa); |
7462cbff DD |
250 | } |
251 | ||
252 | return via_config; | |
1da177e4 LT |
253 | } |
254 | ||
cd36beec BZ |
255 | /* |
256 | * Check and handle 80-wire cable presence | |
257 | */ | |
258 | static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u) | |
259 | { | |
260 | int i; | |
261 | ||
75b1d975 BZ |
262 | switch (vdev->via_config->udma_mask) { |
263 | case ATA_UDMA4: | |
cd36beec BZ |
264 | for (i = 24; i >= 0; i -= 8) |
265 | if (((u >> (i & 16)) & 8) && | |
266 | ((u >> i) & 0x20) && | |
267 | (((u >> i) & 7) < 2)) { | |
268 | /* | |
269 | * 2x PCI clock and | |
270 | * UDMA w/ < 3T/cycle | |
271 | */ | |
272 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
273 | } | |
274 | break; | |
275 | ||
75b1d975 | 276 | case ATA_UDMA5: |
cd36beec BZ |
277 | for (i = 24; i >= 0; i -= 8) |
278 | if (((u >> i) & 0x10) || | |
279 | (((u >> i) & 0x20) && | |
280 | (((u >> i) & 7) < 4))) { | |
281 | /* BIOS 80-wire bit or | |
282 | * UDMA w/ < 60ns/cycle | |
283 | */ | |
284 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
285 | } | |
286 | break; | |
287 | ||
75b1d975 | 288 | case ATA_UDMA6: |
cd36beec BZ |
289 | for (i = 24; i >= 0; i -= 8) |
290 | if (((u >> i) & 0x10) || | |
291 | (((u >> i) & 0x20) && | |
292 | (((u >> i) & 7) < 6))) { | |
293 | /* BIOS 80-wire bit or | |
294 | * UDMA w/ < 60ns/cycle | |
295 | */ | |
296 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
297 | } | |
298 | break; | |
299 | } | |
300 | } | |
301 | ||
1da177e4 LT |
302 | /** |
303 | * init_chipset_via82cxxx - initialization handler | |
304 | * @dev: PCI device | |
305 | * @name: Name of interface | |
306 | * | |
307 | * The initialization callback. Here we determine the IDE chip type | |
308 | * and initialize its drive independent registers. | |
309 | */ | |
310 | ||
f3718d3e | 311 | static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name) |
1da177e4 LT |
312 | { |
313 | struct pci_dev *isa = NULL; | |
cd36beec | 314 | struct via82cxxx_dev *vdev; |
7462cbff | 315 | struct via_isa_bridge *via_config; |
1da177e4 | 316 | u8 t, v; |
cd36beec BZ |
317 | u32 u; |
318 | ||
319 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); | |
320 | if (!vdev) { | |
321 | printk(KERN_ERR "VP_IDE: out of memory :(\n"); | |
322 | return -ENOMEM; | |
323 | } | |
324 | pci_set_drvdata(dev, vdev); | |
1da177e4 LT |
325 | |
326 | /* | |
327 | * Find the ISA bridge to see how good the IDE is. | |
328 | */ | |
cd36beec | 329 | vdev->via_config = via_config = via_config_find(&isa); |
23a1b2a7 AC |
330 | |
331 | /* We checked this earlier so if it fails here deeep badness | |
332 | is involved */ | |
333 | ||
334 | BUG_ON(!via_config->id); | |
1da177e4 LT |
335 | |
336 | /* | |
cd36beec | 337 | * Detect cable and configure Clk66 |
1da177e4 | 338 | */ |
cd36beec BZ |
339 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
340 | ||
341 | via_cable_detect(vdev, u); | |
1da177e4 | 342 | |
75b1d975 | 343 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 344 | /* Enable Clk66 */ |
7462cbff DD |
345 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
346 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 347 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
348 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
349 | } | |
350 | ||
351 | /* | |
352 | * Check whether interfaces are enabled. | |
353 | */ | |
354 | ||
355 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
356 | ||
357 | /* | |
358 | * Set up FIFO sizes and thresholds. | |
359 | */ | |
360 | ||
361 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
362 | ||
363 | /* Disable PREQ# till DDACK# */ | |
364 | if (via_config->flags & VIA_BAD_PREQ) { | |
365 | /* Would crash on 586b rev 41 */ | |
366 | t &= 0x7f; | |
367 | } | |
368 | ||
369 | /* Fix FIFO split between channels */ | |
370 | if (via_config->flags & VIA_SET_FIFO) { | |
371 | t &= (t & 0x9f); | |
372 | switch (v & 3) { | |
373 | case 2: t |= 0x00; break; /* 16 on primary */ | |
374 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
375 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
376 | } | |
377 | } | |
378 | ||
379 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
380 | ||
381 | /* | |
382 | * Determine system bus clock. | |
383 | */ | |
384 | ||
385 | via_clock = system_bus_clock() * 1000; | |
386 | ||
387 | switch (via_clock) { | |
388 | case 33000: via_clock = 33333; break; | |
389 | case 37000: via_clock = 37500; break; | |
390 | case 41000: via_clock = 41666; break; | |
391 | } | |
392 | ||
393 | if (via_clock < 20000 || via_clock > 50000) { | |
394 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
395 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
396 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
397 | "to assume 80-wire cable.\n"); | |
398 | via_clock = 33333; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Print the boot message. | |
403 | */ | |
404 | ||
405 | pci_read_config_byte(isa, PCI_REVISION_ID, &t); | |
75b1d975 | 406 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s " |
1da177e4 LT |
407 | "controller on pci%s\n", |
408 | via_config->name, t, | |
75b1d975 BZ |
409 | via_config->udma_mask ? "U" : "MW", |
410 | via_dma[via_config->udma_mask ? | |
411 | (fls(via_config->udma_mask) - 1) : 0], | |
1da177e4 LT |
412 | pci_name(dev)); |
413 | ||
652aa162 | 414 | pci_dev_put(isa); |
1da177e4 LT |
415 | return 0; |
416 | } | |
417 | ||
f3718d3e | 418 | static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif) |
1da177e4 | 419 | { |
cd36beec | 420 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
421 | int i; |
422 | ||
423 | hwif->autodma = 0; | |
424 | ||
425 | hwif->tuneproc = &via82cxxx_tune_drive; | |
426 | hwif->speedproc = &via_set_drive; | |
427 | ||
428 | ||
74a9d5f1 | 429 | #ifdef CONFIG_PPC_CHRP |
e8222502 | 430 | if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) { |
1da177e4 LT |
431 | hwif->irq = hwif->channel ? 15 : 14; |
432 | } | |
433 | #endif | |
434 | ||
435 | for (i = 0; i < 2; i++) { | |
436 | hwif->drives[i].io_32bit = 1; | |
7462cbff | 437 | hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1; |
1da177e4 LT |
438 | hwif->drives[i].autotune = 1; |
439 | hwif->drives[i].dn = hwif->channel * 2 + i; | |
440 | } | |
441 | ||
442 | if (!hwif->dma_base) | |
443 | return; | |
444 | ||
445 | hwif->atapi_dma = 1; | |
75b1d975 BZ |
446 | |
447 | hwif->ultra_mask = vdev->via_config->udma_mask; | |
1da177e4 LT |
448 | hwif->mwdma_mask = 0x07; |
449 | hwif->swdma_mask = 0x07; | |
450 | ||
451 | if (!hwif->udma_four) | |
7462cbff | 452 | hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1; |
1da177e4 LT |
453 | hwif->ide_dma_check = &via82cxxx_ide_dma_check; |
454 | if (!noautodma) | |
455 | hwif->autodma = 1; | |
456 | hwif->drives[0].autodma = hwif->autodma; | |
457 | hwif->drives[1].autodma = hwif->autodma; | |
458 | } | |
459 | ||
4f1d774a MK |
460 | static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = { |
461 | { /* 0 */ | |
462 | .name = "VP_IDE", | |
463 | .init_chipset = init_chipset_via82cxxx, | |
464 | .init_hwif = init_hwif_via82cxxx, | |
465 | .channels = 2, | |
466 | .autodma = NOAUTODMA, | |
467 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, | |
468 | .bootable = ON_BOARD | |
469 | },{ /* 1 */ | |
470 | .name = "VP_IDE", | |
471 | .init_chipset = init_chipset_via82cxxx, | |
472 | .init_hwif = init_hwif_via82cxxx, | |
473 | .channels = 2, | |
474 | .autodma = AUTODMA, | |
475 | .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, | |
476 | .bootable = ON_BOARD, | |
477 | } | |
1da177e4 LT |
478 | }; |
479 | ||
480 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
481 | { | |
23a1b2a7 AC |
482 | struct pci_dev *isa = NULL; |
483 | struct via_isa_bridge *via_config; | |
484 | /* | |
485 | * Find the ISA bridge and check we know what it is. | |
486 | */ | |
487 | via_config = via_config_find(&isa); | |
488 | pci_dev_put(isa); | |
489 | if (!via_config->id) { | |
490 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
491 | return -ENODEV; | |
492 | } | |
4f1d774a | 493 | return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]); |
1da177e4 LT |
494 | } |
495 | ||
496 | static struct pci_device_id via_pci_tbl[] = { | |
497 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
498 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
4f1d774a | 499 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
e0b874df | 500 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1da177e4 LT |
501 | { 0, }, |
502 | }; | |
503 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
504 | ||
505 | static struct pci_driver driver = { | |
506 | .name = "VIA_IDE", | |
507 | .id_table = via_pci_tbl, | |
508 | .probe = via_init_one, | |
509 | }; | |
510 | ||
82ab1eec | 511 | static int __init via_ide_init(void) |
1da177e4 LT |
512 | { |
513 | return ide_pci_register_driver(&driver); | |
514 | } | |
515 | ||
516 | module_init(via_ide_init); | |
517 | ||
518 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
519 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
520 | MODULE_LICENSE("GPL"); |