[deliverable/linux.git] / drivers / ide / pci / via82cxxx.c

/*
 *
 * Version 3.38
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define DISPLAY_VIA_TIMINGS

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_UDMA		0x007
#define VIA_UDMA_NONE		0x000
#define VIA_UDMA_33		0x001
#define VIA_UDMA_66		0x002
#define VIA_UDMA_100		0x003
#define VIA_UDMA_133		0x004
#define VIA_BAD_PREQ		0x010	/* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x020	/* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x040	/* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x080	/* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x100	/* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x200	/* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u16 flags;
} via_isa_bridges[] = {
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, VIA_UDMA_100 },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, VIA_UDMA_100 },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->flags & VIA_UDMA) {
		case VIA_UDMA_33:  t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
		case VIA_UDMA_66:  t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
		case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
		case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
		default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the drive and
 *	the chipset to a desired transfer mode. It also can be called
 *	by upper layers.
 */

static int via_set_drive(ide_drive_t *drive, u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
	struct ide_timing t, p;
	unsigned int T, UT;

	if (speed != XFER_PIO_SLOW)
		ide_config_drive_speed(drive, speed);

	T = 1000000000 / via_clock;

	switch (vdev->via_config->flags & VIA_UDMA) {
		case VIA_UDMA_33:   UT = T;   break;
		case VIA_UDMA_66:   UT = T/2; break;
		case VIA_UDMA_100:  UT = T/3; break;
		case VIA_UDMA_133:  UT = T/4; break;
		default: UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);

	if (!drive->init_speed)
		drive->init_speed = speed;
	drive->current_speed = speed;

	return 0;
}

/**
 *	via82cxxx_tune_drive	-	PIO setup
 *	@drive: drive to set up
 *	@pio: mode to use (255 for 'best possible')
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
{
	if (pio == 255) {
		via_set_drive(drive,
			ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
		return;
	}

	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
}

/**
 *	via82cxxx_ide_dma_check		-	set up for DMA if possible
 *	@drive: IDE drive to set up
 *
 *	Set up the drive for the highest supported speed considering the
 *	driver, controller and cable
 */
 
static int via82cxxx_ide_dma_check (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	u16 w80 = hwif->udma_four;

	u16 speed = ide_find_best_mode(drive,
		XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
		(vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));

	via_set_drive(drive, speed);

	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
		return hwif->ide_dma_on(drive);
	return hwif->ide_dma_off_quietly(drive);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;
	u8 t;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
			if (t >= via_config->rev_min &&
			    t <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->flags & VIA_UDMA) {
		case VIA_UDMA_66:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case VIA_UDMA_100:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case VIA_UDMA_133:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via82cxxx_dev *vdev;
	struct via_isa_bridge *via_config;
	u8 t, v;
	u32 u;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return -ENOMEM;
	}
	pci_set_drvdata(dev, vdev);

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	vdev->via_config = via_config = via_config_find(&isa);

	/* We checked this earlier so if it fails here deeep badness
	   is involved */

	BUG_ON(!via_config->id);

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
		"controller on pci%s\n",
		via_config->name, t,
		via_dma[via_config->flags & VIA_UDMA],
		pci_name(dev));

	pci_dev_put(isa);
	return 0;
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	int i;

	hwif->autodma = 0;

	hwif->tuneproc = &via82cxxx_tune_drive;
	hwif->speedproc = &via_set_drive;


#ifdef CONFIG_PPC_CHRP
	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
		hwif->irq = hwif->channel ? 15 : 14;
	}
#endif

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x7f;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;

	if (!hwif->udma_four)
		hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= NOAUTODMA,
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
		.bootable	= ON_BOARD
	},{	/* 1 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
		.bootable	= ON_BOARD,
	}
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);
	pci_dev_put(isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
}

static struct pci_device_id via_pci_tbl[] = {
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	*
	3	* Version 3.38
	4	*
	5	* VIA IDE driver for Linux. Supported southbridges:
	6	*
	7	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	8	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	9	* vt8235, vt8237, vt8237a
1da177e4 LT	10	*
	11	* Copyright (c) 2000-2002 Vojtech Pavlik
	12	*
	13	* Based on the work of:
	14	* Michel Aubry
	15	* Jeff Garzik
	16	* Andre Hedrick
	17	*
	18	* Documentation:
	19	* Obsolete device documentation publically available from via.com.tw
	20	* Current device documentation available under NDA only
	21	*/
	22
	23	/*
	24	* This program is free software; you can redistribute it and/or modify it
	25	* under the terms of the GNU General Public License version 2 as published by
	26	* the Free Software Foundation.
	27	*/
	28
1da177e4 LT	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/ioport.h>
	32	#include <linux/blkdev.h>
	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/ide.h>
	36	#include <asm/io.h>
	37
74a9d5f1	38	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	39	#include <asm/processor.h>
	40	#endif
	41
	42	#include "ide-timing.h"
	43
	44	#define DISPLAY_VIA_TIMINGS
	45
	46	#define VIA_IDE_ENABLE 0x40
	47	#define VIA_IDE_CONFIG 0x41
	48	#define VIA_FIFO_CONFIG 0x43
	49	#define VIA_MISC_1 0x44
	50	#define VIA_MISC_2 0x45
	51	#define VIA_MISC_3 0x46
	52	#define VIA_DRIVE_TIMING 0x48
	53	#define VIA_8BIT_TIMING 0x4e
	54	#define VIA_ADDRESS_SETUP 0x4c
	55	#define VIA_UDMA_TIMING 0x50
	56
	57	#define VIA_UDMA 0x007
	58	#define VIA_UDMA_NONE 0x000
	59	#define VIA_UDMA_33 0x001
	60	#define VIA_UDMA_66 0x002
	61	#define VIA_UDMA_100 0x003
	62	#define VIA_UDMA_133 0x004
	63	#define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
	64	#define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
	65	#define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
	66	#define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
	67	#define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
	68	#define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
	69
	70	/*
	71	* VIA SouthBridge chips.
	72	*/
	73
	74	static struct via_isa_bridge {
	75	char *name;
	76	u16 id;
	77	u8 rev_min;
	78	u8 rev_max;
	79	u16 flags;
	80	} via_isa_bridges[] = {
4f1d774a	81	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
ceef833b	82	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
1da177e4	83	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
a7dec1e0	84	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
1da177e4 LT	85	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	86	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	87	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
	88	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
	89	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
	90	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
	91	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
	92	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	93	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
	94	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 \| VIA_SET_FIFO },
	96	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 \| VIA_SET_FIFO \| VIA_BAD_PREQ },
	97	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 \| VIA_SET_FIFO },
	98	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 \| VIA_SET_FIFO },
	99	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE \| VIA_SET_FIFO },
	100	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK },
	101	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
	102	{ NULL }
	103	};
	104
1da177e4 LT	105	static unsigned int via_clock;
	106	static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
	107
7462cbff DD	108	struct via82cxxx_dev
	109	{
	110	struct via_isa_bridge *via_config;
	111	unsigned int via_80w;
	112	};
	113
1da177e4 LT	114	/**
	115	* via_set_speed - write timing registers
	116	* @dev: PCI device
	117	* @dn: device
	118	* @timing: IDE timing data to use
	119	*
	120	* via_set_speed writes timing values to the chipset registers
	121	*/
	122
7462cbff	123	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	124	{
7462cbff	125	struct pci_dev *dev = hwif->pci_dev;
cd36beec	126	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	127	u8 t;
1da177e4 LT	128
7462cbff	129	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	130	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	131	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	132	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	133	}
	134
	135	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	136	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	137
	138	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	139	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	140
7462cbff	141	switch (vdev->via_config->flags & VIA_UDMA) {
1da177e4 LT	142	case VIA_UDMA_33: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	143	case VIA_UDMA_66: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	144	case VIA_UDMA_100: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	145	case VIA_UDMA_133: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	146	default: return;
	147	}
	148
	149	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	150	}
	151
	152	/**
	153	* via_set_drive - configure transfer mode
	154	* @drive: Drive to set up
	155	* @speed: desired speed
	156	*
	157	* via_set_drive() computes timing values configures the drive and
	158	* the chipset to a desired transfer mode. It also can be called
	159	* by upper layers.
	160	*/
	161
	162	static int via_set_drive(ide_drive_t *drive, u8 speed)
	163	{
	164	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
cd36beec	165	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
1da177e4 LT	166	struct ide_timing t, p;
	167	unsigned int T, UT;
	168
	169	if (speed != XFER_PIO_SLOW)
	170	ide_config_drive_speed(drive, speed);
	171
	172	T = 1000000000 / via_clock;
	173
7462cbff	174	switch (vdev->via_config->flags & VIA_UDMA) {
1da177e4 LT	175	case VIA_UDMA_33: UT = T; break;
	176	case VIA_UDMA_66: UT = T/2; break;
	177	case VIA_UDMA_100: UT = T/3; break;
	178	case VIA_UDMA_133: UT = T/4; break;
	179	default: UT = T;
	180	}
	181
	182	ide_timing_compute(drive, speed, &t, T, UT);
	183
	184	if (peer->present) {
	185	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	186	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	187	}
	188
7462cbff	189	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	190
	191	if (!drive->init_speed)
	192	drive->init_speed = speed;
	193	drive->current_speed = speed;
	194
	195	return 0;
	196	}
	197
	198	/**
	199	* via82cxxx_tune_drive - PIO setup
	200	* @drive: drive to set up
	201	* @pio: mode to use (255 for 'best possible')
	202	*
	203	* A callback from the upper layers for PIO-only tuning.
	204	*/
	205
	206	static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
	207	{
	208	if (pio == 255) {
	209	via_set_drive(drive,
	210	ide_find_best_mode(drive, XFER_PIO \| XFER_EPIO));
	211	return;
	212	}
	213
	214	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
	215	}
	216
	217	/**
	218	* via82cxxx_ide_dma_check - set up for DMA if possible
	219	* @drive: IDE drive to set up
	220	*
	221	* Set up the drive for the highest supported speed considering the
	222	* driver, controller and cable
	223	*/
	224
	225	static int via82cxxx_ide_dma_check (ide_drive_t *drive)
	226	{
7462cbff	227	ide_hwif_t *hwif = HWIF(drive);
cd36beec	228	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
7462cbff	229	u16 w80 = hwif->udma_four;
1da177e4 LT	230
	231	u16 speed = ide_find_best_mode(drive,
	232	XFER_PIO \| XFER_EPIO \| XFER_SWDMA \| XFER_MWDMA \|
7462cbff DD	233	(vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) \|
	234	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) \|
	235	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) \|
	236	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
1da177e4 LT	237
	238	via_set_drive(drive, speed);
	239
	240	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
7462cbff DD	241	return hwif->ide_dma_on(drive);
	242	return hwif->ide_dma_off_quietly(drive);
	243	}
	244
	245	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	246	{
	247	struct via_isa_bridge *via_config;
	248	u8 t;
	249
	250	for (via_config = via_isa_bridges; via_config->id; via_config++)
652aa162	251	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	252	!!(via_config->flags & VIA_BAD_ID),
	253	via_config->id, NULL))) {
	254
	255	pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
	256	if (t >= via_config->rev_min &&
	257	t <= via_config->rev_max)
	258	break;
652aa162	259	pci_dev_put(*isa);
7462cbff DD	260	}
	261
	262	return via_config;
1da177e4 LT	263	}
1da177e4 LT	264
cd36beec BZ	265	/*
	266	* Check and handle 80-wire cable presence
	267	*/
	268	static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
	269	{
	270	int i;
	271
	272	switch (vdev->via_config->flags & VIA_UDMA) {
	273	case VIA_UDMA_66:
	274	for (i = 24; i >= 0; i -= 8)
	275	if (((u >> (i & 16)) & 8) &&
	276	((u >> i) & 0x20) &&
	277	(((u >> i) & 7) < 2)) {
	278	/*
	279	* 2x PCI clock and
	280	* UDMA w/ < 3T/cycle
	281	*/
	282	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	283	}
	284	break;
	285
	286	case VIA_UDMA_100:
	287	for (i = 24; i >= 0; i -= 8)
	288	if (((u >> i) & 0x10) \|\|
	289	(((u >> i) & 0x20) &&
	290	(((u >> i) & 7) < 4))) {
	291	/* BIOS 80-wire bit or
	292	* UDMA w/ < 60ns/cycle
	293	*/
	294	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	295	}
	296	break;
	297
	298	case VIA_UDMA_133:
	299	for (i = 24; i >= 0; i -= 8)
	300	if (((u >> i) & 0x10) \|\|
	301	(((u >> i) & 0x20) &&
	302	(((u >> i) & 7) < 6))) {
	303	/* BIOS 80-wire bit or
	304	* UDMA w/ < 60ns/cycle
	305	*/
	306	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	307	}
	308	break;
	309	}
	310	}
	311
1da177e4 LT	312	/**
	313	* init_chipset_via82cxxx - initialization handler
	314	* @dev: PCI device
	315	* @name: Name of interface
	316	*
	317	* The initialization callback. Here we determine the IDE chip type
	318	* and initialize its drive independent registers.
	319	*/
	320
f3718d3e	321	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	322	{
1da177e4 LT	323	struct pci_dev *isa = NULL;
cd36beec	324	struct via82cxxx_dev *vdev;
7462cbff	325	struct via_isa_bridge *via_config;
1da177e4	326	u8 t, v;
cd36beec BZ	327	u32 u;
	328
	329	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	330	if (!vdev) {
	331	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	332	return -ENOMEM;
	333	}
	334	pci_set_drvdata(dev, vdev);
1da177e4 LT	335
	336	/*
	337	* Find the ISA bridge to see how good the IDE is.
	338	*/
cd36beec	339	vdev->via_config = via_config = via_config_find(&isa);
23a1b2a7 AC	340
	341	/* We checked this earlier so if it fails here deeep badness
	342	is involved */
	343
	344	BUG_ON(!via_config->id);
1da177e4 LT	345
1da177e4 LT	346	/*
cd36beec	347	* Detect cable and configure Clk66
1da177e4	348	*/
cd36beec BZ	349	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	350
	351	via_cable_detect(vdev, u);
1da177e4	352
7462cbff DD	353	if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) {
7462cbff DD	354	/* Enable Clk66 */
7462cbff DD	355	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	356	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	357	/* Would cause trouble on 596a and 686 */
1da177e4 LT	358	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	359	}
	360
	361	/*
	362	* Check whether interfaces are enabled.
	363	*/
	364
	365	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	366
	367	/*
	368	* Set up FIFO sizes and thresholds.
	369	*/
	370
	371	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	372
	373	/* Disable PREQ# till DDACK# */
	374	if (via_config->flags & VIA_BAD_PREQ) {
	375	/* Would crash on 586b rev 41 */
	376	t &= 0x7f;
	377	}
	378
	379	/* Fix FIFO split between channels */
	380	if (via_config->flags & VIA_SET_FIFO) {
	381	t &= (t & 0x9f);
	382	switch (v & 3) {
	383	case 2: t \|= 0x00; break; /* 16 on primary */
	384	case 1: t \|= 0x60; break; /* 16 on secondary */
	385	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	386	}
	387	}
	388
	389	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	390
	391	/*
	392	* Determine system bus clock.
	393	*/
	394
	395	via_clock = system_bus_clock() * 1000;
	396
	397	switch (via_clock) {
	398	case 33000: via_clock = 33333; break;
	399	case 37000: via_clock = 37500; break;
	400	case 41000: via_clock = 41666; break;
	401	}
	402
	403	if (via_clock < 20000 \|\| via_clock > 50000) {
	404	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	405	"impossible (%d), using 33 MHz instead.\n", via_clock);
	406	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	407	"to assume 80-wire cable.\n");
	408	via_clock = 33333;
	409	}
	410
	411	/*
	412	* Print the boot message.
	413	*/
	414
	415	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	416	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
	417	"controller on pci%s\n",
	418	via_config->name, t,
	419	via_dma[via_config->flags & VIA_UDMA],
	420	pci_name(dev));
	421
652aa162	422	pci_dev_put(isa);
1da177e4 LT	423	return 0;
	424	}
	425
f3718d3e	426	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	427	{
cd36beec	428	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	429	int i;
	430
	431	hwif->autodma = 0;
	432
	433	hwif->tuneproc = &via82cxxx_tune_drive;
	434	hwif->speedproc = &via_set_drive;
	435
	436
74a9d5f1	437	#ifdef CONFIG_PPC_CHRP
e8222502	438	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
1da177e4 LT	439	hwif->irq = hwif->channel ? 15 : 14;
	440	}
	441	#endif
	442
	443	for (i = 0; i < 2; i++) {
	444	hwif->drives[i].io_32bit = 1;
7462cbff	445	hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
1da177e4 LT	446	hwif->drives[i].autotune = 1;
	447	hwif->drives[i].dn = hwif->channel * 2 + i;
	448	}
	449
	450	if (!hwif->dma_base)
	451	return;
	452
	453	hwif->atapi_dma = 1;
	454	hwif->ultra_mask = 0x7f;
	455	hwif->mwdma_mask = 0x07;
	456	hwif->swdma_mask = 0x07;
	457
	458	if (!hwif->udma_four)
7462cbff	459	hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
1da177e4 LT	460	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	461	if (!noautodma)
	462	hwif->autodma = 1;
	463	hwif->drives[0].autodma = hwif->autodma;
	464	hwif->drives[1].autodma = hwif->autodma;
	465	}
	466
4f1d774a MK	467	static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	468	{ /* 0 */
	469	.name = "VP_IDE",
	470	.init_chipset = init_chipset_via82cxxx,
	471	.init_hwif = init_hwif_via82cxxx,
	472	.channels = 2,
	473	.autodma = NOAUTODMA,
	474	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
	475	.bootable = ON_BOARD
	476	},{ /* 1 */
	477	.name = "VP_IDE",
	478	.init_chipset = init_chipset_via82cxxx,
	479	.init_hwif = init_hwif_via82cxxx,
	480	.channels = 2,
	481	.autodma = AUTODMA,
	482	.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
	483	.bootable = ON_BOARD,
	484	}
1da177e4 LT	485	};
	486
	487	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	488	{
23a1b2a7 AC	489	struct pci_dev *isa = NULL;
	490	struct via_isa_bridge *via_config;
	491	/*
	492	* Find the ISA bridge and check we know what it is.
	493	*/
	494	via_config = via_config_find(&isa);
	495	pci_dev_put(isa);
	496	if (!via_config->id) {
	497	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	498	return -ENODEV;
	499	}
4f1d774a	500	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
1da177e4 LT	501	}
	502
	503	static struct pci_device_id via_pci_tbl[] = {
	504	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	505	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
4f1d774a	506	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1da177e4 LT	507	{ 0, },
	508	};
	509	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	510
	511	static struct pci_driver driver = {
	512	.name = "VIA_IDE",
	513	.id_table = via_pci_tbl,
	514	.probe = via_init_one,
	515	};
	516
82ab1eec	517	static int __init via_ide_init(void)
1da177e4 LT	518	{
	519	return ide_pci_register_driver(&driver);
	520	}
	521
	522	module_init(via_ide_init);
	523
	524	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	525	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	526	MODULE_LICENSE("GPL");