Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Version 3.38 | |
4 | * | |
5 | * VIA IDE driver for Linux. Supported southbridges: | |
6 | * | |
7 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
8 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 9 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
10 | * |
11 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
12 | * | |
13 | * Based on the work of: | |
14 | * Michel Aubry | |
15 | * Jeff Garzik | |
16 | * Andre Hedrick | |
17 | * | |
18 | * Documentation: | |
19 | * Obsolete device documentation publically available from via.com.tw | |
20 | * Current device documentation available under NDA only | |
21 | */ | |
22 | ||
23 | /* | |
24 | * This program is free software; you can redistribute it and/or modify it | |
25 | * under the terms of the GNU General Public License version 2 as published by | |
26 | * the Free Software Foundation. | |
27 | */ | |
28 | ||
1da177e4 LT |
29 | #include <linux/module.h> |
30 | #include <linux/kernel.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/blkdev.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/ide.h> | |
36 | #include <asm/io.h> | |
37 | ||
74a9d5f1 | 38 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
39 | #include <asm/processor.h> |
40 | #endif | |
41 | ||
42 | #include "ide-timing.h" | |
43 | ||
44 | #define DISPLAY_VIA_TIMINGS | |
45 | ||
46 | #define VIA_IDE_ENABLE 0x40 | |
47 | #define VIA_IDE_CONFIG 0x41 | |
48 | #define VIA_FIFO_CONFIG 0x43 | |
49 | #define VIA_MISC_1 0x44 | |
50 | #define VIA_MISC_2 0x45 | |
51 | #define VIA_MISC_3 0x46 | |
52 | #define VIA_DRIVE_TIMING 0x48 | |
53 | #define VIA_8BIT_TIMING 0x4e | |
54 | #define VIA_ADDRESS_SETUP 0x4c | |
55 | #define VIA_UDMA_TIMING 0x50 | |
56 | ||
57 | #define VIA_UDMA 0x007 | |
58 | #define VIA_UDMA_NONE 0x000 | |
59 | #define VIA_UDMA_33 0x001 | |
60 | #define VIA_UDMA_66 0x002 | |
61 | #define VIA_UDMA_100 0x003 | |
62 | #define VIA_UDMA_133 0x004 | |
63 | #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */ | |
64 | #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */ | |
65 | #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */ | |
66 | #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */ | |
67 | #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */ | |
68 | #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */ | |
69 | ||
70 | /* | |
71 | * VIA SouthBridge chips. | |
72 | */ | |
73 | ||
74 | static struct via_isa_bridge { | |
75 | char *name; | |
76 | u16 id; | |
77 | u8 rev_min; | |
78 | u8 rev_max; | |
79 | u16 flags; | |
80 | } via_isa_bridges[] = { | |
fb594d31 | 81 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
e0b874df | 82 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
4f1d774a | 83 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
ceef833b | 84 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
1da177e4 | 85 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
a7dec1e0 | 86 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
1da177e4 LT |
87 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
88 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
89 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
90 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
91 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, | |
92 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, | |
93 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, | |
94 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
95 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, | |
96 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
97 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
98 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, | |
99 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
100 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
101 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, | |
102 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, | |
103 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
104 | { NULL } | |
105 | }; | |
106 | ||
1da177e4 LT |
107 | static unsigned int via_clock; |
108 | static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" }; | |
109 | ||
7462cbff DD |
110 | struct via82cxxx_dev |
111 | { | |
112 | struct via_isa_bridge *via_config; | |
113 | unsigned int via_80w; | |
114 | }; | |
115 | ||
1da177e4 LT |
116 | /** |
117 | * via_set_speed - write timing registers | |
118 | * @dev: PCI device | |
119 | * @dn: device | |
120 | * @timing: IDE timing data to use | |
121 | * | |
122 | * via_set_speed writes timing values to the chipset registers | |
123 | */ | |
124 | ||
7462cbff | 125 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 126 | { |
7462cbff | 127 | struct pci_dev *dev = hwif->pci_dev; |
cd36beec | 128 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
129 | u8 t; |
130 | ||
7462cbff | 131 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 LT |
132 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
133 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
134 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); | |
135 | } | |
136 | ||
137 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
138 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
139 | ||
140 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
141 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
142 | ||
7462cbff | 143 | switch (vdev->via_config->flags & VIA_UDMA) { |
1da177e4 LT |
144 | case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; |
145 | case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
146 | case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
147 | case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
148 | default: return; | |
149 | } | |
150 | ||
151 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
152 | } | |
153 | ||
154 | /** | |
155 | * via_set_drive - configure transfer mode | |
156 | * @drive: Drive to set up | |
157 | * @speed: desired speed | |
158 | * | |
159 | * via_set_drive() computes timing values configures the drive and | |
160 | * the chipset to a desired transfer mode. It also can be called | |
161 | * by upper layers. | |
162 | */ | |
163 | ||
164 | static int via_set_drive(ide_drive_t *drive, u8 speed) | |
165 | { | |
166 | ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1); | |
cd36beec | 167 | struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev); |
1da177e4 LT |
168 | struct ide_timing t, p; |
169 | unsigned int T, UT; | |
170 | ||
171 | if (speed != XFER_PIO_SLOW) | |
172 | ide_config_drive_speed(drive, speed); | |
173 | ||
174 | T = 1000000000 / via_clock; | |
175 | ||
7462cbff | 176 | switch (vdev->via_config->flags & VIA_UDMA) { |
1da177e4 LT |
177 | case VIA_UDMA_33: UT = T; break; |
178 | case VIA_UDMA_66: UT = T/2; break; | |
179 | case VIA_UDMA_100: UT = T/3; break; | |
180 | case VIA_UDMA_133: UT = T/4; break; | |
181 | default: UT = T; | |
182 | } | |
183 | ||
184 | ide_timing_compute(drive, speed, &t, T, UT); | |
185 | ||
186 | if (peer->present) { | |
187 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
188 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
189 | } | |
190 | ||
7462cbff | 191 | via_set_speed(HWIF(drive), drive->dn, &t); |
1da177e4 LT |
192 | |
193 | if (!drive->init_speed) | |
194 | drive->init_speed = speed; | |
195 | drive->current_speed = speed; | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /** | |
201 | * via82cxxx_tune_drive - PIO setup | |
202 | * @drive: drive to set up | |
203 | * @pio: mode to use (255 for 'best possible') | |
204 | * | |
205 | * A callback from the upper layers for PIO-only tuning. | |
206 | */ | |
207 | ||
208 | static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio) | |
209 | { | |
210 | if (pio == 255) { | |
211 | via_set_drive(drive, | |
212 | ide_find_best_mode(drive, XFER_PIO | XFER_EPIO)); | |
213 | return; | |
214 | } | |
215 | ||
216 | via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5)); | |
217 | } | |
218 | ||
219 | /** | |
220 | * via82cxxx_ide_dma_check - set up for DMA if possible | |
221 | * @drive: IDE drive to set up | |
222 | * | |
223 | * Set up the drive for the highest supported speed considering the | |
224 | * driver, controller and cable | |
225 | */ | |
226 | ||
227 | static int via82cxxx_ide_dma_check (ide_drive_t *drive) | |
228 | { | |
7462cbff | 229 | ide_hwif_t *hwif = HWIF(drive); |
cd36beec | 230 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
7462cbff | 231 | u16 w80 = hwif->udma_four; |
1da177e4 LT |
232 | |
233 | u16 speed = ide_find_best_mode(drive, | |
234 | XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA | | |
7462cbff DD |
235 | (vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) | |
236 | (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) | | |
237 | (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) | | |
238 | (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0)); | |
1da177e4 LT |
239 | |
240 | via_set_drive(drive, speed); | |
241 | ||
242 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) | |
7462cbff DD |
243 | return hwif->ide_dma_on(drive); |
244 | return hwif->ide_dma_off_quietly(drive); | |
245 | } | |
246 | ||
247 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) | |
248 | { | |
249 | struct via_isa_bridge *via_config; | |
250 | u8 t; | |
251 | ||
252 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 253 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
254 | !!(via_config->flags & VIA_BAD_ID), |
255 | via_config->id, NULL))) { | |
256 | ||
257 | pci_read_config_byte(*isa, PCI_REVISION_ID, &t); | |
258 | if (t >= via_config->rev_min && | |
259 | t <= via_config->rev_max) | |
260 | break; | |
652aa162 | 261 | pci_dev_put(*isa); |
7462cbff DD |
262 | } |
263 | ||
264 | return via_config; | |
1da177e4 LT |
265 | } |
266 | ||
cd36beec BZ |
267 | /* |
268 | * Check and handle 80-wire cable presence | |
269 | */ | |
270 | static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u) | |
271 | { | |
272 | int i; | |
273 | ||
274 | switch (vdev->via_config->flags & VIA_UDMA) { | |
275 | case VIA_UDMA_66: | |
276 | for (i = 24; i >= 0; i -= 8) | |
277 | if (((u >> (i & 16)) & 8) && | |
278 | ((u >> i) & 0x20) && | |
279 | (((u >> i) & 7) < 2)) { | |
280 | /* | |
281 | * 2x PCI clock and | |
282 | * UDMA w/ < 3T/cycle | |
283 | */ | |
284 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
285 | } | |
286 | break; | |
287 | ||
288 | case VIA_UDMA_100: | |
289 | for (i = 24; i >= 0; i -= 8) | |
290 | if (((u >> i) & 0x10) || | |
291 | (((u >> i) & 0x20) && | |
292 | (((u >> i) & 7) < 4))) { | |
293 | /* BIOS 80-wire bit or | |
294 | * UDMA w/ < 60ns/cycle | |
295 | */ | |
296 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
297 | } | |
298 | break; | |
299 | ||
300 | case VIA_UDMA_133: | |
301 | for (i = 24; i >= 0; i -= 8) | |
302 | if (((u >> i) & 0x10) || | |
303 | (((u >> i) & 0x20) && | |
304 | (((u >> i) & 7) < 6))) { | |
305 | /* BIOS 80-wire bit or | |
306 | * UDMA w/ < 60ns/cycle | |
307 | */ | |
308 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
309 | } | |
310 | break; | |
311 | } | |
312 | } | |
313 | ||
1da177e4 LT |
314 | /** |
315 | * init_chipset_via82cxxx - initialization handler | |
316 | * @dev: PCI device | |
317 | * @name: Name of interface | |
318 | * | |
319 | * The initialization callback. Here we determine the IDE chip type | |
320 | * and initialize its drive independent registers. | |
321 | */ | |
322 | ||
f3718d3e | 323 | static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name) |
1da177e4 LT |
324 | { |
325 | struct pci_dev *isa = NULL; | |
cd36beec | 326 | struct via82cxxx_dev *vdev; |
7462cbff | 327 | struct via_isa_bridge *via_config; |
1da177e4 | 328 | u8 t, v; |
cd36beec BZ |
329 | u32 u; |
330 | ||
331 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); | |
332 | if (!vdev) { | |
333 | printk(KERN_ERR "VP_IDE: out of memory :(\n"); | |
334 | return -ENOMEM; | |
335 | } | |
336 | pci_set_drvdata(dev, vdev); | |
1da177e4 LT |
337 | |
338 | /* | |
339 | * Find the ISA bridge to see how good the IDE is. | |
340 | */ | |
cd36beec | 341 | vdev->via_config = via_config = via_config_find(&isa); |
23a1b2a7 AC |
342 | |
343 | /* We checked this earlier so if it fails here deeep badness | |
344 | is involved */ | |
345 | ||
346 | BUG_ON(!via_config->id); | |
1da177e4 LT |
347 | |
348 | /* | |
cd36beec | 349 | * Detect cable and configure Clk66 |
1da177e4 | 350 | */ |
cd36beec BZ |
351 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
352 | ||
353 | via_cable_detect(vdev, u); | |
1da177e4 | 354 | |
7462cbff DD |
355 | if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) { |
356 | /* Enable Clk66 */ | |
7462cbff DD |
357 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
358 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 359 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
360 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
361 | } | |
362 | ||
363 | /* | |
364 | * Check whether interfaces are enabled. | |
365 | */ | |
366 | ||
367 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
368 | ||
369 | /* | |
370 | * Set up FIFO sizes and thresholds. | |
371 | */ | |
372 | ||
373 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
374 | ||
375 | /* Disable PREQ# till DDACK# */ | |
376 | if (via_config->flags & VIA_BAD_PREQ) { | |
377 | /* Would crash on 586b rev 41 */ | |
378 | t &= 0x7f; | |
379 | } | |
380 | ||
381 | /* Fix FIFO split between channels */ | |
382 | if (via_config->flags & VIA_SET_FIFO) { | |
383 | t &= (t & 0x9f); | |
384 | switch (v & 3) { | |
385 | case 2: t |= 0x00; break; /* 16 on primary */ | |
386 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
387 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
388 | } | |
389 | } | |
390 | ||
391 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
392 | ||
393 | /* | |
394 | * Determine system bus clock. | |
395 | */ | |
396 | ||
397 | via_clock = system_bus_clock() * 1000; | |
398 | ||
399 | switch (via_clock) { | |
400 | case 33000: via_clock = 33333; break; | |
401 | case 37000: via_clock = 37500; break; | |
402 | case 41000: via_clock = 41666; break; | |
403 | } | |
404 | ||
405 | if (via_clock < 20000 || via_clock > 50000) { | |
406 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
407 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
408 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
409 | "to assume 80-wire cable.\n"); | |
410 | via_clock = 33333; | |
411 | } | |
412 | ||
413 | /* | |
414 | * Print the boot message. | |
415 | */ | |
416 | ||
417 | pci_read_config_byte(isa, PCI_REVISION_ID, &t); | |
418 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s " | |
419 | "controller on pci%s\n", | |
420 | via_config->name, t, | |
421 | via_dma[via_config->flags & VIA_UDMA], | |
422 | pci_name(dev)); | |
423 | ||
652aa162 | 424 | pci_dev_put(isa); |
1da177e4 LT |
425 | return 0; |
426 | } | |
427 | ||
f3718d3e | 428 | static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif) |
1da177e4 | 429 | { |
cd36beec | 430 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
431 | int i; |
432 | ||
433 | hwif->autodma = 0; | |
434 | ||
435 | hwif->tuneproc = &via82cxxx_tune_drive; | |
436 | hwif->speedproc = &via_set_drive; | |
437 | ||
438 | ||
74a9d5f1 | 439 | #ifdef CONFIG_PPC_CHRP |
e8222502 | 440 | if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) { |
1da177e4 LT |
441 | hwif->irq = hwif->channel ? 15 : 14; |
442 | } | |
443 | #endif | |
444 | ||
445 | for (i = 0; i < 2; i++) { | |
446 | hwif->drives[i].io_32bit = 1; | |
7462cbff | 447 | hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1; |
1da177e4 LT |
448 | hwif->drives[i].autotune = 1; |
449 | hwif->drives[i].dn = hwif->channel * 2 + i; | |
450 | } | |
451 | ||
452 | if (!hwif->dma_base) | |
453 | return; | |
454 | ||
455 | hwif->atapi_dma = 1; | |
456 | hwif->ultra_mask = 0x7f; | |
457 | hwif->mwdma_mask = 0x07; | |
458 | hwif->swdma_mask = 0x07; | |
459 | ||
460 | if (!hwif->udma_four) | |
7462cbff | 461 | hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1; |
1da177e4 LT |
462 | hwif->ide_dma_check = &via82cxxx_ide_dma_check; |
463 | if (!noautodma) | |
464 | hwif->autodma = 1; | |
465 | hwif->drives[0].autodma = hwif->autodma; | |
466 | hwif->drives[1].autodma = hwif->autodma; | |
467 | } | |
468 | ||
4f1d774a MK |
469 | static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = { |
470 | { /* 0 */ | |
471 | .name = "VP_IDE", | |
472 | .init_chipset = init_chipset_via82cxxx, | |
473 | .init_hwif = init_hwif_via82cxxx, | |
474 | .channels = 2, | |
475 | .autodma = NOAUTODMA, | |
476 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, | |
477 | .bootable = ON_BOARD | |
478 | },{ /* 1 */ | |
479 | .name = "VP_IDE", | |
480 | .init_chipset = init_chipset_via82cxxx, | |
481 | .init_hwif = init_hwif_via82cxxx, | |
482 | .channels = 2, | |
483 | .autodma = AUTODMA, | |
484 | .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, | |
485 | .bootable = ON_BOARD, | |
486 | } | |
1da177e4 LT |
487 | }; |
488 | ||
489 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
490 | { | |
23a1b2a7 AC |
491 | struct pci_dev *isa = NULL; |
492 | struct via_isa_bridge *via_config; | |
493 | /* | |
494 | * Find the ISA bridge and check we know what it is. | |
495 | */ | |
496 | via_config = via_config_find(&isa); | |
497 | pci_dev_put(isa); | |
498 | if (!via_config->id) { | |
499 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
500 | return -ENODEV; | |
501 | } | |
4f1d774a | 502 | return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]); |
1da177e4 LT |
503 | } |
504 | ||
505 | static struct pci_device_id via_pci_tbl[] = { | |
506 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
507 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
4f1d774a | 508 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
e0b874df | 509 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1da177e4 LT |
510 | { 0, }, |
511 | }; | |
512 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
513 | ||
514 | static struct pci_driver driver = { | |
515 | .name = "VIA_IDE", | |
516 | .id_table = via_pci_tbl, | |
517 | .probe = via_init_one, | |
518 | }; | |
519 | ||
82ab1eec | 520 | static int __init via_ide_init(void) |
1da177e4 LT |
521 | { |
522 | return ide_pci_register_driver(&driver); | |
523 | } | |
524 | ||
525 | module_init(via_ide_init); | |
526 | ||
527 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
528 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
529 | MODULE_LICENSE("GPL"); |