[deliverable/linux.git] / drivers / ide / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "pdc202xx_old"

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (ata_id_iordy_disable(drive->id))
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_quirkproc(ide_drive_t *drive)
{
	const char **list, *m = (char *)&drive->id[ATA_ID_PROD];

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(m, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdc202xx_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= HWIF(drive);
		struct request *rq	= hwif->rq;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return ide_dma_end(drive);
}

static int pdc202xx_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->extra_base - 16;
	u8 dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->extra_base - 16;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_timeout(drive);
}

static unsigned int init_chipset_pdc202xx(struct pci_dev *dev)
{
	unsigned long dmabase = pci_resource_start(dev, 4);
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (dmabase == 0)
		goto out;

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", pci_name(dev),
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			pci_name(dev), udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
out:
	return dev->irq;
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s %s: PCI config space interrupt "
				"mirror fixed\n", name, pci_name(dev));
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
	.resetproc		= pdc202xx_reset,
	.cable_detect		= pdc2026x_cable_detect,
};

static const struct ide_dma_ops pdc20246_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= ide_dma_end,
	.dma_test_irq		= pdc202xx_dma_test_irq,
	.dma_lost_irq		= pdc202xx_dma_lost_irq,
	.dma_timeout		= pdc202xx_dma_timeout,
};

static const struct ide_dma_ops pdc2026x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= pdc202xx_dma_start,
	.dma_end		= pdc202xx_dma_end,
	.dma_test_irq		= pdc202xx_dma_test_irq,
	.dma_lost_irq		= pdc202xx_dma_lost_irq,
	.dma_timeout		= pdc202xx_dma_timeout,
};

#define DECLARE_PDC2026X_DEV(udma, sectors) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdc202xx, \
		.port_ops	= &pdc2026x_port_ops, \
		.dma_ops	= &pdc2026x_dma_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
		.max_sectors	= sectors, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0: PDC20246 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.dma_ops	= &pdc20246_dma_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1: PDC2026{2,3} */
	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 2)
		pdc202ata4_fixup_irq(dev, d->name);

	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO DRV_NAME " %s: skipping Promise "
				"PDC20265 attached to I2O RAID controller\n",
				pci_name(dev));
			return -ENODEV;
		}
	}

	return ide_pci_init_one(dev, d, NULL);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver pdc202xx_pci_driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_ide_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

module_init(pdc202xx_ide_init);
module_exit(pdc202xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	3	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/ide.h>
	19
	20	#include <asm/io.h>
1da177e4	21
ced3ec8a BZ	22	#define DRV_NAME "pdc202xx_old"
ced3ec8a BZ	23
1da177e4 LT	24	#define PDC202XX_DEBUG_DRIVE_INFO 0
	25
	26	static const char *pdc_quirk_drives[] = {
	27	"QUANTUM FIREBALLlct08 08",
	28	"QUANTUM FIREBALLP KA6.4",
	29	"QUANTUM FIREBALLP KA9.1",
	30	"QUANTUM FIREBALLP LM20.4",
	31	"QUANTUM FIREBALLP KX13.6",
	32	"QUANTUM FIREBALLP KX20.5",
	33	"QUANTUM FIREBALLP KX27.3",
	34	"QUANTUM FIREBALLP LM20.5",
	35	NULL
	36	};
	37
4fce3164	38	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	39
88b2b32b	40	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	41	{
1da177e4 LT	42	ide_hwif_t *hwif = HWIF(drive);
36501650	43	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	44	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	45
4fce3164	46	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	47	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	48
4fce3164 BZ	49	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	50	u32 drive_conf = 0;
1da177e4	51	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	52	#endif
1da177e4	53
4fce3164 BZ	54	/*
	55	* TODO: do this once per channel
	56	*/
	57	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	58	pdc_old_disable_66MHz_clock(hwif);
1da177e4	59
4fce3164 BZ	60	pci_read_config_byte(dev, drive_pci, &AP);
	61	pci_read_config_byte(dev, drive_pci + 1, &BP);
	62	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	63
1da177e4 LT	64	switch(speed) {
1da177e4 LT	65	case XFER_UDMA_5:
	66	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	67	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	68	case XFER_UDMA_3:
	69	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	70	case XFER_UDMA_0:
	71	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	72	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	73	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	74	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	75	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	76	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	77	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	78	case XFER_PIO_0:
	79	default: TA = 0x09; TB = 0x13; break;
	80	}
	81
	82	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	83	/*
	84	* preserve SYNC_INT / ERDDY_EN bits while clearing
	85	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	86	*/
	87	AP &= ~0x3f;
48fb2688	88	if (ata_id_iordy_disable(drive->id))
4fce3164 BZ	89	AP \|= 0x20; /* set IORDY_EN bit */
	90	if (drive->media == ide_disk)
	91	AP \|= 0x10; /* set Prefetch_EN bit */
	92	/* clear PB[4:0] bits of register B */
	93	BP &= ~0x1f;
	94	pci_write_config_byte(dev, drive_pci, AP \| TA);
	95	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	96	} else {
4fce3164 BZ	97	/* clear MB[2:0] bits of register B */
	98	BP &= ~0xe0;
	99	/* clear MC[3:0] bits of register C */
	100	CP &= ~0x0f;
	101	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	102	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	103	}
	104
	105	#if PDC202XX_DEBUG_DRIVE_INFO
	106	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	107	drive->name, ide_xfer_verbose(speed),
	108	drive->dn, drive_conf);
4fce3164	109	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	110	printk("0x%08x\n", drive_conf);
4fce3164	111	#endif
1da177e4 LT	112	}
1da177e4 LT	113
26bcb879	114	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	115	{
88b2b32b	116	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	117	}
1da177e4 LT	118
f454cbe8	119	static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	120	{
36501650	121	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	122	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	123
36501650	124	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	125
49521f97 BZ	126	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	127	}
	128
	129	/*
	130	* Set the control register to use the 66MHz system
	131	* clock for UDMA 3/4/5 mode operation when necessary.
	132	*
4fce3164 BZ	133	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	134	*
1da177e4 LT	135	* It may also be possible to leave the 66MHz clock on
	136	* and readjust the timing parameters.
	137	*/
	138	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	139	{
1c029fd6	140	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	141	u8 clock = inb(clock_reg);
1da177e4	142
0ecdca26	143	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	144	}
	145
	146	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	147	{
1c029fd6	148	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	149	u8 clock = inb(clock_reg);
1da177e4	150
0ecdca26	151	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	152	}
1da177e4 LT	153
f01393e4	154	static void pdc202xx_quirkproc(ide_drive_t *drive)
1da177e4	155	{
4dde4492	156	const char *list, m = (char *)&drive->id[ATA_ID_PROD];
d24ec426 SS	157
d24ec426 SS	158	for (list = pdc_quirk_drives; *list != NULL; list++)
4dde4492	159	if (strstr(m, *list) != NULL) {
f01393e4 BZ	160	drive->quirk_list = 2;
	161	return;
	162	}
	163
	164	drive->quirk_list = 0;
1da177e4 LT	165	}
1da177e4 LT	166
5e37bdc0	167	static void pdc202xx_dma_start(ide_drive_t *drive)
1da177e4 LT	168	{
	169	if (drive->current_speed > XFER_UDMA_2)
	170	pdc_old_enable_66MHz_clock(drive->hwif);
97100fc8	171	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
1da177e4	172	ide_hwif_t *hwif = HWIF(drive);
b65fac32	173	struct request *rq = hwif->rq;
1c029fd6	174	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	175	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	176	u32 word_count = 0;
0ecdca26	177	u8 clock = inb(high_16 + 0x11);
1da177e4	178
0ecdca26	179	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	180	word_count = (rq->nr_sectors << 8);
	181	word_count = (rq_data_dir(rq) == READ) ?
	182	word_count \| 0x05000000 :
	183	word_count \| 0x06000000;
0ecdca26	184	outl(word_count, atapi_reg);
1da177e4 LT	185	}
	186	ide_dma_start(drive);
	187	}
	188
5e37bdc0	189	static int pdc202xx_dma_end(ide_drive_t *drive)
1da177e4	190	{
97100fc8	191	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
1da177e4	192	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	193	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	194	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	195	u8 clock = 0;
	196
0ecdca26 BZ	197	outl(0, atapi_reg); /* zero out extra */
	198	clock = inb(high_16 + 0x11);
	199	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	200	}
	201	if (drive->current_speed > XFER_UDMA_2)
	202	pdc_old_disable_66MHz_clock(drive->hwif);
653bcf52	203	return ide_dma_end(drive);
1da177e4 LT	204	}
1da177e4 LT	205
5e37bdc0	206	static int pdc202xx_dma_test_irq(ide_drive_t *drive)
1da177e4 LT	207	{
1da177e4 LT	208	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	209	unsigned long high_16 = hwif->extra_base - 16;
cab7f8ed	210	u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
0ecdca26	211	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	212
	213	if (hwif->channel) {
	214	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	215	if ((sc1d & 0x50) == 0x50)
	216	goto somebody_else;
	217	else if ((sc1d & 0x40) == 0x40)
	218	return (dma_stat & 4) == 4;
	219	} else {
	220	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	221	if ((sc1d & 0x05) == 0x05)
	222	goto somebody_else;
	223	else if ((sc1d & 0x04) == 0x04)
	224	return (dma_stat & 4) == 4;
	225	}
	226	somebody_else:
	227	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	228	}
	229
1da177e4 LT	230	static void pdc202xx_reset_host (ide_hwif_t *hwif)
1da177e4 LT	231	{
1c029fd6	232	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26	233	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	234
0ecdca26	235	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	236	mdelay(100);
0ecdca26	237	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	238	mdelay(2000); /* 2 seconds ?! */
	239
	240	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	241	hwif->channel ? "Secondary" : "Primary");
	242	}
	243
	244	static void pdc202xx_reset (ide_drive_t *drive)
	245	{
	246	ide_hwif_t *hwif = HWIF(drive);
	247	ide_hwif_t *mate = hwif->mate;
26bcb879	248
1da177e4 LT	249	pdc202xx_reset_host(hwif);
1da177e4 LT	250	pdc202xx_reset_host(mate);
26bcb879 BZ	251
26bcb879 BZ	252	ide_set_max_pio(drive);
1da177e4 LT	253	}
1da177e4 LT	254
ac95beed BZ	255	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
	256	{
	257	pdc202xx_reset(drive);
	258	ide_dma_lost_irq(drive);
	259	}
	260
	261	static void pdc202xx_dma_timeout(ide_drive_t *drive)
	262	{
	263	pdc202xx_reset(drive);
	264	ide_dma_timeout(drive);
	265	}
	266
feb22b7f	267	static unsigned int init_chipset_pdc202xx(struct pci_dev *dev)
1da177e4	268	{
73369d2a	269	unsigned long dmabase = pci_resource_start(dev, 4);
1da177e4 LT	270	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
1da177e4 LT	271
73369d2a BZ	272	if (dmabase == 0)
73369d2a BZ	273	goto out;
1da177e4	274
0ecdca26 BZ	275	udma_speed_flag = inb(dmabase \| 0x1f);
	276	primary_mode = inb(dmabase \| 0x1a);
	277	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	278	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
1da177e4 LT	279	"Primary %s Mode " \
5e59c236	280	"Secondary %s Mode.\n", pci_name(dev),
1da177e4 LT	281	(udma_speed_flag & 1) ? "EN" : "DIS",
	282	(primary_mode & 1) ? "MASTER" : "PCI",
	283	(secondary_mode & 1) ? "MASTER" : "PCI" );
	284
1da177e4 LT	285	if (!(udma_speed_flag & 1)) {
1da177e4 LT	286	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
5e59c236	287	pci_name(dev), udma_speed_flag,
1da177e4	288	(udma_speed_flag\|1));
0ecdca26 BZ	289	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	290	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	291	}
73369d2a BZ	292	out:
73369d2a BZ	293	return dev->irq;
1da177e4 LT	294	}
1da177e4 LT	295
97f84baa BZ	296	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	297	const char *name)
1da177e4 LT	298	{
	299	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	300	u8 irq = 0, irq2 = 0;
	301	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	302	/* 0xbc */
	303	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	304	if (irq != irq2) {
	305	pci_write_config_byte(dev,
	306	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
28cfd8af BZ	307	printk(KERN_INFO "%s %s: PCI config space interrupt "
28cfd8af BZ	308	"mirror fixed\n", name, pci_name(dev));
1da177e4 LT	309	}
1da177e4 LT	310	}
1da177e4 LT	311	}
1da177e4 LT	312
4db90a14 BZ	313	#define IDE_HFLAGS_PDC202XX \
4db90a14 BZ	314	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
4db90a14 BZ	315	IDE_HFLAG_OFF_BOARD)
4db90a14 BZ	316
ac95beed BZ	317	static const struct ide_port_ops pdc20246_port_ops = {
	318	.set_pio_mode = pdc202xx_set_pio_mode,
	319	.set_dma_mode = pdc202xx_set_mode,
	320	.quirkproc = pdc202xx_quirkproc,
	321	};
	322
	323	static const struct ide_port_ops pdc2026x_port_ops = {
	324	.set_pio_mode = pdc202xx_set_pio_mode,
	325	.set_dma_mode = pdc202xx_set_mode,
	326	.quirkproc = pdc202xx_quirkproc,
	327	.resetproc = pdc202xx_reset,
	328	.cable_detect = pdc2026x_cable_detect,
	329	};
	330
f37afdac BZ	331	static const struct ide_dma_ops pdc20246_dma_ops = {
	332	.dma_host_set = ide_dma_host_set,
	333	.dma_setup = ide_dma_setup,
	334	.dma_exec_cmd = ide_dma_exec_cmd,
	335	.dma_start = ide_dma_start,
653bcf52	336	.dma_end = ide_dma_end,
5e37bdc0 BZ	337	.dma_test_irq = pdc202xx_dma_test_irq,
	338	.dma_lost_irq = pdc202xx_dma_lost_irq,
	339	.dma_timeout = pdc202xx_dma_timeout,
	340	};
	341
f37afdac BZ	342	static const struct ide_dma_ops pdc2026x_dma_ops = {
	343	.dma_host_set = ide_dma_host_set,
	344	.dma_setup = ide_dma_setup,
	345	.dma_exec_cmd = ide_dma_exec_cmd,
5e37bdc0 BZ	346	.dma_start = pdc202xx_dma_start,
	347	.dma_end = pdc202xx_dma_end,
	348	.dma_test_irq = pdc202xx_dma_test_irq,
	349	.dma_lost_irq = pdc202xx_dma_lost_irq,
	350	.dma_timeout = pdc202xx_dma_timeout,
	351	};
	352
6b492496	353	#define DECLARE_PDC2026X_DEV(udma, sectors) \
5ef8cb5d	354	{ \
ced3ec8a	355	.name = DRV_NAME, \
5ef8cb5d	356	.init_chipset = init_chipset_pdc202xx, \
ac95beed	357	.port_ops = &pdc2026x_port_ops, \
5e37bdc0	358	.dma_ops = &pdc2026x_dma_ops, \
6b492496	359	.host_flags = IDE_HFLAGS_PDC202XX, \
5ef8cb5d BZ	360	.pio_mask = ATA_PIO4, \
	361	.mwdma_mask = ATA_MWDMA2, \
	362	.udma_mask = udma, \
6b492496	363	.max_sectors = sectors, \
5ef8cb5d BZ	364	}
5ef8cb5d BZ	365
85620436	366	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
ced3ec8a BZ	367	{ /* 0: PDC20246 */
ced3ec8a BZ	368	.name = DRV_NAME,
1da177e4	369	.init_chipset = init_chipset_pdc202xx,
ac95beed	370	.port_ops = &pdc20246_port_ops,
5e37bdc0	371	.dma_ops = &pdc20246_dma_ops,
4db90a14	372	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	373	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	374	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	375	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	376	},
5ef8cb5d BZ	377
ced3ec8a BZ	378	/* 1: PDC2026{2,3} */
ced3ec8a BZ	379	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
6b492496 BZ	380	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
6b492496 BZ	381	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
1da177e4 LT	382	};
	383
	384	/**
	385	* pdc202xx_init_one - called when a PDC202xx is found
	386	* @dev: the pdc202xx device
	387	* @id: the matching pci id
	388	*
	389	* Called when the PCI registration layer (or the IDE initialization)
	390	* finds a device matching our IDE device tables.
	391	*/
	392
	393	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	394	{
85620436	395	const struct ide_port_info *d;
97f84baa BZ	396	u8 idx = id->driver_data;
	397
	398	d = &pdc202xx_chipsets[idx];
	399
ced3ec8a	400	if (idx < 2)
97f84baa BZ	401	pdc202ata4_fixup_irq(dev, d->name);
97f84baa BZ	402
ced3ec8a	403	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
97f84baa	404	struct pci_dev *bridge = dev->bus->self;
1da177e4	405
97f84baa BZ	406	if (bridge &&
	407	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	408	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	409	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	410	printk(KERN_INFO DRV_NAME " %s: skipping Promise "
28cfd8af BZ	411	"PDC20265 attached to I2O RAID controller\n",
28cfd8af BZ	412	pci_name(dev));
97f84baa BZ	413	return -ENODEV;
	414	}
	415	}
	416
6cdf6eb3	417	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	418	}
1da177e4 LT	419
9cbcc5e3 BZ	420	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	421	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	422	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
ced3ec8a BZ	423	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	424	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	425	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
1da177e4 LT	426	{ 0, },
	427	};
	428	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	429
a9ab09e2	430	static struct pci_driver pdc202xx_pci_driver = {
1da177e4 LT	431	.name = "Promise_Old_IDE",
	432	.id_table = pdc202xx_pci_tbl,
	433	.probe = pdc202xx_init_one,
574a1c24	434	.remove = ide_pci_remove,
feb22b7f BZ	435	.suspend = ide_pci_suspend,
feb22b7f BZ	436	.resume = ide_pci_resume,
1da177e4 LT	437	};
1da177e4 LT	438
82ab1eec	439	static int __init pdc202xx_ide_init(void)
1da177e4	440	{
a9ab09e2	441	return ide_pci_register_driver(&pdc202xx_pci_driver);
1da177e4 LT	442	}
1da177e4 LT	443
574a1c24 BZ	444	static void __exit pdc202xx_ide_exit(void)
574a1c24 BZ	445	{
a9ab09e2	446	pci_unregister_driver(&pdc202xx_pci_driver);
574a1c24 BZ	447	}
574a1c24 BZ	448
1da177e4	449	module_init(pdc202xx_ide_init);
574a1c24	450	module_exit(pdc202xx_ide_exit);
1da177e4 LT	451
	452	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	453	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	454	MODULE_LICENSE("GPL");