[deliverable/linux.git] / drivers / ide / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007, 2009	MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "pdc202xx_old"

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static int pdc202xx_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long high_16	= pci_resource_start(dev, 4);
	u8 sc1d			= inb(high_16 + 0x1d);

	if (hwif->channel) {
		/*
		 * bit 7: error, bit 6: interrupting,
		 * bit 5: FIFO full, bit 4: FIFO empty
		 */
		return ((sc1d & 0x50) == 0x40) ? 1 : 0;
	} else	{
		/*
		 * bit 3: error, bit 2: interrupting,
		 * bit 1: FIFO full, bit 0: FIFO empty
		 */
		return ((sc1d & 0x05) == 0x04) ? 1 : 0;
	}
}

static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		struct request *rq	= hwif->rq;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (blk_rq_sectors(rq) << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return ide_dma_end(drive);
}

static int init_chipset_pdc202xx(struct pci_dev *dev)
{
	unsigned long dmabase = pci_resource_start(dev, 4);
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (dmabase == 0)
		goto out;

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", pci_name(dev),
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			pci_name(dev), udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
out:
	return 0;
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s %s: PCI config space interrupt "
				"mirror fixed\n", name, pci_name(dev));
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.test_irq		= pdc202xx_test_irq,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.cable_detect		= pdc2026x_cable_detect,
};

static const struct ide_dma_ops pdc2026x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= pdc202xx_dma_start,
	.dma_end		= pdc202xx_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

#define DECLARE_PDC2026X_DEV(udma, sectors) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdc202xx, \
		.port_ops	= &pdc2026x_port_ops, \
		.dma_ops	= &pdc2026x_dma_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
		.max_sectors	= sectors, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0: PDC20246 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.dma_ops	= &sff_dma_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1: PDC2026{2,3} */
	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 2)
		pdc202ata4_fixup_irq(dev, d->name);

	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO DRV_NAME " %s: skipping Promise "
				"PDC20265 attached to I2O RAID controller\n",
				pci_name(dev));
			return -ENODEV;
		}
	}

	return ide_pci_init_one(dev, d, NULL);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver pdc202xx_pci_driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_ide_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

module_init(pdc202xx_ide_init);
module_exit(pdc202xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
669165da	3	* Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4fce3164	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/ide.h>
	19
	20	#include <asm/io.h>
1da177e4	21
ced3ec8a BZ	22	#define DRV_NAME "pdc202xx_old"
ced3ec8a BZ	23
4fce3164	24	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	25
88b2b32b	26	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4	27	{
898ec223	28	ide_hwif_t *hwif = drive->hwif;
36501650	29	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	30	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	31
4fce3164	32	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	33	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	34
4fce3164 BZ	35	/*
	36	* TODO: do this once per channel
	37	*/
	38	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	39	pdc_old_disable_66MHz_clock(hwif);
1da177e4	40
4fce3164 BZ	41	pci_read_config_byte(dev, drive_pci, &AP);
	42	pci_read_config_byte(dev, drive_pci + 1, &BP);
	43	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	44
1da177e4 LT	45	switch(speed) {
1da177e4 LT	46	case XFER_UDMA_5:
	47	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	48	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	49	case XFER_UDMA_3:
	50	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	51	case XFER_UDMA_0:
	52	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	53	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	54	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	55	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	56	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	57	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	58	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	59	case XFER_PIO_0:
	60	default: TA = 0x09; TB = 0x13; break;
	61	}
	62
	63	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	64	/*
	65	* preserve SYNC_INT / ERDDY_EN bits while clearing
	66	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	67	*/
	68	AP &= ~0x3f;
c9ef59ff	69	if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
4fce3164 BZ	70	AP \|= 0x20; /* set IORDY_EN bit */
	71	if (drive->media == ide_disk)
	72	AP \|= 0x10; /* set Prefetch_EN bit */
	73	/* clear PB[4:0] bits of register B */
	74	BP &= ~0x1f;
	75	pci_write_config_byte(dev, drive_pci, AP \| TA);
	76	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	77	} else {
4fce3164 BZ	78	/* clear MB[2:0] bits of register B */
	79	BP &= ~0xe0;
	80	/* clear MC[3:0] bits of register C */
	81	CP &= ~0x0f;
	82	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	83	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4	84	}
1da177e4 LT	85	}
1da177e4 LT	86
26bcb879	87	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	88	{
88b2b32b	89	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	90	}
1da177e4 LT	91
e0321fbe SS	92	static int pdc202xx_test_irq(ide_hwif_t *hwif)
	93	{
	94	struct pci_dev *dev = to_pci_dev(hwif->dev);
	95	unsigned long high_16 = pci_resource_start(dev, 4);
	96	u8 sc1d = inb(high_16 + 0x1d);
	97
	98	if (hwif->channel) {
	99	/*
	100	* bit 7: error, bit 6: interrupting,
	101	* bit 5: FIFO full, bit 4: FIFO empty
	102	*/
	103	return ((sc1d & 0x50) == 0x40) ? 1 : 0;
	104	} else {
	105	/*
	106	* bit 3: error, bit 2: interrupting,
	107	* bit 1: FIFO full, bit 0: FIFO empty
	108	*/
	109	return ((sc1d & 0x05) == 0x04) ? 1 : 0;
	110	}
	111	}
	112
f454cbe8	113	static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	114	{
36501650	115	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	116	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	117
36501650	118	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	119
49521f97 BZ	120	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	121	}
	122
	123	/*
	124	* Set the control register to use the 66MHz system
	125	* clock for UDMA 3/4/5 mode operation when necessary.
	126	*
4fce3164 BZ	127	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	128	*
1da177e4 LT	129	* It may also be possible to leave the 66MHz clock on
	130	* and readjust the timing parameters.
	131	*/
	132	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	133	{
1c029fd6	134	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	135	u8 clock = inb(clock_reg);
1da177e4	136
0ecdca26	137	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	138	}
	139
	140	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	141	{
1c029fd6	142	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	143	u8 clock = inb(clock_reg);
1da177e4	144
0ecdca26	145	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	146	}
1da177e4 LT	147
5e37bdc0	148	static void pdc202xx_dma_start(ide_drive_t *drive)
1da177e4 LT	149	{
	150	if (drive->current_speed > XFER_UDMA_2)
	151	pdc_old_enable_66MHz_clock(drive->hwif);
97100fc8	152	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	153	ide_hwif_t *hwif = drive->hwif;
b65fac32	154	struct request *rq = hwif->rq;
1c029fd6	155	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	156	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	157	u32 word_count = 0;
0ecdca26	158	u8 clock = inb(high_16 + 0x11);
1da177e4	159
0ecdca26	160	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
9780e2dd	161	word_count = (blk_rq_sectors(rq) << 8);
1da177e4 LT	162	word_count = (rq_data_dir(rq) == READ) ?
	163	word_count \| 0x05000000 :
	164	word_count \| 0x06000000;
0ecdca26	165	outl(word_count, atapi_reg);
1da177e4 LT	166	}
	167	ide_dma_start(drive);
	168	}
	169
5e37bdc0	170	static int pdc202xx_dma_end(ide_drive_t *drive)
1da177e4	171	{
97100fc8	172	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	173	ide_hwif_t *hwif = drive->hwif;
1c029fd6	174	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	175	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	176	u8 clock = 0;
	177
0ecdca26 BZ	178	outl(0, atapi_reg); /* zero out extra */
	179	clock = inb(high_16 + 0x11);
	180	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	181	}
	182	if (drive->current_speed > XFER_UDMA_2)
	183	pdc_old_disable_66MHz_clock(drive->hwif);
653bcf52	184	return ide_dma_end(drive);
1da177e4 LT	185	}
1da177e4 LT	186
2ed0ef54	187	static int init_chipset_pdc202xx(struct pci_dev *dev)
1da177e4	188	{
73369d2a	189	unsigned long dmabase = pci_resource_start(dev, 4);
1da177e4 LT	190	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
1da177e4 LT	191
73369d2a BZ	192	if (dmabase == 0)
73369d2a BZ	193	goto out;
1da177e4	194
0ecdca26 BZ	195	udma_speed_flag = inb(dmabase \| 0x1f);
	196	primary_mode = inb(dmabase \| 0x1a);
	197	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	198	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
1da177e4 LT	199	"Primary %s Mode " \
5e59c236	200	"Secondary %s Mode.\n", pci_name(dev),
1da177e4 LT	201	(udma_speed_flag & 1) ? "EN" : "DIS",
	202	(primary_mode & 1) ? "MASTER" : "PCI",
	203	(secondary_mode & 1) ? "MASTER" : "PCI" );
	204
1da177e4 LT	205	if (!(udma_speed_flag & 1)) {
1da177e4 LT	206	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
5e59c236	207	pci_name(dev), udma_speed_flag,
1da177e4	208	(udma_speed_flag\|1));
0ecdca26 BZ	209	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	210	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	211	}
73369d2a	212	out:
2ed0ef54	213	return 0;
1da177e4 LT	214	}
1da177e4 LT	215
97f84baa BZ	216	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	217	const char *name)
1da177e4 LT	218	{
	219	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	220	u8 irq = 0, irq2 = 0;
	221	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	222	/* 0xbc */
	223	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	224	if (irq != irq2) {
	225	pci_write_config_byte(dev,
	226	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
28cfd8af BZ	227	printk(KERN_INFO "%s %s: PCI config space interrupt "
28cfd8af BZ	228	"mirror fixed\n", name, pci_name(dev));
1da177e4 LT	229	}
1da177e4 LT	230	}
1da177e4 LT	231	}
1da177e4 LT	232
4db90a14 BZ	233	#define IDE_HFLAGS_PDC202XX \
4db90a14 BZ	234	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
4db90a14 BZ	235	IDE_HFLAG_OFF_BOARD)
4db90a14 BZ	236
ac95beed BZ	237	static const struct ide_port_ops pdc20246_port_ops = {
	238	.set_pio_mode = pdc202xx_set_pio_mode,
	239	.set_dma_mode = pdc202xx_set_mode,
e0321fbe	240	.test_irq = pdc202xx_test_irq,
ac95beed BZ	241	};
	242
	243	static const struct ide_port_ops pdc2026x_port_ops = {
	244	.set_pio_mode = pdc202xx_set_pio_mode,
	245	.set_dma_mode = pdc202xx_set_mode,
ac95beed BZ	246	.cable_detect = pdc2026x_cable_detect,
	247	};
	248
f37afdac BZ	249	static const struct ide_dma_ops pdc2026x_dma_ops = {
	250	.dma_host_set = ide_dma_host_set,
	251	.dma_setup = ide_dma_setup,
5e37bdc0 BZ	252	.dma_start = pdc202xx_dma_start,
5e37bdc0 BZ	253	.dma_end = pdc202xx_dma_end,
72b9304f	254	.dma_test_irq = ide_dma_test_irq,
1221e241	255	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	256	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	257	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	258	};
5e37bdc0 BZ	259
6b492496	260	#define DECLARE_PDC2026X_DEV(udma, sectors) \
5ef8cb5d	261	{ \
ced3ec8a	262	.name = DRV_NAME, \
5ef8cb5d	263	.init_chipset = init_chipset_pdc202xx, \
ac95beed	264	.port_ops = &pdc2026x_port_ops, \
5e37bdc0	265	.dma_ops = &pdc2026x_dma_ops, \
6b492496	266	.host_flags = IDE_HFLAGS_PDC202XX, \
5ef8cb5d BZ	267	.pio_mask = ATA_PIO4, \
	268	.mwdma_mask = ATA_MWDMA2, \
	269	.udma_mask = udma, \
6b492496	270	.max_sectors = sectors, \
5ef8cb5d BZ	271	}
5ef8cb5d BZ	272
85620436	273	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
ced3ec8a BZ	274	{ /* 0: PDC20246 */
ced3ec8a BZ	275	.name = DRV_NAME,
1da177e4	276	.init_chipset = init_chipset_pdc202xx,
ac95beed	277	.port_ops = &pdc20246_port_ops,
72b9304f	278	.dma_ops = &sff_dma_ops,
4db90a14	279	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	280	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	281	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	282	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	283	},
5ef8cb5d BZ	284
ced3ec8a BZ	285	/* 1: PDC2026{2,3} */
ced3ec8a BZ	286	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
6b492496 BZ	287	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
6b492496 BZ	288	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
1da177e4 LT	289	};
	290
	291	/**
	292	* pdc202xx_init_one - called when a PDC202xx is found
	293	* @dev: the pdc202xx device
	294	* @id: the matching pci id
	295	*
	296	* Called when the PCI registration layer (or the IDE initialization)
	297	* finds a device matching our IDE device tables.
	298	*/
	299
	300	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	301	{
85620436	302	const struct ide_port_info *d;
97f84baa BZ	303	u8 idx = id->driver_data;
	304
	305	d = &pdc202xx_chipsets[idx];
	306
ced3ec8a	307	if (idx < 2)
97f84baa BZ	308	pdc202ata4_fixup_irq(dev, d->name);
97f84baa BZ	309
ced3ec8a	310	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
97f84baa	311	struct pci_dev *bridge = dev->bus->self;
1da177e4	312
97f84baa BZ	313	if (bridge &&
	314	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	315	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	316	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	317	printk(KERN_INFO DRV_NAME " %s: skipping Promise "
28cfd8af BZ	318	"PDC20265 attached to I2O RAID controller\n",
28cfd8af BZ	319	pci_name(dev));
97f84baa BZ	320	return -ENODEV;
	321	}
	322	}
	323
6cdf6eb3	324	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	325	}
1da177e4 LT	326
9cbcc5e3 BZ	327	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	328	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	329	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
ced3ec8a BZ	330	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	331	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	332	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
1da177e4 LT	333	{ 0, },
	334	};
	335	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	336
a9ab09e2	337	static struct pci_driver pdc202xx_pci_driver = {
1da177e4 LT	338	.name = "Promise_Old_IDE",
	339	.id_table = pdc202xx_pci_tbl,
	340	.probe = pdc202xx_init_one,
574a1c24	341	.remove = ide_pci_remove,
feb22b7f BZ	342	.suspend = ide_pci_suspend,
feb22b7f BZ	343	.resume = ide_pci_resume,
1da177e4 LT	344	};
1da177e4 LT	345
82ab1eec	346	static int __init pdc202xx_ide_init(void)
1da177e4	347	{
a9ab09e2	348	return ide_pci_register_driver(&pdc202xx_pci_driver);
1da177e4 LT	349	}
1da177e4 LT	350
574a1c24 BZ	351	static void __exit pdc202xx_ide_exit(void)
574a1c24 BZ	352	{
a9ab09e2	353	pci_unregister_driver(&pdc202xx_pci_driver);
574a1c24 BZ	354	}
574a1c24 BZ	355
1da177e4	356	module_init(pdc202xx_ide_init);
574a1c24	357	module_exit(pdc202xx_ide_exit);
1da177e4 LT	358
	359	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	360	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	361	MODULE_LICENSE("GPL");