Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Support for IDE interfaces on PowerMacs. |
58f189fc | 3 | * |
1da177e4 LT |
4 | * These IDE interfaces are memory-mapped and have a DBDMA channel |
5 | * for doing DMA. | |
6 | * | |
7 | * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt | |
8a97206e | 8 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * Some code taken from drivers/ide/ide-dma.c: | |
16 | * | |
17 | * Copyright (c) 1995-1998 Mark Lord | |
18 | * | |
19 | * TODO: - Use pre-calculated (kauai) timing tables all the time and | |
20 | * get rid of the "rounded" tables used previously, so we have the | |
21 | * same table format for all controllers and can then just have one | |
22 | * big table | |
23 | * | |
24 | */ | |
1da177e4 LT |
25 | #include <linux/types.h> |
26 | #include <linux/kernel.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/ide.h> | |
30 | #include <linux/notifier.h> | |
31 | #include <linux/reboot.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/adb.h> | |
34 | #include <linux/pmu.h> | |
35 | #include <linux/scatterlist.h> | |
36 | ||
37 | #include <asm/prom.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/dbdma.h> | |
40 | #include <asm/ide.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/machdep.h> | |
43 | #include <asm/pmac_feature.h> | |
44 | #include <asm/sections.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #ifndef CONFIG_PPC64 | |
48 | #include <asm/mediabay.h> | |
49 | #endif | |
50 | ||
b36ba532 BZ |
51 | #define DRV_NAME "ide-pmac" |
52 | ||
1da177e4 LT |
53 | #undef IDE_PMAC_DEBUG |
54 | ||
55 | #define DMA_WAIT_TIMEOUT 50 | |
56 | ||
57 | typedef struct pmac_ide_hwif { | |
58 | unsigned long regbase; | |
59 | int irq; | |
60 | int kind; | |
61 | int aapl_bus_id; | |
1da177e4 LT |
62 | unsigned mediabay : 1; |
63 | unsigned broken_dma : 1; | |
64 | unsigned broken_dma_warn : 1; | |
65 | struct device_node* node; | |
66 | struct macio_dev *mdev; | |
67 | u32 timings[4]; | |
68 | volatile u32 __iomem * *kauai_fcr; | |
1da177e4 LT |
69 | /* Those fields are duplicating what is in hwif. We currently |
70 | * can't use the hwif ones because of some assumptions that are | |
71 | * beeing done by the generic code about the kind of dma controller | |
72 | * and format of the dma table. This will have to be fixed though. | |
73 | */ | |
74 | volatile struct dbdma_regs __iomem * dma_regs; | |
75 | struct dbdma_cmd* dma_table_cpu; | |
1da177e4 LT |
76 | } pmac_ide_hwif_t; |
77 | ||
1da177e4 LT |
78 | enum { |
79 | controller_ohare, /* OHare based */ | |
80 | controller_heathrow, /* Heathrow/Paddington */ | |
81 | controller_kl_ata3, /* KeyLargo ATA-3 */ | |
82 | controller_kl_ata4, /* KeyLargo ATA-4 */ | |
83 | controller_un_ata6, /* UniNorth2 ATA-6 */ | |
84 | controller_k2_ata6, /* K2 ATA-6 */ | |
85 | controller_sh_ata6, /* Shasta ATA-6 */ | |
86 | }; | |
87 | ||
88 | static const char* model_name[] = { | |
89 | "OHare ATA", /* OHare based */ | |
90 | "Heathrow ATA", /* Heathrow/Paddington */ | |
91 | "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ | |
92 | "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ | |
93 | "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ | |
94 | "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ | |
95 | "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ | |
96 | }; | |
97 | ||
98 | /* | |
99 | * Extra registers, both 32-bit little-endian | |
100 | */ | |
101 | #define IDE_TIMING_CONFIG 0x200 | |
102 | #define IDE_INTERRUPT 0x300 | |
103 | ||
104 | /* Kauai (U2) ATA has different register setup */ | |
105 | #define IDE_KAUAI_PIO_CONFIG 0x200 | |
106 | #define IDE_KAUAI_ULTRA_CONFIG 0x210 | |
107 | #define IDE_KAUAI_POLL_CONFIG 0x220 | |
108 | ||
109 | /* | |
110 | * Timing configuration register definitions | |
111 | */ | |
112 | ||
113 | /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ | |
114 | #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) | |
115 | #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) | |
116 | #define IDE_SYSCLK_NS 30 /* 33Mhz cell */ | |
117 | #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ | |
118 | ||
119 | /* 133Mhz cell, found in shasta. | |
120 | * See comments about 100 Mhz Uninorth 2... | |
121 | * Note that PIO_MASK and MDMA_MASK seem to overlap | |
122 | */ | |
123 | #define TR_133_PIOREG_PIO_MASK 0xff000fff | |
124 | #define TR_133_PIOREG_MDMA_MASK 0x00fff800 | |
125 | #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff | |
126 | #define TR_133_UDMAREG_UDMA_EN 0x00000001 | |
127 | ||
128 | /* 100Mhz cell, found in Uninorth 2. I don't have much infos about | |
129 | * this one yet, it appears as a pci device (106b/0033) on uninorth | |
130 | * internal PCI bus and it's clock is controlled like gem or fw. It | |
131 | * appears to be an evolution of keylargo ATA4 with a timing register | |
132 | * extended to 2 32bits registers and a similar DBDMA channel. Other | |
133 | * registers seem to exist but I can't tell much about them. | |
134 | * | |
135 | * So far, I'm using pre-calculated tables for this extracted from | |
136 | * the values used by the MacOS X driver. | |
137 | * | |
138 | * The "PIO" register controls PIO and MDMA timings, the "ULTRA" | |
139 | * register controls the UDMA timings. At least, it seems bit 0 | |
140 | * of this one enables UDMA vs. MDMA, and bits 4..7 are the | |
141 | * cycle time in units of 10ns. Bits 8..15 are used by I don't | |
142 | * know their meaning yet | |
143 | */ | |
144 | #define TR_100_PIOREG_PIO_MASK 0xff000fff | |
145 | #define TR_100_PIOREG_MDMA_MASK 0x00fff000 | |
146 | #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff | |
147 | #define TR_100_UDMAREG_UDMA_EN 0x00000001 | |
148 | ||
149 | ||
150 | /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on | |
151 | * 40 connector cable and to 4 on 80 connector one. | |
152 | * Clock unit is 15ns (66Mhz) | |
153 | * | |
154 | * 3 Values can be programmed: | |
155 | * - Write data setup, which appears to match the cycle time. They | |
156 | * also call it DIOW setup. | |
157 | * - Ready to pause time (from spec) | |
158 | * - Address setup. That one is weird. I don't see where exactly | |
159 | * it fits in UDMA cycles, I got it's name from an obscure piece | |
160 | * of commented out code in Darwin. They leave it to 0, we do as | |
161 | * well, despite a comment that would lead to think it has a | |
162 | * min value of 45ns. | |
163 | * Apple also add 60ns to the write data setup (or cycle time ?) on | |
164 | * reads. | |
165 | */ | |
166 | #define TR_66_UDMA_MASK 0xfff00000 | |
167 | #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ | |
168 | #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */ | |
169 | #define TR_66_UDMA_ADDRSETUP_SHIFT 29 | |
170 | #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ | |
171 | #define TR_66_UDMA_RDY2PAUS_SHIFT 25 | |
172 | #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ | |
173 | #define TR_66_UDMA_WRDATASETUP_SHIFT 21 | |
174 | #define TR_66_MDMA_MASK 0x000ffc00 | |
175 | #define TR_66_MDMA_RECOVERY_MASK 0x000f8000 | |
176 | #define TR_66_MDMA_RECOVERY_SHIFT 15 | |
177 | #define TR_66_MDMA_ACCESS_MASK 0x00007c00 | |
178 | #define TR_66_MDMA_ACCESS_SHIFT 10 | |
179 | #define TR_66_PIO_MASK 0x000003ff | |
180 | #define TR_66_PIO_RECOVERY_MASK 0x000003e0 | |
181 | #define TR_66_PIO_RECOVERY_SHIFT 5 | |
182 | #define TR_66_PIO_ACCESS_MASK 0x0000001f | |
183 | #define TR_66_PIO_ACCESS_SHIFT 0 | |
184 | ||
185 | /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo | |
186 | * Can do pio & mdma modes, clock unit is 30ns (33Mhz) | |
187 | * | |
188 | * The access time and recovery time can be programmed. Some older | |
189 | * Darwin code base limit OHare to 150ns cycle time. I decided to do | |
190 | * the same here fore safety against broken old hardware ;) | |
191 | * The HalfTick bit, when set, adds half a clock (15ns) to the access | |
192 | * time and removes one from recovery. It's not supported on KeyLargo | |
193 | * implementation afaik. The E bit appears to be set for PIO mode 0 and | |
194 | * is used to reach long timings used in this mode. | |
195 | */ | |
196 | #define TR_33_MDMA_MASK 0x003ff800 | |
197 | #define TR_33_MDMA_RECOVERY_MASK 0x001f0000 | |
198 | #define TR_33_MDMA_RECOVERY_SHIFT 16 | |
199 | #define TR_33_MDMA_ACCESS_MASK 0x0000f800 | |
200 | #define TR_33_MDMA_ACCESS_SHIFT 11 | |
201 | #define TR_33_MDMA_HALFTICK 0x00200000 | |
202 | #define TR_33_PIO_MASK 0x000007ff | |
203 | #define TR_33_PIO_E 0x00000400 | |
204 | #define TR_33_PIO_RECOVERY_MASK 0x000003e0 | |
205 | #define TR_33_PIO_RECOVERY_SHIFT 5 | |
206 | #define TR_33_PIO_ACCESS_MASK 0x0000001f | |
207 | #define TR_33_PIO_ACCESS_SHIFT 0 | |
208 | ||
209 | /* | |
210 | * Interrupt register definitions | |
211 | */ | |
212 | #define IDE_INTR_DMA 0x80000000 | |
213 | #define IDE_INTR_DEVICE 0x40000000 | |
214 | ||
215 | /* | |
216 | * FCR Register on Kauai. Not sure what bit 0x4 is ... | |
217 | */ | |
218 | #define KAUAI_FCR_UATA_MAGIC 0x00000004 | |
219 | #define KAUAI_FCR_UATA_RESET_N 0x00000002 | |
220 | #define KAUAI_FCR_UATA_ENABLE 0x00000001 | |
221 | ||
1da177e4 LT |
222 | /* Rounded Multiword DMA timings |
223 | * | |
224 | * I gave up finding a generic formula for all controller | |
225 | * types and instead, built tables based on timing values | |
226 | * used by Apple in Darwin's implementation. | |
227 | */ | |
228 | struct mdma_timings_t { | |
229 | int accessTime; | |
230 | int recoveryTime; | |
231 | int cycleTime; | |
232 | }; | |
233 | ||
aacaf9bd | 234 | struct mdma_timings_t mdma_timings_33[] = |
1da177e4 LT |
235 | { |
236 | { 240, 240, 480 }, | |
237 | { 180, 180, 360 }, | |
238 | { 135, 135, 270 }, | |
239 | { 120, 120, 240 }, | |
240 | { 105, 105, 210 }, | |
241 | { 90, 90, 180 }, | |
242 | { 75, 75, 150 }, | |
243 | { 75, 45, 120 }, | |
244 | { 0, 0, 0 } | |
245 | }; | |
246 | ||
aacaf9bd | 247 | struct mdma_timings_t mdma_timings_33k[] = |
1da177e4 LT |
248 | { |
249 | { 240, 240, 480 }, | |
250 | { 180, 180, 360 }, | |
251 | { 150, 150, 300 }, | |
252 | { 120, 120, 240 }, | |
253 | { 90, 120, 210 }, | |
254 | { 90, 90, 180 }, | |
255 | { 90, 60, 150 }, | |
256 | { 90, 30, 120 }, | |
257 | { 0, 0, 0 } | |
258 | }; | |
259 | ||
aacaf9bd | 260 | struct mdma_timings_t mdma_timings_66[] = |
1da177e4 LT |
261 | { |
262 | { 240, 240, 480 }, | |
263 | { 180, 180, 360 }, | |
264 | { 135, 135, 270 }, | |
265 | { 120, 120, 240 }, | |
266 | { 105, 105, 210 }, | |
267 | { 90, 90, 180 }, | |
268 | { 90, 75, 165 }, | |
269 | { 75, 45, 120 }, | |
270 | { 0, 0, 0 } | |
271 | }; | |
272 | ||
273 | /* KeyLargo ATA-4 Ultra DMA timings (rounded) */ | |
274 | struct { | |
275 | int addrSetup; /* ??? */ | |
276 | int rdy2pause; | |
277 | int wrDataSetup; | |
aacaf9bd | 278 | } kl66_udma_timings[] = |
1da177e4 LT |
279 | { |
280 | { 0, 180, 120 }, /* Mode 0 */ | |
281 | { 0, 150, 90 }, /* 1 */ | |
282 | { 0, 120, 60 }, /* 2 */ | |
283 | { 0, 90, 45 }, /* 3 */ | |
284 | { 0, 90, 30 } /* 4 */ | |
285 | }; | |
286 | ||
287 | /* UniNorth 2 ATA/100 timings */ | |
288 | struct kauai_timing { | |
289 | int cycle_time; | |
290 | u32 timing_reg; | |
291 | }; | |
292 | ||
aacaf9bd | 293 | static struct kauai_timing kauai_pio_timings[] = |
1da177e4 LT |
294 | { |
295 | { 930 , 0x08000fff }, | |
296 | { 600 , 0x08000a92 }, | |
297 | { 383 , 0x0800060f }, | |
298 | { 360 , 0x08000492 }, | |
299 | { 330 , 0x0800048f }, | |
300 | { 300 , 0x080003cf }, | |
301 | { 270 , 0x080003cc }, | |
302 | { 240 , 0x0800038b }, | |
303 | { 239 , 0x0800030c }, | |
304 | { 180 , 0x05000249 }, | |
c15d5d43 BZ |
305 | { 120 , 0x04000148 }, |
306 | { 0 , 0 }, | |
1da177e4 LT |
307 | }; |
308 | ||
aacaf9bd | 309 | static struct kauai_timing kauai_mdma_timings[] = |
1da177e4 LT |
310 | { |
311 | { 1260 , 0x00fff000 }, | |
312 | { 480 , 0x00618000 }, | |
313 | { 360 , 0x00492000 }, | |
314 | { 270 , 0x0038e000 }, | |
315 | { 240 , 0x0030c000 }, | |
316 | { 210 , 0x002cb000 }, | |
317 | { 180 , 0x00249000 }, | |
318 | { 150 , 0x00209000 }, | |
319 | { 120 , 0x00148000 }, | |
320 | { 0 , 0 }, | |
321 | }; | |
322 | ||
aacaf9bd | 323 | static struct kauai_timing kauai_udma_timings[] = |
1da177e4 LT |
324 | { |
325 | { 120 , 0x000070c0 }, | |
326 | { 90 , 0x00005d80 }, | |
327 | { 60 , 0x00004a60 }, | |
328 | { 45 , 0x00003a50 }, | |
329 | { 30 , 0x00002a30 }, | |
330 | { 20 , 0x00002921 }, | |
331 | { 0 , 0 }, | |
332 | }; | |
333 | ||
aacaf9bd | 334 | static struct kauai_timing shasta_pio_timings[] = |
1da177e4 LT |
335 | { |
336 | { 930 , 0x08000fff }, | |
337 | { 600 , 0x0A000c97 }, | |
338 | { 383 , 0x07000712 }, | |
339 | { 360 , 0x040003cd }, | |
340 | { 330 , 0x040003cd }, | |
341 | { 300 , 0x040003cd }, | |
342 | { 270 , 0x040003cd }, | |
343 | { 240 , 0x040003cd }, | |
344 | { 239 , 0x040003cd }, | |
345 | { 180 , 0x0400028b }, | |
c15d5d43 BZ |
346 | { 120 , 0x0400010a }, |
347 | { 0 , 0 }, | |
1da177e4 LT |
348 | }; |
349 | ||
aacaf9bd | 350 | static struct kauai_timing shasta_mdma_timings[] = |
1da177e4 LT |
351 | { |
352 | { 1260 , 0x00fff000 }, | |
353 | { 480 , 0x00820800 }, | |
354 | { 360 , 0x00820800 }, | |
355 | { 270 , 0x00820800 }, | |
356 | { 240 , 0x00820800 }, | |
357 | { 210 , 0x00820800 }, | |
358 | { 180 , 0x00820800 }, | |
359 | { 150 , 0x0028b000 }, | |
360 | { 120 , 0x001ca000 }, | |
361 | { 0 , 0 }, | |
362 | }; | |
363 | ||
aacaf9bd | 364 | static struct kauai_timing shasta_udma133_timings[] = |
1da177e4 LT |
365 | { |
366 | { 120 , 0x00035901, }, | |
367 | { 90 , 0x000348b1, }, | |
368 | { 60 , 0x00033881, }, | |
369 | { 45 , 0x00033861, }, | |
370 | { 30 , 0x00033841, }, | |
371 | { 20 , 0x00033031, }, | |
372 | { 15 , 0x00033021, }, | |
373 | { 0 , 0 }, | |
374 | }; | |
375 | ||
376 | ||
377 | static inline u32 | |
378 | kauai_lookup_timing(struct kauai_timing* table, int cycle_time) | |
379 | { | |
380 | int i; | |
381 | ||
382 | for (i=0; table[i].cycle_time; i++) | |
383 | if (cycle_time > table[i+1].cycle_time) | |
384 | return table[i].timing_reg; | |
90a87ea4 | 385 | BUG(); |
1da177e4 LT |
386 | return 0; |
387 | } | |
388 | ||
389 | /* allow up to 256 DBDMA commands per xfer */ | |
390 | #define MAX_DCMDS 256 | |
391 | ||
392 | /* | |
393 | * Wait 1s for disk to answer on IDE bus after a hard reset | |
394 | * of the device (via GPIO/FCR). | |
395 | * | |
396 | * Some devices seem to "pollute" the bus even after dropping | |
397 | * the BSY bit (typically some combo drives slave on the UDMA | |
398 | * bus) after a hard reset. Since we hard reset all drives on | |
399 | * KeyLargo ATA66, we have to keep that delay around. I may end | |
400 | * up not hard resetting anymore on these and keep the delay only | |
401 | * for older interfaces instead (we have to reset when coming | |
402 | * from MacOS...) --BenH. | |
403 | */ | |
404 | #define IDE_WAKEUP_DELAY (1*HZ) | |
405 | ||
0d071922 | 406 | static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); |
1da177e4 LT |
407 | static void pmac_ide_selectproc(ide_drive_t *drive); |
408 | static void pmac_ide_kauai_selectproc(ide_drive_t *drive); | |
409 | ||
23579a2a | 410 | #define PMAC_IDE_REG(x) \ |
4c3032d8 | 411 | ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) |
1da177e4 LT |
412 | |
413 | /* | |
414 | * Apply the timings of the proper unit (master/slave) to the shared | |
415 | * timing register when selecting that unit. This version is for | |
416 | * ASICs with a single timing register | |
417 | */ | |
aacaf9bd | 418 | static void |
1da177e4 LT |
419 | pmac_ide_selectproc(ide_drive_t *drive) |
420 | { | |
7b8797ac BZ |
421 | ide_hwif_t *hwif = drive->hwif; |
422 | pmac_ide_hwif_t *pmif = | |
423 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 | 424 | |
123995b9 | 425 | if (drive->dn & 1) |
1da177e4 LT |
426 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); |
427 | else | |
428 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
429 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
430 | } | |
431 | ||
432 | /* | |
433 | * Apply the timings of the proper unit (master/slave) to the shared | |
434 | * timing register when selecting that unit. This version is for | |
435 | * ASICs with a dual timing register (Kauai) | |
436 | */ | |
aacaf9bd | 437 | static void |
1da177e4 LT |
438 | pmac_ide_kauai_selectproc(ide_drive_t *drive) |
439 | { | |
7b8797ac BZ |
440 | ide_hwif_t *hwif = drive->hwif; |
441 | pmac_ide_hwif_t *pmif = | |
442 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 | 443 | |
123995b9 | 444 | if (drive->dn & 1) { |
1da177e4 LT |
445 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); |
446 | writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
447 | } else { | |
448 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
449 | writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
450 | } | |
451 | (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
452 | } | |
453 | ||
454 | /* | |
455 | * Force an update of controller timing values for a given drive | |
456 | */ | |
aacaf9bd | 457 | static void |
1da177e4 LT |
458 | pmac_ide_do_update_timings(ide_drive_t *drive) |
459 | { | |
7b8797ac BZ |
460 | ide_hwif_t *hwif = drive->hwif; |
461 | pmac_ide_hwif_t *pmif = | |
462 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 | 463 | |
1da177e4 LT |
464 | if (pmif->kind == controller_sh_ata6 || |
465 | pmif->kind == controller_un_ata6 || | |
466 | pmif->kind == controller_k2_ata6) | |
467 | pmac_ide_kauai_selectproc(drive); | |
468 | else | |
469 | pmac_ide_selectproc(drive); | |
470 | } | |
471 | ||
c6dfa867 BZ |
472 | static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd) |
473 | { | |
474 | writeb(cmd, (void __iomem *)hwif->io_ports.command_addr); | |
475 | (void)readl((void __iomem *)(hwif->io_ports.data_addr | |
476 | + IDE_TIMING_CONFIG)); | |
477 | } | |
478 | ||
ecf3a31d | 479 | static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl) |
6e6afb3b | 480 | { |
6e6afb3b BZ |
481 | writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr); |
482 | (void)readl((void __iomem *)(hwif->io_ports.data_addr | |
483 | + IDE_TIMING_CONFIG)); | |
484 | } | |
485 | ||
1da177e4 LT |
486 | /* |
487 | * Old tuning functions (called on hdparm -p), sets up drive PIO timings | |
488 | */ | |
aacaf9bd | 489 | static void |
26bcb879 | 490 | pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 491 | { |
7b8797ac BZ |
492 | ide_hwif_t *hwif = drive->hwif; |
493 | pmac_ide_hwif_t *pmif = | |
494 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
8a97206e | 495 | struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio); |
0b46ff2e | 496 | u32 *timings, t; |
1da177e4 LT |
497 | unsigned accessTicks, recTicks; |
498 | unsigned accessTime, recTime; | |
7dd00083 BZ |
499 | unsigned int cycle_time; |
500 | ||
1da177e4 | 501 | /* which drive is it ? */ |
123995b9 | 502 | timings = &pmif->timings[drive->dn & 1]; |
0b46ff2e | 503 | t = *timings; |
1da177e4 | 504 | |
7dd00083 | 505 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 LT |
506 | |
507 | switch (pmif->kind) { | |
508 | case controller_sh_ata6: { | |
509 | /* 133Mhz cell */ | |
7dd00083 | 510 | u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time); |
0b46ff2e | 511 | t = (t & ~TR_133_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
512 | break; |
513 | } | |
514 | case controller_un_ata6: | |
515 | case controller_k2_ata6: { | |
516 | /* 100Mhz cell */ | |
7dd00083 | 517 | u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time); |
0b46ff2e | 518 | t = (t & ~TR_100_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
519 | break; |
520 | } | |
521 | case controller_kl_ata4: | |
522 | /* 66Mhz cell */ | |
8a97206e | 523 | recTime = cycle_time - tim->active - tim->setup; |
1da177e4 | 524 | recTime = max(recTime, 150U); |
8a97206e | 525 | accessTime = tim->active; |
1da177e4 LT |
526 | accessTime = max(accessTime, 150U); |
527 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
528 | accessTicks = min(accessTicks, 0x1fU); | |
529 | recTicks = SYSCLK_TICKS_66(recTime); | |
530 | recTicks = min(recTicks, 0x1fU); | |
0b46ff2e BH |
531 | t = (t & ~TR_66_PIO_MASK) | |
532 | (accessTicks << TR_66_PIO_ACCESS_SHIFT) | | |
533 | (recTicks << TR_66_PIO_RECOVERY_SHIFT); | |
1da177e4 LT |
534 | break; |
535 | default: { | |
536 | /* 33Mhz cell */ | |
537 | int ebit = 0; | |
8a97206e | 538 | recTime = cycle_time - tim->active - tim->setup; |
1da177e4 | 539 | recTime = max(recTime, 150U); |
8a97206e | 540 | accessTime = tim->active; |
1da177e4 LT |
541 | accessTime = max(accessTime, 150U); |
542 | accessTicks = SYSCLK_TICKS(accessTime); | |
543 | accessTicks = min(accessTicks, 0x1fU); | |
544 | accessTicks = max(accessTicks, 4U); | |
545 | recTicks = SYSCLK_TICKS(recTime); | |
546 | recTicks = min(recTicks, 0x1fU); | |
547 | recTicks = max(recTicks, 5U) - 4; | |
548 | if (recTicks > 9) { | |
549 | recTicks--; /* guess, but it's only for PIO0, so... */ | |
550 | ebit = 1; | |
551 | } | |
0b46ff2e | 552 | t = (t & ~TR_33_PIO_MASK) | |
1da177e4 LT |
553 | (accessTicks << TR_33_PIO_ACCESS_SHIFT) | |
554 | (recTicks << TR_33_PIO_RECOVERY_SHIFT); | |
555 | if (ebit) | |
0b46ff2e | 556 | t |= TR_33_PIO_E; |
1da177e4 LT |
557 | break; |
558 | } | |
559 | } | |
560 | ||
561 | #ifdef IDE_PMAC_DEBUG | |
562 | printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", | |
563 | drive->name, pio, *timings); | |
564 | #endif | |
565 | ||
0b46ff2e | 566 | *timings = t; |
c15d5d43 | 567 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
568 | } |
569 | ||
1da177e4 LT |
570 | /* |
571 | * Calculate KeyLargo ATA/66 UDMA timings | |
572 | */ | |
aacaf9bd | 573 | static int |
1da177e4 LT |
574 | set_timings_udma_ata4(u32 *timings, u8 speed) |
575 | { | |
576 | unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; | |
577 | ||
578 | if (speed > XFER_UDMA_4) | |
579 | return 1; | |
580 | ||
581 | rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause); | |
582 | wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup); | |
583 | addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup); | |
584 | ||
585 | *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) | | |
586 | (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | | |
587 | (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) | | |
588 | (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) | | |
589 | TR_66_UDMA_EN; | |
590 | #ifdef IDE_PMAC_DEBUG | |
591 | printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", | |
592 | speed & 0xf, *timings); | |
593 | #endif | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | /* | |
599 | * Calculate Kauai ATA/100 UDMA timings | |
600 | */ | |
aacaf9bd | 601 | static int |
1da177e4 LT |
602 | set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
603 | { | |
604 | struct ide_timing *t = ide_timing_find_mode(speed); | |
605 | u32 tr; | |
606 | ||
607 | if (speed > XFER_UDMA_5 || t == NULL) | |
608 | return 1; | |
609 | tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma); | |
1da177e4 LT |
610 | *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr; |
611 | *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | /* | |
617 | * Calculate Shasta ATA/133 UDMA timings | |
618 | */ | |
aacaf9bd | 619 | static int |
1da177e4 LT |
620 | set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
621 | { | |
622 | struct ide_timing *t = ide_timing_find_mode(speed); | |
623 | u32 tr; | |
624 | ||
625 | if (speed > XFER_UDMA_6 || t == NULL) | |
626 | return 1; | |
627 | tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma); | |
1da177e4 LT |
628 | *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr; |
629 | *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN; | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | /* | |
635 | * Calculate MDMA timings for all cells | |
636 | */ | |
90f72eca | 637 | static void |
1da177e4 | 638 | set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, |
90f72eca | 639 | u8 speed) |
1da177e4 | 640 | { |
4dde4492 | 641 | u16 *id = drive->id; |
1da177e4 LT |
642 | int cycleTime, accessTime = 0, recTime = 0; |
643 | unsigned accessTicks, recTicks; | |
644 | struct mdma_timings_t* tm = NULL; | |
645 | int i; | |
646 | ||
647 | /* Get default cycle time for mode */ | |
648 | switch(speed & 0xf) { | |
649 | case 0: cycleTime = 480; break; | |
650 | case 1: cycleTime = 150; break; | |
651 | case 2: cycleTime = 120; break; | |
652 | default: | |
90f72eca BZ |
653 | BUG(); |
654 | break; | |
1da177e4 | 655 | } |
90f72eca BZ |
656 | |
657 | /* Check if drive provides explicit DMA cycle time */ | |
4dde4492 BZ |
658 | if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME]) |
659 | cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime); | |
90f72eca | 660 | |
1da177e4 LT |
661 | /* OHare limits according to some old Apple sources */ |
662 | if ((intf_type == controller_ohare) && (cycleTime < 150)) | |
663 | cycleTime = 150; | |
664 | /* Get the proper timing array for this controller */ | |
665 | switch(intf_type) { | |
666 | case controller_sh_ata6: | |
667 | case controller_un_ata6: | |
668 | case controller_k2_ata6: | |
669 | break; | |
670 | case controller_kl_ata4: | |
671 | tm = mdma_timings_66; | |
672 | break; | |
673 | case controller_kl_ata3: | |
674 | tm = mdma_timings_33k; | |
675 | break; | |
676 | default: | |
677 | tm = mdma_timings_33; | |
678 | break; | |
679 | } | |
680 | if (tm != NULL) { | |
681 | /* Lookup matching access & recovery times */ | |
682 | i = -1; | |
683 | for (;;) { | |
684 | if (tm[i+1].cycleTime < cycleTime) | |
685 | break; | |
686 | i++; | |
687 | } | |
1da177e4 LT |
688 | cycleTime = tm[i].cycleTime; |
689 | accessTime = tm[i].accessTime; | |
690 | recTime = tm[i].recoveryTime; | |
691 | ||
692 | #ifdef IDE_PMAC_DEBUG | |
693 | printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", | |
694 | drive->name, cycleTime, accessTime, recTime); | |
695 | #endif | |
696 | } | |
697 | switch(intf_type) { | |
698 | case controller_sh_ata6: { | |
699 | /* 133Mhz cell */ | |
700 | u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime); | |
1da177e4 LT |
701 | *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr; |
702 | *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN; | |
703 | } | |
704 | case controller_un_ata6: | |
705 | case controller_k2_ata6: { | |
706 | /* 100Mhz cell */ | |
707 | u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime); | |
1da177e4 LT |
708 | *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr; |
709 | *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN; | |
710 | } | |
711 | break; | |
712 | case controller_kl_ata4: | |
713 | /* 66Mhz cell */ | |
714 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
715 | accessTicks = min(accessTicks, 0x1fU); | |
716 | accessTicks = max(accessTicks, 0x1U); | |
717 | recTicks = SYSCLK_TICKS_66(recTime); | |
718 | recTicks = min(recTicks, 0x1fU); | |
719 | recTicks = max(recTicks, 0x3U); | |
720 | /* Clear out mdma bits and disable udma */ | |
721 | *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) | | |
722 | (accessTicks << TR_66_MDMA_ACCESS_SHIFT) | | |
723 | (recTicks << TR_66_MDMA_RECOVERY_SHIFT); | |
724 | break; | |
725 | case controller_kl_ata3: | |
726 | /* 33Mhz cell on KeyLargo */ | |
727 | accessTicks = SYSCLK_TICKS(accessTime); | |
728 | accessTicks = max(accessTicks, 1U); | |
729 | accessTicks = min(accessTicks, 0x1fU); | |
730 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
731 | recTicks = SYSCLK_TICKS(recTime); | |
732 | recTicks = max(recTicks, 1U); | |
733 | recTicks = min(recTicks, 0x1fU); | |
734 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
735 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
736 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
737 | break; | |
738 | default: { | |
739 | /* 33Mhz cell on others */ | |
740 | int halfTick = 0; | |
741 | int origAccessTime = accessTime; | |
742 | int origRecTime = recTime; | |
743 | ||
744 | accessTicks = SYSCLK_TICKS(accessTime); | |
745 | accessTicks = max(accessTicks, 1U); | |
746 | accessTicks = min(accessTicks, 0x1fU); | |
747 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
748 | recTicks = SYSCLK_TICKS(recTime); | |
749 | recTicks = max(recTicks, 2U) - 1; | |
750 | recTicks = min(recTicks, 0x1fU); | |
751 | recTime = (recTicks + 1) * IDE_SYSCLK_NS; | |
752 | if ((accessTicks > 1) && | |
753 | ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) && | |
754 | ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) { | |
755 | halfTick = 1; | |
756 | accessTicks--; | |
757 | } | |
758 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
759 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
760 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
761 | if (halfTick) | |
762 | *timings |= TR_33_MDMA_HALFTICK; | |
763 | } | |
764 | } | |
765 | #ifdef IDE_PMAC_DEBUG | |
766 | printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", | |
767 | drive->name, speed & 0xf, *timings); | |
768 | #endif | |
1da177e4 | 769 | } |
1da177e4 | 770 | |
88b2b32b | 771 | static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 772 | { |
7b8797ac BZ |
773 | ide_hwif_t *hwif = drive->hwif; |
774 | pmac_ide_hwif_t *pmif = | |
775 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 | 776 | int ret = 0; |
085798b1 | 777 | u32 *timings, *timings2, tl[2]; |
123995b9 | 778 | u8 unit = drive->dn & 1; |
1da177e4 | 779 | |
1da177e4 LT |
780 | timings = &pmif->timings[unit]; |
781 | timings2 = &pmif->timings[unit+2]; | |
085798b1 BZ |
782 | |
783 | /* Copy timings to local image */ | |
784 | tl[0] = *timings; | |
785 | tl[1] = *timings2; | |
786 | ||
4db90a14 BZ |
787 | if (speed >= XFER_UDMA_0) { |
788 | if (pmif->kind == controller_kl_ata4) | |
789 | ret = set_timings_udma_ata4(&tl[0], speed); | |
790 | else if (pmif->kind == controller_un_ata6 | |
791 | || pmif->kind == controller_k2_ata6) | |
792 | ret = set_timings_udma_ata6(&tl[0], &tl[1], speed); | |
793 | else if (pmif->kind == controller_sh_ata6) | |
794 | ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); | |
795 | else | |
796 | ret = -1; | |
797 | } else | |
798 | set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); | |
53846574 | 799 | |
1da177e4 | 800 | if (ret) |
88b2b32b | 801 | return; |
085798b1 BZ |
802 | |
803 | /* Apply timings to controller */ | |
804 | *timings = tl[0]; | |
805 | *timings2 = tl[1]; | |
806 | ||
1da177e4 | 807 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
808 | } |
809 | ||
810 | /* | |
811 | * Blast some well known "safe" values to the timing registers at init or | |
812 | * wakeup from sleep time, before we do real calculation | |
813 | */ | |
aacaf9bd | 814 | static void |
1da177e4 LT |
815 | sanitize_timings(pmac_ide_hwif_t *pmif) |
816 | { | |
817 | unsigned int value, value2 = 0; | |
818 | ||
819 | switch(pmif->kind) { | |
820 | case controller_sh_ata6: | |
821 | value = 0x0a820c97; | |
822 | value2 = 0x00033031; | |
823 | break; | |
824 | case controller_un_ata6: | |
825 | case controller_k2_ata6: | |
826 | value = 0x08618a92; | |
827 | value2 = 0x00002921; | |
828 | break; | |
829 | case controller_kl_ata4: | |
830 | value = 0x0008438c; | |
831 | break; | |
832 | case controller_kl_ata3: | |
833 | value = 0x00084526; | |
834 | break; | |
835 | case controller_heathrow: | |
836 | case controller_ohare: | |
837 | default: | |
838 | value = 0x00074526; | |
839 | break; | |
840 | } | |
841 | pmif->timings[0] = pmif->timings[1] = value; | |
842 | pmif->timings[2] = pmif->timings[3] = value2; | |
843 | } | |
844 | ||
1da177e4 LT |
845 | /* Suspend call back, should be called after the child devices |
846 | * have actually been suspended | |
847 | */ | |
7b8797ac | 848 | static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif) |
1da177e4 | 849 | { |
1da177e4 LT |
850 | /* We clear the timings */ |
851 | pmif->timings[0] = 0; | |
852 | pmif->timings[1] = 0; | |
853 | ||
616299af BH |
854 | disable_irq(pmif->irq); |
855 | ||
1da177e4 LT |
856 | /* The media bay will handle itself just fine */ |
857 | if (pmif->mediabay) | |
858 | return 0; | |
859 | ||
860 | /* Kauai has bus control FCRs directly here */ | |
861 | if (pmif->kauai_fcr) { | |
862 | u32 fcr = readl(pmif->kauai_fcr); | |
863 | fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); | |
864 | writel(fcr, pmif->kauai_fcr); | |
865 | } | |
866 | ||
867 | /* Disable the bus on older machines and the cell on kauai */ | |
868 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, | |
869 | 0); | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
874 | /* Resume call back, should be called before the child devices | |
875 | * are resumed | |
876 | */ | |
7b8797ac | 877 | static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif) |
1da177e4 | 878 | { |
1da177e4 LT |
879 | /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ |
880 | if (!pmif->mediabay) { | |
881 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); | |
882 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); | |
883 | msleep(10); | |
884 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0); | |
1da177e4 LT |
885 | |
886 | /* Kauai has it different */ | |
887 | if (pmif->kauai_fcr) { | |
888 | u32 fcr = readl(pmif->kauai_fcr); | |
889 | fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; | |
890 | writel(fcr, pmif->kauai_fcr); | |
891 | } | |
616299af BH |
892 | |
893 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1da177e4 LT |
894 | } |
895 | ||
896 | /* Sanitize drive timings */ | |
897 | sanitize_timings(pmif); | |
898 | ||
616299af BH |
899 | enable_irq(pmif->irq); |
900 | ||
1da177e4 LT |
901 | return 0; |
902 | } | |
903 | ||
07a6c66d BZ |
904 | static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) |
905 | { | |
7b8797ac BZ |
906 | pmac_ide_hwif_t *pmif = |
907 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
07a6c66d BZ |
908 | struct device_node *np = pmif->node; |
909 | const char *cable = of_get_property(np, "cable-type", NULL); | |
910 | ||
911 | /* Get cable type from device-tree. */ | |
912 | if (cable && !strncmp(cable, "80-", 3)) | |
913 | return ATA_CBL_PATA80; | |
914 | ||
915 | /* | |
916 | * G5's seem to have incorrect cable type in device-tree. | |
917 | * Let's assume they have a 80 conductor cable, this seem | |
918 | * to be always the case unless the user mucked around. | |
919 | */ | |
920 | if (of_device_is_compatible(np, "K2-UATA") || | |
921 | of_device_is_compatible(np, "shasta-ata")) | |
922 | return ATA_CBL_PATA80; | |
923 | ||
924 | return ATA_CBL_PATA40; | |
925 | } | |
926 | ||
07eb106f BZ |
927 | static void pmac_ide_init_dev(ide_drive_t *drive) |
928 | { | |
929 | ide_hwif_t *hwif = drive->hwif; | |
930 | pmac_ide_hwif_t *pmif = | |
931 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
932 | ||
933 | if (pmif->mediabay) { | |
934 | #ifdef CONFIG_PMAC_MEDIABAY | |
935 | if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) { | |
97100fc8 | 936 | drive->dev_flags &= ~IDE_DFLAG_NOPROBE; |
07eb106f BZ |
937 | return; |
938 | } | |
939 | #endif | |
97100fc8 | 940 | drive->dev_flags |= IDE_DFLAG_NOPROBE; |
07eb106f BZ |
941 | } |
942 | } | |
943 | ||
374e042c BZ |
944 | static const struct ide_tp_ops pmac_tp_ops = { |
945 | .exec_command = pmac_exec_command, | |
946 | .read_status = ide_read_status, | |
947 | .read_altstatus = ide_read_altstatus, | |
ecf3a31d | 948 | .write_devctl = pmac_write_devctl, |
374e042c BZ |
949 | |
950 | .tf_load = ide_tf_load, | |
951 | .tf_read = ide_tf_read, | |
952 | ||
953 | .input_data = ide_input_data, | |
954 | .output_data = ide_output_data, | |
955 | }; | |
956 | ||
ac95beed | 957 | static const struct ide_port_ops pmac_ide_ata6_port_ops = { |
07eb106f | 958 | .init_dev = pmac_ide_init_dev, |
ac95beed BZ |
959 | .set_pio_mode = pmac_ide_set_pio_mode, |
960 | .set_dma_mode = pmac_ide_set_dma_mode, | |
961 | .selectproc = pmac_ide_kauai_selectproc, | |
07a6c66d BZ |
962 | .cable_detect = pmac_ide_cable_detect, |
963 | }; | |
964 | ||
965 | static const struct ide_port_ops pmac_ide_ata4_port_ops = { | |
07eb106f | 966 | .init_dev = pmac_ide_init_dev, |
07a6c66d BZ |
967 | .set_pio_mode = pmac_ide_set_pio_mode, |
968 | .set_dma_mode = pmac_ide_set_dma_mode, | |
969 | .selectproc = pmac_ide_selectproc, | |
970 | .cable_detect = pmac_ide_cable_detect, | |
ac95beed BZ |
971 | }; |
972 | ||
973 | static const struct ide_port_ops pmac_ide_port_ops = { | |
07eb106f | 974 | .init_dev = pmac_ide_init_dev, |
ac95beed BZ |
975 | .set_pio_mode = pmac_ide_set_pio_mode, |
976 | .set_dma_mode = pmac_ide_set_dma_mode, | |
977 | .selectproc = pmac_ide_selectproc, | |
978 | }; | |
979 | ||
f37afdac | 980 | static const struct ide_dma_ops pmac_dma_ops; |
5e37bdc0 | 981 | |
c413b9b9 | 982 | static const struct ide_port_info pmac_port_info = { |
b36ba532 | 983 | .name = DRV_NAME, |
0d071922 | 984 | .init_dma = pmac_ide_init_dma, |
c413b9b9 | 985 | .chipset = ide_pmac, |
374e042c BZ |
986 | .tp_ops = &pmac_tp_ops, |
987 | .port_ops = &pmac_ide_port_ops, | |
5e37bdc0 | 988 | .dma_ops = &pmac_dma_ops, |
c413b9b9 | 989 | .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | |
c413b9b9 | 990 | IDE_HFLAG_POST_SET_MODE | |
c5dd43ec | 991 | IDE_HFLAG_MMIO | |
c413b9b9 BZ |
992 | IDE_HFLAG_UNMASK_IRQS, |
993 | .pio_mask = ATA_PIO4, | |
994 | .mwdma_mask = ATA_MWDMA2, | |
995 | }; | |
996 | ||
1da177e4 LT |
997 | /* |
998 | * Setup, register & probe an IDE channel driven by this driver, this is | |
5b16464a | 999 | * called by one of the 2 probe functions (macio or PCI). |
1da177e4 | 1000 | */ |
b36ba532 | 1001 | static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, hw_regs_t *hw) |
1da177e4 LT |
1002 | { |
1003 | struct device_node *np = pmif->node; | |
018a3d1d | 1004 | const int *bidp; |
48c3c107 | 1005 | struct ide_host *host; |
b36ba532 | 1006 | ide_hwif_t *hwif; |
c97c6aca | 1007 | hw_regs_t *hws[] = { hw, NULL, NULL, NULL }; |
c413b9b9 | 1008 | struct ide_port_info d = pmac_port_info; |
6f904d01 | 1009 | int rc; |
1da177e4 | 1010 | |
1da177e4 | 1011 | pmif->broken_dma = pmif->broken_dma_warn = 0; |
c413b9b9 | 1012 | if (of_device_is_compatible(np, "shasta-ata")) { |
1da177e4 | 1013 | pmif->kind = controller_sh_ata6; |
ac95beed | 1014 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1015 | d.udma_mask = ATA_UDMA6; |
1016 | } else if (of_device_is_compatible(np, "kauai-ata")) { | |
1da177e4 | 1017 | pmif->kind = controller_un_ata6; |
ac95beed | 1018 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1019 | d.udma_mask = ATA_UDMA5; |
1020 | } else if (of_device_is_compatible(np, "K2-UATA")) { | |
1da177e4 | 1021 | pmif->kind = controller_k2_ata6; |
ac95beed | 1022 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1023 | d.udma_mask = ATA_UDMA5; |
1024 | } else if (of_device_is_compatible(np, "keylargo-ata")) { | |
1025 | if (strcmp(np->name, "ata-4") == 0) { | |
1da177e4 | 1026 | pmif->kind = controller_kl_ata4; |
07a6c66d | 1027 | d.port_ops = &pmac_ide_ata4_port_ops; |
c413b9b9 BZ |
1028 | d.udma_mask = ATA_UDMA4; |
1029 | } else | |
1da177e4 | 1030 | pmif->kind = controller_kl_ata3; |
c413b9b9 | 1031 | } else if (of_device_is_compatible(np, "heathrow-ata")) { |
1da177e4 | 1032 | pmif->kind = controller_heathrow; |
c413b9b9 | 1033 | } else { |
1da177e4 LT |
1034 | pmif->kind = controller_ohare; |
1035 | pmif->broken_dma = 1; | |
1036 | } | |
1037 | ||
40cd3a45 | 1038 | bidp = of_get_property(np, "AAPL,bus-id", NULL); |
1da177e4 LT |
1039 | pmif->aapl_bus_id = bidp ? *bidp : 0; |
1040 | ||
1da177e4 LT |
1041 | /* On Kauai-type controllers, we make sure the FCR is correct */ |
1042 | if (pmif->kauai_fcr) | |
1043 | writel(KAUAI_FCR_UATA_MAGIC | | |
1044 | KAUAI_FCR_UATA_RESET_N | | |
1045 | KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); | |
1046 | ||
1047 | pmif->mediabay = 0; | |
1048 | ||
1049 | /* Make sure we have sane timings */ | |
1050 | sanitize_timings(pmif); | |
1051 | ||
9842727d BH |
1052 | host = ide_host_alloc(&d, hws); |
1053 | if (host == NULL) | |
1054 | return -ENOMEM; | |
1055 | hwif = host->ports[0]; | |
1056 | ||
1da177e4 LT |
1057 | #ifndef CONFIG_PPC64 |
1058 | /* XXX FIXME: Media bay stuff need re-organizing */ | |
1059 | if (np->parent && np->parent->name | |
1060 | && strcasecmp(np->parent->name, "media-bay") == 0) { | |
8c870933 | 1061 | #ifdef CONFIG_PMAC_MEDIABAY |
2dde7861 BZ |
1062 | media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, |
1063 | hwif); | |
8c870933 | 1064 | #endif /* CONFIG_PMAC_MEDIABAY */ |
1da177e4 LT |
1065 | pmif->mediabay = 1; |
1066 | if (!bidp) | |
1067 | pmif->aapl_bus_id = 1; | |
1068 | } else if (pmif->kind == controller_ohare) { | |
1069 | /* The code below is having trouble on some ohare machines | |
1070 | * (timing related ?). Until I can put my hand on one of these | |
1071 | * units, I keep the old way | |
1072 | */ | |
1073 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); | |
1074 | } else | |
1075 | #endif | |
1076 | { | |
1077 | /* This is necessary to enable IDE when net-booting */ | |
1078 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); | |
1079 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); | |
1080 | msleep(10); | |
1081 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0); | |
1082 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1083 | } | |
1084 | ||
b36ba532 BZ |
1085 | printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), " |
1086 | "bus ID %d%s, irq %d\n", model_name[pmif->kind], | |
1087 | pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id, | |
1088 | pmif->mediabay ? " (mediabay)" : "", hw->irq); | |
1089 | ||
9842727d BH |
1090 | rc = ide_host_register(host, &d, hws); |
1091 | if (rc) { | |
1092 | ide_host_free(host); | |
6f904d01 | 1093 | return rc; |
9842727d | 1094 | } |
5cbf79cd | 1095 | |
1da177e4 LT |
1096 | return 0; |
1097 | } | |
1098 | ||
5c58666f BZ |
1099 | static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base) |
1100 | { | |
1101 | int i; | |
1102 | ||
1103 | for (i = 0; i < 8; ++i) | |
4c3032d8 BZ |
1104 | hw->io_ports_array[i] = base + i * 0x10; |
1105 | ||
1106 | hw->io_ports.ctl_addr = base + 0x160; | |
5c58666f BZ |
1107 | } |
1108 | ||
1da177e4 LT |
1109 | /* |
1110 | * Attach to a macio probed interface | |
1111 | */ | |
1112 | static int __devinit | |
5e655772 | 1113 | pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
1114 | { |
1115 | void __iomem *base; | |
1116 | unsigned long regbase; | |
1da177e4 | 1117 | pmac_ide_hwif_t *pmif; |
939b0f1d | 1118 | int irq, rc; |
57c802e8 | 1119 | hw_regs_t hw; |
1da177e4 | 1120 | |
5297a3e5 BZ |
1121 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); |
1122 | if (pmif == NULL) | |
1123 | return -ENOMEM; | |
1124 | ||
cc5d0189 | 1125 | if (macio_resource_count(mdev) == 0) { |
939b0f1d BZ |
1126 | printk(KERN_WARNING "ide-pmac: no address for %s\n", |
1127 | mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1128 | rc = -ENXIO; |
1129 | goto out_free_pmif; | |
1da177e4 LT |
1130 | } |
1131 | ||
1132 | /* Request memory resource for IO ports */ | |
1133 | if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) { | |
939b0f1d BZ |
1134 | printk(KERN_ERR "ide-pmac: can't request MMIO resource for " |
1135 | "%s!\n", mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1136 | rc = -EBUSY; |
1137 | goto out_free_pmif; | |
1da177e4 LT |
1138 | } |
1139 | ||
1140 | /* XXX This is bogus. Should be fixed in the registry by checking | |
1141 | * the kind of host interrupt controller, a bit like gatwick | |
1142 | * fixes in irq.c. That works well enough for the single case | |
1143 | * where that happens though... | |
1144 | */ | |
1145 | if (macio_irq_count(mdev) == 0) { | |
939b0f1d BZ |
1146 | printk(KERN_WARNING "ide-pmac: no intrs for device %s, using " |
1147 | "13\n", mdev->ofdev.node->full_name); | |
69917c26 | 1148 | irq = irq_create_mapping(NULL, 13); |
1da177e4 LT |
1149 | } else |
1150 | irq = macio_irq(mdev, 0); | |
1151 | ||
1152 | base = ioremap(macio_resource_start(mdev, 0), 0x400); | |
1153 | regbase = (unsigned long) base; | |
1154 | ||
1da177e4 LT |
1155 | pmif->mdev = mdev; |
1156 | pmif->node = mdev->ofdev.node; | |
1157 | pmif->regbase = regbase; | |
1158 | pmif->irq = irq; | |
1159 | pmif->kauai_fcr = NULL; | |
53846574 | 1160 | |
1da177e4 LT |
1161 | if (macio_resource_count(mdev) >= 2) { |
1162 | if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) | |
939b0f1d BZ |
1163 | printk(KERN_WARNING "ide-pmac: can't request DMA " |
1164 | "resource for %s!\n", | |
1165 | mdev->ofdev.node->full_name); | |
1da177e4 LT |
1166 | else |
1167 | pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); | |
1168 | } else | |
1169 | pmif->dma_regs = NULL; | |
53846574 | 1170 | |
7b8797ac | 1171 | dev_set_drvdata(&mdev->ofdev.dev, pmif); |
1da177e4 | 1172 | |
57c802e8 | 1173 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1174 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 | 1175 | hw.irq = irq; |
c56c5648 BZ |
1176 | hw.dev = &mdev->bus->pdev->dev; |
1177 | hw.parent = &mdev->ofdev.dev; | |
57c802e8 | 1178 | |
b36ba532 | 1179 | rc = pmac_ide_setup_device(pmif, &hw); |
1da177e4 LT |
1180 | if (rc != 0) { |
1181 | /* The inteface is released to the common IDE layer */ | |
1182 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1183 | iounmap(base); | |
ed908fa1 | 1184 | if (pmif->dma_regs) { |
1da177e4 | 1185 | iounmap(pmif->dma_regs); |
ed908fa1 BZ |
1186 | macio_release_resource(mdev, 1); |
1187 | } | |
1da177e4 | 1188 | macio_release_resource(mdev, 0); |
5297a3e5 | 1189 | kfree(pmif); |
1da177e4 LT |
1190 | } |
1191 | ||
1192 | return rc; | |
5297a3e5 BZ |
1193 | |
1194 | out_free_pmif: | |
1195 | kfree(pmif); | |
1196 | return rc; | |
1da177e4 LT |
1197 | } |
1198 | ||
1199 | static int | |
8b4b8a24 | 1200 | pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) |
1da177e4 | 1201 | { |
7b8797ac BZ |
1202 | pmac_ide_hwif_t *pmif = |
1203 | (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1204 | int rc = 0; | |
1da177e4 | 1205 | |
8b4b8a24 | 1206 | if (mesg.event != mdev->ofdev.dev.power.power_state.event |
3a2d5b70 | 1207 | && (mesg.event & PM_EVENT_SLEEP)) { |
7b8797ac | 1208 | rc = pmac_ide_do_suspend(pmif); |
1da177e4 | 1209 | if (rc == 0) |
8b4b8a24 | 1210 | mdev->ofdev.dev.power.power_state = mesg; |
1da177e4 LT |
1211 | } |
1212 | ||
1213 | return rc; | |
1214 | } | |
1215 | ||
1216 | static int | |
1217 | pmac_ide_macio_resume(struct macio_dev *mdev) | |
1218 | { | |
7b8797ac BZ |
1219 | pmac_ide_hwif_t *pmif = |
1220 | (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1221 | int rc = 0; | |
1222 | ||
ca078bae | 1223 | if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) { |
7b8797ac | 1224 | rc = pmac_ide_do_resume(pmif); |
1da177e4 | 1225 | if (rc == 0) |
829ca9a3 | 1226 | mdev->ofdev.dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1227 | } |
1228 | ||
1229 | return rc; | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * Attach to a PCI probed interface | |
1234 | */ | |
1235 | static int __devinit | |
1236 | pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) | |
1237 | { | |
1da177e4 LT |
1238 | struct device_node *np; |
1239 | pmac_ide_hwif_t *pmif; | |
1240 | void __iomem *base; | |
1241 | unsigned long rbase, rlen; | |
939b0f1d | 1242 | int rc; |
57c802e8 | 1243 | hw_regs_t hw; |
1da177e4 LT |
1244 | |
1245 | np = pci_device_to_OF_node(pdev); | |
1246 | if (np == NULL) { | |
1247 | printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n"); | |
1248 | return -ENODEV; | |
1249 | } | |
5297a3e5 BZ |
1250 | |
1251 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); | |
1252 | if (pmif == NULL) | |
1253 | return -ENOMEM; | |
1254 | ||
1da177e4 | 1255 | if (pci_enable_device(pdev)) { |
939b0f1d BZ |
1256 | printk(KERN_WARNING "ide-pmac: Can't enable PCI device for " |
1257 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1258 | rc = -ENXIO; |
1259 | goto out_free_pmif; | |
1da177e4 LT |
1260 | } |
1261 | pci_set_master(pdev); | |
1262 | ||
1263 | if (pci_request_regions(pdev, "Kauai ATA")) { | |
939b0f1d BZ |
1264 | printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for " |
1265 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1266 | rc = -ENXIO; |
1267 | goto out_free_pmif; | |
1da177e4 LT |
1268 | } |
1269 | ||
1da177e4 LT |
1270 | pmif->mdev = NULL; |
1271 | pmif->node = np; | |
1272 | ||
1273 | rbase = pci_resource_start(pdev, 0); | |
1274 | rlen = pci_resource_len(pdev, 0); | |
1275 | ||
1276 | base = ioremap(rbase, rlen); | |
1277 | pmif->regbase = (unsigned long) base + 0x2000; | |
1da177e4 | 1278 | pmif->dma_regs = base + 0x1000; |
1da177e4 LT |
1279 | pmif->kauai_fcr = base; |
1280 | pmif->irq = pdev->irq; | |
1281 | ||
7b8797ac | 1282 | pci_set_drvdata(pdev, pmif); |
1da177e4 | 1283 | |
57c802e8 | 1284 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1285 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 BZ |
1286 | hw.irq = pdev->irq; |
1287 | hw.dev = &pdev->dev; | |
1288 | ||
b36ba532 | 1289 | rc = pmac_ide_setup_device(pmif, &hw); |
1da177e4 LT |
1290 | if (rc != 0) { |
1291 | /* The inteface is released to the common IDE layer */ | |
1292 | pci_set_drvdata(pdev, NULL); | |
1293 | iounmap(base); | |
1da177e4 | 1294 | pci_release_regions(pdev); |
5297a3e5 | 1295 | kfree(pmif); |
1da177e4 LT |
1296 | } |
1297 | ||
1298 | return rc; | |
5297a3e5 BZ |
1299 | |
1300 | out_free_pmif: | |
1301 | kfree(pmif); | |
1302 | return rc; | |
1da177e4 LT |
1303 | } |
1304 | ||
1305 | static int | |
8b4b8a24 | 1306 | pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1da177e4 | 1307 | { |
7b8797ac BZ |
1308 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); |
1309 | int rc = 0; | |
1310 | ||
8b4b8a24 | 1311 | if (mesg.event != pdev->dev.power.power_state.event |
3a2d5b70 | 1312 | && (mesg.event & PM_EVENT_SLEEP)) { |
7b8797ac | 1313 | rc = pmac_ide_do_suspend(pmif); |
1da177e4 | 1314 | if (rc == 0) |
8b4b8a24 | 1315 | pdev->dev.power.power_state = mesg; |
1da177e4 LT |
1316 | } |
1317 | ||
1318 | return rc; | |
1319 | } | |
1320 | ||
1321 | static int | |
1322 | pmac_ide_pci_resume(struct pci_dev *pdev) | |
1323 | { | |
7b8797ac BZ |
1324 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); |
1325 | int rc = 0; | |
1326 | ||
ca078bae | 1327 | if (pdev->dev.power.power_state.event != PM_EVENT_ON) { |
7b8797ac | 1328 | rc = pmac_ide_do_resume(pmif); |
1da177e4 | 1329 | if (rc == 0) |
829ca9a3 | 1330 | pdev->dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1331 | } |
1332 | ||
1333 | return rc; | |
1334 | } | |
1335 | ||
5e655772 | 1336 | static struct of_device_id pmac_ide_macio_match[] = |
1da177e4 LT |
1337 | { |
1338 | { | |
1339 | .name = "IDE", | |
1da177e4 LT |
1340 | }, |
1341 | { | |
1342 | .name = "ATA", | |
1da177e4 LT |
1343 | }, |
1344 | { | |
1da177e4 | 1345 | .type = "ide", |
1da177e4 LT |
1346 | }, |
1347 | { | |
1da177e4 | 1348 | .type = "ata", |
1da177e4 LT |
1349 | }, |
1350 | {}, | |
1351 | }; | |
1352 | ||
1353 | static struct macio_driver pmac_ide_macio_driver = | |
1354 | { | |
1355 | .name = "ide-pmac", | |
1356 | .match_table = pmac_ide_macio_match, | |
1357 | .probe = pmac_ide_macio_attach, | |
1358 | .suspend = pmac_ide_macio_suspend, | |
1359 | .resume = pmac_ide_macio_resume, | |
1360 | }; | |
1361 | ||
9cbcc5e3 BZ |
1362 | static const struct pci_device_id pmac_ide_pci_match[] = { |
1363 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, | |
1364 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, | |
1365 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, | |
1366 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, | |
1367 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, | |
71e4eda8 | 1368 | {}, |
1da177e4 LT |
1369 | }; |
1370 | ||
1371 | static struct pci_driver pmac_ide_pci_driver = { | |
1372 | .name = "ide-pmac", | |
1373 | .id_table = pmac_ide_pci_match, | |
1374 | .probe = pmac_ide_pci_attach, | |
1375 | .suspend = pmac_ide_pci_suspend, | |
1376 | .resume = pmac_ide_pci_resume, | |
1377 | }; | |
1378 | MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match); | |
1379 | ||
9e5755bc | 1380 | int __init pmac_ide_probe(void) |
1da177e4 | 1381 | { |
9e5755bc AM |
1382 | int error; |
1383 | ||
e8222502 | 1384 | if (!machine_is(powermac)) |
9e5755bc | 1385 | return -ENODEV; |
1da177e4 LT |
1386 | |
1387 | #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST | |
9e5755bc AM |
1388 | error = pci_register_driver(&pmac_ide_pci_driver); |
1389 | if (error) | |
1390 | goto out; | |
1391 | error = macio_register_driver(&pmac_ide_macio_driver); | |
1392 | if (error) { | |
1393 | pci_unregister_driver(&pmac_ide_pci_driver); | |
1394 | goto out; | |
1395 | } | |
1da177e4 | 1396 | #else |
9e5755bc AM |
1397 | error = macio_register_driver(&pmac_ide_macio_driver); |
1398 | if (error) | |
1399 | goto out; | |
1400 | error = pci_register_driver(&pmac_ide_pci_driver); | |
1401 | if (error) { | |
1402 | macio_unregister_driver(&pmac_ide_macio_driver); | |
1403 | goto out; | |
1404 | } | |
1beb6a7d | 1405 | #endif |
9e5755bc AM |
1406 | out: |
1407 | return error; | |
1da177e4 LT |
1408 | } |
1409 | ||
1da177e4 LT |
1410 | /* |
1411 | * pmac_ide_build_dmatable builds the DBDMA command list | |
1412 | * for a transfer and sets the DBDMA channel to point to it. | |
1413 | */ | |
22981694 | 1414 | static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) |
1da177e4 | 1415 | { |
7b8797ac BZ |
1416 | ide_hwif_t *hwif = drive->hwif; |
1417 | pmac_ide_hwif_t *pmif = | |
1418 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 | 1419 | struct dbdma_cmd *table; |
1da177e4 LT |
1420 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; |
1421 | struct scatterlist *sg; | |
22981694 BZ |
1422 | int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE); |
1423 | int i = cmd->sg_nents, count = 0; | |
1da177e4 LT |
1424 | |
1425 | /* DMA table is already aligned */ | |
1426 | table = (struct dbdma_cmd *) pmif->dma_table_cpu; | |
1427 | ||
1428 | /* Make sure DMA controller is stopped (necessary ?) */ | |
1429 | writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); | |
1430 | while (readl(&dma->status) & RUN) | |
1431 | udelay(1); | |
1432 | ||
1da177e4 LT |
1433 | /* Build DBDMA commands list */ |
1434 | sg = hwif->sg_table; | |
1435 | while (i && sg_dma_len(sg)) { | |
1436 | u32 cur_addr; | |
1437 | u32 cur_len; | |
1438 | ||
1439 | cur_addr = sg_dma_address(sg); | |
1440 | cur_len = sg_dma_len(sg); | |
1441 | ||
1442 | if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) { | |
1443 | if (pmif->broken_dma_warn == 0) { | |
aca38a51 | 1444 | printk(KERN_WARNING "%s: DMA on non aligned address, " |
1da177e4 LT |
1445 | "switching to PIO on Ohare chipset\n", drive->name); |
1446 | pmif->broken_dma_warn = 1; | |
1447 | } | |
11998b31 | 1448 | return 0; |
1da177e4 LT |
1449 | } |
1450 | while (cur_len) { | |
1451 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
1452 | ||
1453 | if (count++ >= MAX_DCMDS) { | |
1454 | printk(KERN_WARNING "%s: DMA table too small\n", | |
1455 | drive->name); | |
11998b31 | 1456 | return 0; |
1da177e4 LT |
1457 | } |
1458 | st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE); | |
1459 | st_le16(&table->req_count, tc); | |
1460 | st_le32(&table->phy_addr, cur_addr); | |
1461 | table->cmd_dep = 0; | |
1462 | table->xfer_status = 0; | |
1463 | table->res_count = 0; | |
1464 | cur_addr += tc; | |
1465 | cur_len -= tc; | |
1466 | ++table; | |
1467 | } | |
55c16a70 | 1468 | sg = sg_next(sg); |
1da177e4 LT |
1469 | i--; |
1470 | } | |
1471 | ||
1472 | /* convert the last command to an input/output last command */ | |
1473 | if (count) { | |
1474 | st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST); | |
1475 | /* add the stop command to the end of the list */ | |
1476 | memset(table, 0, sizeof(struct dbdma_cmd)); | |
1477 | st_le16(&table->command, DBDMA_STOP); | |
1478 | mb(); | |
1479 | writel(hwif->dmatable_dma, &dma->cmdptr); | |
1480 | return 1; | |
1481 | } | |
1482 | ||
1483 | printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name); | |
f6fb786d | 1484 | |
1da177e4 LT |
1485 | return 0; /* revert to PIO for this request */ |
1486 | } | |
1487 | ||
1da177e4 LT |
1488 | /* |
1489 | * Prepare a DMA transfer. We build the DMA table, adjust the timings for | |
1490 | * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion | |
1491 | */ | |
22981694 | 1492 | static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) |
1da177e4 | 1493 | { |
898ec223 | 1494 | ide_hwif_t *hwif = drive->hwif; |
7b8797ac BZ |
1495 | pmac_ide_hwif_t *pmif = |
1496 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
9055ba3e | 1497 | u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4); |
22981694 | 1498 | u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE); |
1da177e4 | 1499 | |
11998b31 | 1500 | if (pmac_ide_build_dmatable(drive, cmd) == 0) |
1da177e4 | 1501 | return 1; |
1da177e4 LT |
1502 | |
1503 | /* Apple adds 60ns to wrDataSetup on reads */ | |
1504 | if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { | |
22981694 | 1505 | writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL), |
1da177e4 LT |
1506 | PMAC_IDE_REG(IDE_TIMING_CONFIG)); |
1507 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1508 | } | |
1509 | ||
1da177e4 LT |
1510 | return 0; |
1511 | } | |
1512 | ||
1da177e4 LT |
1513 | /* |
1514 | * Kick the DMA controller into life after the DMA command has been issued | |
1515 | * to the drive. | |
1516 | */ | |
aacaf9bd | 1517 | static void |
1da177e4 LT |
1518 | pmac_ide_dma_start(ide_drive_t *drive) |
1519 | { | |
7b8797ac BZ |
1520 | ide_hwif_t *hwif = drive->hwif; |
1521 | pmac_ide_hwif_t *pmif = | |
1522 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1523 | volatile struct dbdma_regs __iomem *dma; |
1524 | ||
1525 | dma = pmif->dma_regs; | |
1526 | ||
1527 | writel((RUN << 16) | RUN, &dma->control); | |
1528 | /* Make sure it gets to the controller right now */ | |
1529 | (void)readl(&dma->control); | |
1530 | } | |
1531 | ||
1532 | /* | |
1533 | * After a DMA transfer, make sure the controller is stopped | |
1534 | */ | |
aacaf9bd | 1535 | static int |
1da177e4 LT |
1536 | pmac_ide_dma_end (ide_drive_t *drive) |
1537 | { | |
7b8797ac BZ |
1538 | ide_hwif_t *hwif = drive->hwif; |
1539 | pmac_ide_hwif_t *pmif = | |
1540 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
9055ba3e | 1541 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; |
1da177e4 | 1542 | u32 dstat; |
1da177e4 | 1543 | |
1da177e4 LT |
1544 | dstat = readl(&dma->status); |
1545 | writel(((RUN|WAKE|DEAD) << 16), &dma->control); | |
f5e0b5ec | 1546 | |
1da177e4 LT |
1547 | /* verify good dma status. we don't check for ACTIVE beeing 0. We should... |
1548 | * in theory, but with ATAPI decices doing buffer underruns, that would | |
1549 | * cause us to disable DMA, which isn't what we want | |
1550 | */ | |
1551 | return (dstat & (RUN|DEAD)) != RUN; | |
1552 | } | |
1553 | ||
1554 | /* | |
1555 | * Check out that the interrupt we got was for us. We can't always know this | |
1556 | * for sure with those Apple interfaces (well, we could on the recent ones but | |
1557 | * that's not implemented yet), on the other hand, we don't have shared interrupts | |
1558 | * so it's not really a problem | |
1559 | */ | |
aacaf9bd | 1560 | static int |
1da177e4 LT |
1561 | pmac_ide_dma_test_irq (ide_drive_t *drive) |
1562 | { | |
7b8797ac BZ |
1563 | ide_hwif_t *hwif = drive->hwif; |
1564 | pmac_ide_hwif_t *pmif = | |
1565 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
9055ba3e | 1566 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; |
1da177e4 LT |
1567 | unsigned long status, timeout; |
1568 | ||
1da177e4 LT |
1569 | /* We have to things to deal with here: |
1570 | * | |
1571 | * - The dbdma won't stop if the command was started | |
1572 | * but completed with an error without transferring all | |
1573 | * datas. This happens when bad blocks are met during | |
1574 | * a multi-block transfer. | |
1575 | * | |
1576 | * - The dbdma fifo hasn't yet finished flushing to | |
1577 | * to system memory when the disk interrupt occurs. | |
1578 | * | |
1579 | */ | |
1580 | ||
1581 | /* If ACTIVE is cleared, the STOP command have passed and | |
1582 | * transfer is complete. | |
1583 | */ | |
1584 | status = readl(&dma->status); | |
1585 | if (!(status & ACTIVE)) | |
1586 | return 1; | |
1da177e4 LT |
1587 | |
1588 | /* If dbdma didn't execute the STOP command yet, the | |
1589 | * active bit is still set. We consider that we aren't | |
1590 | * sharing interrupts (which is hopefully the case with | |
1591 | * those controllers) and so we just try to flush the | |
1592 | * channel for pending data in the fifo | |
1593 | */ | |
1594 | udelay(1); | |
1595 | writel((FLUSH << 16) | FLUSH, &dma->control); | |
1596 | timeout = 0; | |
1597 | for (;;) { | |
1598 | udelay(1); | |
1599 | status = readl(&dma->status); | |
1600 | if ((status & FLUSH) == 0) | |
1601 | break; | |
1602 | if (++timeout > 100) { | |
1603 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
898ec223 | 1604 | timeout flushing channel\n", hwif->index); |
1da177e4 LT |
1605 | break; |
1606 | } | |
1607 | } | |
1608 | return 1; | |
1609 | } | |
1610 | ||
15ce926a | 1611 | static void pmac_ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 1612 | { |
1da177e4 LT |
1613 | } |
1614 | ||
841d2a9b SS |
1615 | static void |
1616 | pmac_ide_dma_lost_irq (ide_drive_t *drive) | |
1da177e4 | 1617 | { |
7b8797ac BZ |
1618 | ide_hwif_t *hwif = drive->hwif; |
1619 | pmac_ide_hwif_t *pmif = | |
1620 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
9055ba3e BZ |
1621 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; |
1622 | unsigned long status = readl(&dma->status); | |
1da177e4 | 1623 | |
1da177e4 | 1624 | printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status); |
1da177e4 LT |
1625 | } |
1626 | ||
f37afdac | 1627 | static const struct ide_dma_ops pmac_dma_ops = { |
5e37bdc0 BZ |
1628 | .dma_host_set = pmac_ide_dma_host_set, |
1629 | .dma_setup = pmac_ide_dma_setup, | |
5e37bdc0 BZ |
1630 | .dma_start = pmac_ide_dma_start, |
1631 | .dma_end = pmac_ide_dma_end, | |
1632 | .dma_test_irq = pmac_ide_dma_test_irq, | |
5e37bdc0 BZ |
1633 | .dma_lost_irq = pmac_ide_dma_lost_irq, |
1634 | }; | |
1635 | ||
1da177e4 LT |
1636 | /* |
1637 | * Allocate the data structures needed for using DMA with an interface | |
1638 | * and fill the proper list of functions pointers | |
1639 | */ | |
0d071922 BZ |
1640 | static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, |
1641 | const struct ide_port_info *d) | |
1da177e4 | 1642 | { |
7b8797ac BZ |
1643 | pmac_ide_hwif_t *pmif = |
1644 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
36501650 BZ |
1645 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1646 | ||
1da177e4 LT |
1647 | /* We won't need pci_dev if we switch to generic consistent |
1648 | * DMA routines ... | |
1649 | */ | |
0d071922 | 1650 | if (dev == NULL || pmif->dma_regs == 0) |
c413b9b9 | 1651 | return -ENODEV; |
1da177e4 LT |
1652 | /* |
1653 | * Allocate space for the DBDMA commands. | |
1654 | * The +2 is +1 for the stop command and +1 to allow for | |
1655 | * aligning the start address to a multiple of 16 bytes. | |
1656 | */ | |
1657 | pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent( | |
36501650 | 1658 | dev, |
1da177e4 LT |
1659 | (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), |
1660 | &hwif->dmatable_dma); | |
1661 | if (pmif->dma_table_cpu == NULL) { | |
1662 | printk(KERN_ERR "%s: unable to allocate DMA command list\n", | |
1663 | hwif->name); | |
c413b9b9 | 1664 | return -ENOMEM; |
1da177e4 LT |
1665 | } |
1666 | ||
4f52a329 BZ |
1667 | hwif->sg_max_nents = MAX_DCMDS; |
1668 | ||
c413b9b9 | 1669 | return 0; |
1da177e4 | 1670 | } |
ade2daf9 BZ |
1671 | |
1672 | module_init(pmac_ide_probe); | |
de9facbf AB |
1673 | |
1674 | MODULE_LICENSE("GPL"); |