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ide-pmac: don't check kauai_lookup_timing() return value
[deliverable/linux.git] / drivers / ide / ppc / pmac.c
CommitLineData
1da177e4 1/*
f30c2269 2 * linux/drivers/ide/ppc/pmac.c
1da177e4
LT		 3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
c15d5d43 9 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * Some code taken from drivers/ide/ide-dma.c:
17 *
18 * Copyright (c) 1995-1998 Mark Lord
19 *
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
23 * big table
24 *
25 */
1da177e4
LT		 26#include <linux/types.h>
27#include <linux/kernel.h>
1da177e4
LT		 28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/ide.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <linux/pci.h>
34#include <linux/adb.h>
35#include <linux/pmu.h>
36#include <linux/scatterlist.h>
37
38#include <asm/prom.h>
39#include <asm/io.h>
40#include <asm/dbdma.h>
41#include <asm/ide.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/pmac_feature.h>
45#include <asm/sections.h>
46#include <asm/irq.h>
47
48#ifndef CONFIG_PPC64
49#include <asm/mediabay.h>
50#endif
51
9e5755bc 52#include "../ide-timing.h"
1da177e4
LT		 53
54#undef IDE_PMAC_DEBUG
55
56#define DMA_WAIT_TIMEOUT 50
57
58typedef struct pmac_ide_hwif {
59 unsigned long regbase;
60 int irq;
61 int kind;
62 int aapl_bus_id;
63 unsigned cable_80 : 1;
64 unsigned mediabay : 1;
65 unsigned broken_dma : 1;
66 unsigned broken_dma_warn : 1;
67 struct device_node* node;
68 struct macio_dev *mdev;
69 u32 timings[4];
70 volatile u32 __iomem * *kauai_fcr;
71#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
76 */
77 volatile struct dbdma_regs __iomem * dma_regs;
78 struct dbdma_cmd* dma_table_cpu;
79#endif
80
81} pmac_ide_hwif_t;
82
aacaf9bd 83static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 84static int pmac_ide_count;
85
86enum {
87 controller_ohare, /* OHare based */
88 controller_heathrow, /* Heathrow/Paddington */
89 controller_kl_ata3, /* KeyLargo ATA-3 */
90 controller_kl_ata4, /* KeyLargo ATA-4 */
91 controller_un_ata6, /* UniNorth2 ATA-6 */
92 controller_k2_ata6, /* K2 ATA-6 */
93 controller_sh_ata6, /* Shasta ATA-6 */
94};
95
96static const char* model_name[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
104};
105
106/*
107 * Extra registers, both 32-bit little-endian
108 */
109#define IDE_TIMING_CONFIG 0x200
110#define IDE_INTERRUPT 0x300
111
112/* Kauai (U2) ATA has different register setup */
113#define IDE_KAUAI_PIO_CONFIG 0x200
114#define IDE_KAUAI_ULTRA_CONFIG 0x210
115#define IDE_KAUAI_POLL_CONFIG 0x220
116
117/*
118 * Timing configuration register definitions
119 */
120
121/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
126
127/* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
130 */
131#define TR_133_PIOREG_PIO_MASK 0xff000fff
132#define TR_133_PIOREG_MDMA_MASK 0x00fff800
133#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134#define TR_133_UDMAREG_UDMA_EN 0x00000001
135
136/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
142 *
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
145 *
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
151 */
152#define TR_100_PIOREG_PIO_MASK 0xff000fff
153#define TR_100_PIOREG_MDMA_MASK 0x00fff000
154#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155#define TR_100_UDMAREG_UDMA_EN 0x00000001
156
157
158/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
161 *
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
170 * min value of 45ns.
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
172 * reads.
173 */
174#define TR_66_UDMA_MASK 0xfff00000
175#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177#define TR_66_UDMA_ADDRSETUP_SHIFT 29
178#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179#define TR_66_UDMA_RDY2PAUS_SHIFT 25
180#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181#define TR_66_UDMA_WRDATASETUP_SHIFT 21
182#define TR_66_MDMA_MASK 0x000ffc00
183#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184#define TR_66_MDMA_RECOVERY_SHIFT 15
185#define TR_66_MDMA_ACCESS_MASK 0x00007c00
186#define TR_66_MDMA_ACCESS_SHIFT 10
187#define TR_66_PIO_MASK 0x000003ff
188#define TR_66_PIO_RECOVERY_MASK 0x000003e0
189#define TR_66_PIO_RECOVERY_SHIFT 5
190#define TR_66_PIO_ACCESS_MASK 0x0000001f
191#define TR_66_PIO_ACCESS_SHIFT 0
192
193/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
195 *
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
203 */
204#define TR_33_MDMA_MASK 0x003ff800
205#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206#define TR_33_MDMA_RECOVERY_SHIFT 16
207#define TR_33_MDMA_ACCESS_MASK 0x0000f800
208#define TR_33_MDMA_ACCESS_SHIFT 11
209#define TR_33_MDMA_HALFTICK 0x00200000
210#define TR_33_PIO_MASK 0x000007ff
211#define TR_33_PIO_E 0x00000400
212#define TR_33_PIO_RECOVERY_MASK 0x000003e0
213#define TR_33_PIO_RECOVERY_SHIFT 5
214#define TR_33_PIO_ACCESS_MASK 0x0000001f
215#define TR_33_PIO_ACCESS_SHIFT 0
216
217/*
218 * Interrupt register definitions
219 */
220#define IDE_INTR_DMA 0x80000000
221#define IDE_INTR_DEVICE 0x40000000
222
223/*
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
225 */
226#define KAUAI_FCR_UATA_MAGIC 0x00000004
227#define KAUAI_FCR_UATA_RESET_N 0x00000002
228#define KAUAI_FCR_UATA_ENABLE 0x00000001
229
230#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
231
232/* Rounded Multiword DMA timings
233 *
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
237 */
238struct mdma_timings_t {
239 int accessTime;
240 int recoveryTime;
241 int cycleTime;
242};
243
aacaf9bd 244struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 245{
246 { 240, 240, 480 },
247 { 180, 180, 360 },
248 { 135, 135, 270 },
249 { 120, 120, 240 },
250 { 105, 105, 210 },
251 { 90, 90, 180 },
252 { 75, 75, 150 },
253 { 75, 45, 120 },
254 { 0, 0, 0 }
255};
256
aacaf9bd 257struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 258{
259 { 240, 240, 480 },
260 { 180, 180, 360 },
261 { 150, 150, 300 },
262 { 120, 120, 240 },
263 { 90, 120, 210 },
264 { 90, 90, 180 },
265 { 90, 60, 150 },
266 { 90, 30, 120 },
267 { 0, 0, 0 }
268};
269
aacaf9bd 270struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 271{
272 { 240, 240, 480 },
273 { 180, 180, 360 },
274 { 135, 135, 270 },
275 { 120, 120, 240 },
276 { 105, 105, 210 },
277 { 90, 90, 180 },
278 { 90, 75, 165 },
279 { 75, 45, 120 },
280 { 0, 0, 0 }
281};
282
283/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
284struct {
285 int addrSetup; /* ??? */
286 int rdy2pause;
287 int wrDataSetup;
aacaf9bd 288} kl66_udma_timings[] =
1da177e4
LT		 289{
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
295};
296
297/* UniNorth 2 ATA/100 timings */
298struct kauai_timing {
299 int cycle_time;
300 u32 timing_reg;
301};
302
aacaf9bd 303static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 304{
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
c15d5d43
BZ		 315 { 120 , 0x04000148 },
316 { 0 , 0 },
1da177e4
LT		 317};
318
aacaf9bd 319static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
aacaf9bd 333static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
aacaf9bd 344static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
c15d5d43
BZ		 356 { 120 , 0x0400010a },
357 { 0 , 0 },
1da177e4
LT		 358};
359
aacaf9bd 360static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 361{
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
371 { 0 , 0 },
372};
373
aacaf9bd 374static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 375{
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
383 { 0 , 0 },
384};
385
386
387static inline u32
388kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
389{
390 int i;
391
392 for (i=0; table[i].cycle_time; i++)
393 if (cycle_time > table[i+1].cycle_time)
394 return table[i].timing_reg;
90a87ea4 395 BUG();
1da177e4
LT		 396 return 0;
397}
398
399/* allow up to 256 DBDMA commands per xfer */
400#define MAX_DCMDS 256
401
402/*
403 * Wait 1s for disk to answer on IDE bus after a hard reset
404 * of the device (via GPIO/FCR).
405 *
406 * Some devices seem to "pollute" the bus even after dropping
407 * the BSY bit (typically some combo drives slave on the UDMA
408 * bus) after a hard reset. Since we hard reset all drives on
409 * KeyLargo ATA66, we have to keep that delay around. I may end
410 * up not hard resetting anymore on these and keep the delay only
411 * for older interfaces instead (we have to reset when coming
412 * from MacOS...) --BenH.
413 */
414#define IDE_WAKEUP_DELAY (1*HZ)
415
416static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
417static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
1da177e4
LT		 418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
1da177e4
LT		 423/*
424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
426 */
aacaf9bd 427void
1da177e4
LT		 428pmac_ide_init_hwif_ports(hw_regs_t *hw,
429 unsigned long data_port, unsigned long ctrl_port,
430 int *irq)
431{
432 int i, ix;
433
434 if (data_port == 0)
435 return;
436
437 for (ix = 0; ix < MAX_HWIFS; ++ix)
438 if (data_port == pmac_ide[ix].regbase)
439 break;
440
441 if (ix >= MAX_HWIFS) {
442 /* Probably a PCI interface... */
443 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
444 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
445 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
446 return;
447 }
448
449 for (i = 0; i < 8; ++i)
450 hw->io_ports[i] = data_port + i * 0x10;
451 hw->io_ports[8] = data_port + 0x160;
452
453 if (irq != NULL)
454 *irq = pmac_ide[ix].irq;
22192ccd
BH		 455
456 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
1da177e4
LT		 457}
458
459#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
460
461/*
462 * Apply the timings of the proper unit (master/slave) to the shared
463 * timing register when selecting that unit. This version is for
464 * ASICs with a single timing register
465 */
aacaf9bd 466static void
1da177e4
LT		 467pmac_ide_selectproc(ide_drive_t *drive)
468{
469 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
470
471 if (pmif == NULL)
472 return;
473
474 if (drive->select.b.unit & 0x01)
475 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 else
477 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
478 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
479}
480
481/*
482 * Apply the timings of the proper unit (master/slave) to the shared
483 * timing register when selecting that unit. This version is for
484 * ASICs with a dual timing register (Kauai)
485 */
aacaf9bd 486static void
1da177e4
LT		 487pmac_ide_kauai_selectproc(ide_drive_t *drive)
488{
489 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
490
491 if (pmif == NULL)
492 return;
493
494 if (drive->select.b.unit & 0x01) {
495 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
497 } else {
498 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
499 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
500 }
501 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
502}
503
504/*
505 * Force an update of controller timing values for a given drive
506 */
aacaf9bd 507static void
1da177e4
LT		 508pmac_ide_do_update_timings(ide_drive_t *drive)
509{
510 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
511
512 if (pmif == NULL)
513 return;
514
515 if (pmif->kind == controller_sh_ata6 ||
516 pmif->kind == controller_un_ata6 ||
517 pmif->kind == controller_k2_ata6)
518 pmac_ide_kauai_selectproc(drive);
519 else
520 pmac_ide_selectproc(drive);
521}
522
523static void
524pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
525{
526 u32 tmp;
527
528 writeb(value, (void __iomem *) port);
529 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
530}
531
532/*
533 * Send the SET_FEATURE IDE command to the drive and update drive->id with
534 * the new state. We currently don't use the generic routine as it used to
535 * cause various trouble, especially with older mediabays.
536 * This code is sometimes triggering a spurrious interrupt though, I need
537 * to sort that out sooner or later and see if I can finally get the
538 * common version to work properly in all cases
539 */
aacaf9bd 540static int
1da177e4
LT		 541pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
542{
543 ide_hwif_t *hwif = HWIF(drive);
544 int result = 1;
545
546 disable_irq_nosync(hwif->irq);
547 udelay(1);
548 SELECT_DRIVE(drive);
549 SELECT_MASK(drive, 0);
550 udelay(1);
551 /* Get rid of pending error state */
552 (void) hwif->INB(IDE_STATUS_REG);
553 /* Timeout bumped for some powerbooks */
554 if (wait_for_ready(drive, 2000)) {
555 /* Timeout bumped for some powerbooks */
556 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
557 "before SET_FEATURE!\n", drive->name);
558 goto out;
559 }
560 udelay(10);
561 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
562 hwif->OUTB(command, IDE_NSECTOR_REG);
563 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
564 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
565 udelay(1);
566 /* Timeout bumped for some powerbooks */
567 result = wait_for_ready(drive, 2000);
568 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
569 if (result)
570 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
571 "after SET_FEATURE !\n", drive->name);
572out:
573 SELECT_MASK(drive, 0);
574 if (result == 0) {
575 drive->id->dma_ultra &= ~0xFF00;
576 drive->id->dma_mword &= ~0x0F00;
577 drive->id->dma_1word &= ~0x0F00;
578 switch(command) {
579 case XFER_UDMA_7:
580 drive->id->dma_ultra |= 0x8080; break;
581 case XFER_UDMA_6:
582 drive->id->dma_ultra |= 0x4040; break;
583 case XFER_UDMA_5:
584 drive->id->dma_ultra |= 0x2020; break;
585 case XFER_UDMA_4:
586 drive->id->dma_ultra |= 0x1010; break;
587 case XFER_UDMA_3:
588 drive->id->dma_ultra |= 0x0808; break;
589 case XFER_UDMA_2:
590 drive->id->dma_ultra |= 0x0404; break;
591 case XFER_UDMA_1:
592 drive->id->dma_ultra |= 0x0202; break;
593 case XFER_UDMA_0:
594 drive->id->dma_ultra |= 0x0101; break;
595 case XFER_MW_DMA_2:
596 drive->id->dma_mword |= 0x0404; break;
597 case XFER_MW_DMA_1:
598 drive->id->dma_mword |= 0x0202; break;
599 case XFER_MW_DMA_0:
600 drive->id->dma_mword |= 0x0101; break;
601 case XFER_SW_DMA_2:
602 drive->id->dma_1word |= 0x0404; break;
603 case XFER_SW_DMA_1:
604 drive->id->dma_1word |= 0x0202; break;
605 case XFER_SW_DMA_0:
606 drive->id->dma_1word |= 0x0101; break;
607 default: break;
608 }
59785c8f
BZ		 609 if (!drive->init_speed)
610 drive->init_speed = command;
611 drive->current_speed = command;
1da177e4
LT		 612 }
613 enable_irq(hwif->irq);
614 return result;
615}
616
617/*
618 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
619 */
aacaf9bd 620static void
26bcb879 621pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 622{
1da177e4
LT		 623 u32 *timings;
624 unsigned accessTicks, recTicks;
625 unsigned accessTime, recTime;
626 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
7dd00083
BZ		 627 unsigned int cycle_time;
628
1da177e4
LT		 629 if (pmif == NULL)
630 return;
631
632 /* which drive is it ? */
633 timings = &pmif->timings[drive->select.b.unit & 0x01];
634
7dd00083 635 cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4
LT		 636
637 switch (pmif->kind) {
638 case controller_sh_ata6: {
639 /* 133Mhz cell */
7dd00083 640 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
1da177e4
LT		 641 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
642 break;
643 }
644 case controller_un_ata6:
645 case controller_k2_ata6: {
646 /* 100Mhz cell */
7dd00083 647 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
1da177e4
LT		 648 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
649 break;
650 }
651 case controller_kl_ata4:
652 /* 66Mhz cell */
7dd00083 653 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 654 - ide_pio_timings[pio].setup_time;
655 recTime = max(recTime, 150U);
656 accessTime = ide_pio_timings[pio].active_time;
657 accessTime = max(accessTime, 150U);
658 accessTicks = SYSCLK_TICKS_66(accessTime);
659 accessTicks = min(accessTicks, 0x1fU);
660 recTicks = SYSCLK_TICKS_66(recTime);
661 recTicks = min(recTicks, 0x1fU);
662 *timings = ((*timings) & ~TR_66_PIO_MASK) |
663 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
664 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
665 break;
666 default: {
667 /* 33Mhz cell */
668 int ebit = 0;
7dd00083 669 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 670 - ide_pio_timings[pio].setup_time;
671 recTime = max(recTime, 150U);
672 accessTime = ide_pio_timings[pio].active_time;
673 accessTime = max(accessTime, 150U);
674 accessTicks = SYSCLK_TICKS(accessTime);
675 accessTicks = min(accessTicks, 0x1fU);
676 accessTicks = max(accessTicks, 4U);
677 recTicks = SYSCLK_TICKS(recTime);
678 recTicks = min(recTicks, 0x1fU);
679 recTicks = max(recTicks, 5U) - 4;
680 if (recTicks > 9) {
681 recTicks--; /* guess, but it's only for PIO0, so... */
682 ebit = 1;
683 }
684 *timings = ((*timings) & ~TR_33_PIO_MASK) |
685 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
686 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
687 if (ebit)
688 *timings |= TR_33_PIO_E;
689 break;
690 }
691 }
692
693#ifdef IDE_PMAC_DEBUG
694 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
695 drive->name, pio, *timings);
696#endif
697
c15d5d43
BZ		 698 if (pmac_ide_do_setfeature(drive, XFER_PIO_0 + pio))
699 return;
700
701 pmac_ide_do_update_timings(drive);
1da177e4
LT		 702}
703
704#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
705
706/*
707 * Calculate KeyLargo ATA/66 UDMA timings
708 */
aacaf9bd 709static int
1da177e4
LT		 710set_timings_udma_ata4(u32 *timings, u8 speed)
711{
712 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
713
714 if (speed > XFER_UDMA_4)
715 return 1;
716
717 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
718 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
719 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
720
721 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
722 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
723 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
724 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
725 TR_66_UDMA_EN;
726#ifdef IDE_PMAC_DEBUG
727 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
728 speed & 0xf, *timings);
729#endif
730
731 return 0;
732}
733
734/*
735 * Calculate Kauai ATA/100 UDMA timings
736 */
aacaf9bd 737static int
1da177e4
LT		 738set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
739{
740 struct ide_timing *t = ide_timing_find_mode(speed);
741 u32 tr;
742
743 if (speed > XFER_UDMA_5 || t == NULL)
744 return 1;
745 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
1da177e4
LT		 746 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
747 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
748
749 return 0;
750}
751
752/*
753 * Calculate Shasta ATA/133 UDMA timings
754 */
aacaf9bd 755static int
1da177e4
LT		 756set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
757{
758 struct ide_timing *t = ide_timing_find_mode(speed);
759 u32 tr;
760
761 if (speed > XFER_UDMA_6 || t == NULL)
762 return 1;
763 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
1da177e4
LT		 764 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
765 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
766
767 return 0;
768}
769
770/*
771 * Calculate MDMA timings for all cells
772 */
aacaf9bd 773static int
1da177e4
LT		 774set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
775 u8 speed, int drive_cycle_time)
776{
777 int cycleTime, accessTime = 0, recTime = 0;
778 unsigned accessTicks, recTicks;
779 struct mdma_timings_t* tm = NULL;
780 int i;
781
782 /* Get default cycle time for mode */
783 switch(speed & 0xf) {
784 case 0: cycleTime = 480; break;
785 case 1: cycleTime = 150; break;
786 case 2: cycleTime = 120; break;
787 default:
788 return 1;
789 }
790 /* Adjust for drive */
791 if (drive_cycle_time && drive_cycle_time > cycleTime)
792 cycleTime = drive_cycle_time;
793 /* OHare limits according to some old Apple sources */
794 if ((intf_type == controller_ohare) && (cycleTime < 150))
795 cycleTime = 150;
796 /* Get the proper timing array for this controller */
797 switch(intf_type) {
798 case controller_sh_ata6:
799 case controller_un_ata6:
800 case controller_k2_ata6:
801 break;
802 case controller_kl_ata4:
803 tm = mdma_timings_66;
804 break;
805 case controller_kl_ata3:
806 tm = mdma_timings_33k;
807 break;
808 default:
809 tm = mdma_timings_33;
810 break;
811 }
812 if (tm != NULL) {
813 /* Lookup matching access & recovery times */
814 i = -1;
815 for (;;) {
816 if (tm[i+1].cycleTime < cycleTime)
817 break;
818 i++;
819 }
820 if (i < 0)
821 return 1;
822 cycleTime = tm[i].cycleTime;
823 accessTime = tm[i].accessTime;
824 recTime = tm[i].recoveryTime;
825
826#ifdef IDE_PMAC_DEBUG
827 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
828 drive->name, cycleTime, accessTime, recTime);
829#endif
830 }
831 switch(intf_type) {
832 case controller_sh_ata6: {
833 /* 133Mhz cell */
834 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
1da177e4
LT		 835 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
836 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
837 }
838 case controller_un_ata6:
839 case controller_k2_ata6: {
840 /* 100Mhz cell */
841 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
1da177e4
LT		 842 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
843 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
844 }
845 break;
846 case controller_kl_ata4:
847 /* 66Mhz cell */
848 accessTicks = SYSCLK_TICKS_66(accessTime);
849 accessTicks = min(accessTicks, 0x1fU);
850 accessTicks = max(accessTicks, 0x1U);
851 recTicks = SYSCLK_TICKS_66(recTime);
852 recTicks = min(recTicks, 0x1fU);
853 recTicks = max(recTicks, 0x3U);
854 /* Clear out mdma bits and disable udma */
855 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
856 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
857 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
858 break;
859 case controller_kl_ata3:
860 /* 33Mhz cell on KeyLargo */
861 accessTicks = SYSCLK_TICKS(accessTime);
862 accessTicks = max(accessTicks, 1U);
863 accessTicks = min(accessTicks, 0x1fU);
864 accessTime = accessTicks * IDE_SYSCLK_NS;
865 recTicks = SYSCLK_TICKS(recTime);
866 recTicks = max(recTicks, 1U);
867 recTicks = min(recTicks, 0x1fU);
868 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
869 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
870 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
871 break;
872 default: {
873 /* 33Mhz cell on others */
874 int halfTick = 0;
875 int origAccessTime = accessTime;
876 int origRecTime = recTime;
877
878 accessTicks = SYSCLK_TICKS(accessTime);
879 accessTicks = max(accessTicks, 1U);
880 accessTicks = min(accessTicks, 0x1fU);
881 accessTime = accessTicks * IDE_SYSCLK_NS;
882 recTicks = SYSCLK_TICKS(recTime);
883 recTicks = max(recTicks, 2U) - 1;
884 recTicks = min(recTicks, 0x1fU);
885 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
886 if ((accessTicks > 1) &&
887 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
888 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
889 halfTick = 1;
890 accessTicks--;
891 }
892 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
893 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
894 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
895 if (halfTick)
896 *timings |= TR_33_MDMA_HALFTICK;
897 }
898 }
899#ifdef IDE_PMAC_DEBUG
900 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
901 drive->name, speed & 0xf, *timings);
902#endif
903 return 0;
904}
905#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
906
907/*
908 * Speedproc. This function is called by the core to set any of the standard
8f4dd2e4 909 * DMA timing (MDMA or UDMA) to both the drive and the controller.
1da177e4
LT		 910 * You may notice we don't use this function on normal "dma check" operation,
911 * our dedicated function is more precise as it uses the drive provided
912 * cycle time value. We should probably fix this one to deal with that too...
913 */
f212ff28 914static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 915{
916 int unit = (drive->select.b.unit & 0x01);
917 int ret = 0;
918 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
919 u32 *timings, *timings2;
920
921 if (pmif == NULL)
922 return 1;
923
924 timings = &pmif->timings[unit];
925 timings2 = &pmif->timings[unit+2];
926
927 switch(speed) {
928#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
929 case XFER_UDMA_6:
1da177e4 930 case XFER_UDMA_5:
1da177e4
LT		 931 case XFER_UDMA_4:
932 case XFER_UDMA_3:
1da177e4
LT		 933 case XFER_UDMA_2:
934 case XFER_UDMA_1:
935 case XFER_UDMA_0:
936 if (pmif->kind == controller_kl_ata4)
937 ret = set_timings_udma_ata4(timings, speed);
938 else if (pmif->kind == controller_un_ata6
939 || pmif->kind == controller_k2_ata6)
940 ret = set_timings_udma_ata6(timings, timings2, speed);
941 else if (pmif->kind == controller_sh_ata6)
942 ret = set_timings_udma_shasta(timings, timings2, speed);
943 else
944 ret = 1;
945 break;
946 case XFER_MW_DMA_2:
947 case XFER_MW_DMA_1:
948 case XFER_MW_DMA_0:
949 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
950 break;
951 case XFER_SW_DMA_2:
952 case XFER_SW_DMA_1:
953 case XFER_SW_DMA_0:
954 return 1;
955#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1da177e4
LT		 956 default:
957 ret = 1;
958 }
959 if (ret)
960 return ret;
961
962 ret = pmac_ide_do_setfeature(drive, speed);
963 if (ret)
964 return ret;
965
966 pmac_ide_do_update_timings(drive);
1da177e4
LT		 967
968 return 0;
969}
970
971/*
972 * Blast some well known "safe" values to the timing registers at init or
973 * wakeup from sleep time, before we do real calculation
974 */
aacaf9bd 975static void
1da177e4
LT		 976sanitize_timings(pmac_ide_hwif_t *pmif)
977{
978 unsigned int value, value2 = 0;
979
980 switch(pmif->kind) {
981 case controller_sh_ata6:
982 value = 0x0a820c97;
983 value2 = 0x00033031;
984 break;
985 case controller_un_ata6:
986 case controller_k2_ata6:
987 value = 0x08618a92;
988 value2 = 0x00002921;
989 break;
990 case controller_kl_ata4:
991 value = 0x0008438c;
992 break;
993 case controller_kl_ata3:
994 value = 0x00084526;
995 break;
996 case controller_heathrow:
997 case controller_ohare:
998 default:
999 value = 0x00074526;
1000 break;
1001 }
1002 pmif->timings[0] = pmif->timings[1] = value;
1003 pmif->timings[2] = pmif->timings[3] = value2;
1004}
1005
aacaf9bd 1006unsigned long
1da177e4
LT		 1007pmac_ide_get_base(int index)
1008{
1009 return pmac_ide[index].regbase;
1010}
1011
aacaf9bd 1012int
1da177e4
LT		 1013pmac_ide_check_base(unsigned long base)
1014{
1015 int ix;
1016
1017 for (ix = 0; ix < MAX_HWIFS; ++ix)
1018 if (base == pmac_ide[ix].regbase)
1019 return ix;
1020 return -1;
1021}
1022
aacaf9bd 1023int
1da177e4
LT		 1024pmac_ide_get_irq(unsigned long base)
1025{
1026 int ix;
1027
1028 for (ix = 0; ix < MAX_HWIFS; ++ix)
1029 if (base == pmac_ide[ix].regbase)
1030 return pmac_ide[ix].irq;
1031 return 0;
1032}
1033
aacaf9bd 1034static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1da177e4
LT		 1035
1036dev_t __init
1037pmac_find_ide_boot(char *bootdevice, int n)
1038{
1039 int i;
1040
1041 /*
1042 * Look through the list of IDE interfaces for this one.
1043 */
1044 for (i = 0; i < pmac_ide_count; ++i) {
1045 char *name;
1046 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1047 continue;
1048 name = pmac_ide[i].node->full_name;
1049 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1050 /* XXX should cope with the 2nd drive as well... */
1051 return MKDEV(ide_majors[i], 0);
1052 }
1053 }
1054
1055 return 0;
1056}
1057
1058/* Suspend call back, should be called after the child devices
1059 * have actually been suspended
1060 */
1061static int
1062pmac_ide_do_suspend(ide_hwif_t *hwif)
1063{
1064 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1065
1066 /* We clear the timings */
1067 pmif->timings[0] = 0;
1068 pmif->timings[1] = 0;
1069
616299af
BH		 1070 disable_irq(pmif->irq);
1071
1da177e4
LT		 1072 /* The media bay will handle itself just fine */
1073 if (pmif->mediabay)
1074 return 0;
1075
1076 /* Kauai has bus control FCRs directly here */
1077 if (pmif->kauai_fcr) {
1078 u32 fcr = readl(pmif->kauai_fcr);
1079 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1080 writel(fcr, pmif->kauai_fcr);
1081 }
1082
1083 /* Disable the bus on older machines and the cell on kauai */
1084 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1085 0);
1086
1087 return 0;
1088}
1089
1090/* Resume call back, should be called before the child devices
1091 * are resumed
1092 */
1093static int
1094pmac_ide_do_resume(ide_hwif_t *hwif)
1095{
1096 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1097
1098 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1099 if (!pmif->mediabay) {
1100 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1101 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1102 msleep(10);
1103 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 1104
1105 /* Kauai has it different */
1106 if (pmif->kauai_fcr) {
1107 u32 fcr = readl(pmif->kauai_fcr);
1108 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1109 writel(fcr, pmif->kauai_fcr);
1110 }
616299af
BH		 1111
1112 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 1113 }
1114
1115 /* Sanitize drive timings */
1116 sanitize_timings(pmif);
1117
616299af
BH		 1118 enable_irq(pmif->irq);
1119
1da177e4
LT		 1120 return 0;
1121}
1122
1123/*
1124 * Setup, register & probe an IDE channel driven by this driver, this is
1125 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1126 * that ends up beeing free of any device is not kept around by this driver
1127 * (it is kept in 2.4). This introduce an interface numbering change on some
1128 * rare machines unfortunately, but it's better this way.
1129 */
1130static int
1131pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1132{
1133 struct device_node *np = pmif->node;
018a3d1d 1134 const int *bidp;
1da177e4
LT		 1135
1136 pmif->cable_80 = 0;
1137 pmif->broken_dma = pmif->broken_dma_warn = 0;
55b61fec 1138 if (of_device_is_compatible(np, "shasta-ata"))
1da177e4 1139 pmif->kind = controller_sh_ata6;
55b61fec 1140 else if (of_device_is_compatible(np, "kauai-ata"))
1da177e4 1141 pmif->kind = controller_un_ata6;
55b61fec 1142 else if (of_device_is_compatible(np, "K2-UATA"))
1da177e4 1143 pmif->kind = controller_k2_ata6;
55b61fec 1144 else if (of_device_is_compatible(np, "keylargo-ata")) {
1da177e4
LT		 1145 if (strcmp(np->name, "ata-4") == 0)
1146 pmif->kind = controller_kl_ata4;
1147 else
1148 pmif->kind = controller_kl_ata3;
55b61fec 1149 } else if (of_device_is_compatible(np, "heathrow-ata"))
1da177e4
LT		 1150 pmif->kind = controller_heathrow;
1151 else {
1152 pmif->kind = controller_ohare;
1153 pmif->broken_dma = 1;
1154 }
1155
40cd3a45 1156 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1da177e4
LT		 1157 pmif->aapl_bus_id = bidp ? *bidp : 0;
1158
1159 /* Get cable type from device-tree */
1160 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1161 || pmif->kind == controller_k2_ata6
1162 || pmif->kind == controller_sh_ata6) {
40cd3a45 1163 const char* cable = of_get_property(np, "cable-type", NULL);
1da177e4
LT		 1164 if (cable && !strncmp(cable, "80-", 3))
1165 pmif->cable_80 = 1;
1166 }
1167 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1168 * they have a 80 conductor cable, this seem to be always the case unless
1169 * the user mucked around
1170 */
55b61fec
SR		 1171 if (of_device_is_compatible(np, "K2-UATA") ||
1172 of_device_is_compatible(np, "shasta-ata"))
1da177e4
LT		 1173 pmif->cable_80 = 1;
1174
1175 /* On Kauai-type controllers, we make sure the FCR is correct */
1176 if (pmif->kauai_fcr)
1177 writel(KAUAI_FCR_UATA_MAGIC |
1178 KAUAI_FCR_UATA_RESET_N |
1179 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1180
1181 pmif->mediabay = 0;
1182
1183 /* Make sure we have sane timings */
1184 sanitize_timings(pmif);
1185
1186#ifndef CONFIG_PPC64
1187 /* XXX FIXME: Media bay stuff need re-organizing */
1188 if (np->parent && np->parent->name
1189 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1190#ifdef CONFIG_PMAC_MEDIABAY
1da177e4 1191 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
8c870933 1192#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1193 pmif->mediabay = 1;
1194 if (!bidp)
1195 pmif->aapl_bus_id = 1;
1196 } else if (pmif->kind == controller_ohare) {
1197 /* The code below is having trouble on some ohare machines
1198 * (timing related ?). Until I can put my hand on one of these
1199 * units, I keep the old way
1200 */
1201 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1202 } else
1203#endif
1204 {
1205 /* This is necessary to enable IDE when net-booting */
1206 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1207 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1208 msleep(10);
1209 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1210 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1211 }
1212
1213 /* Setup MMIO ops */
1214 default_hwif_mmiops(hwif);
1215 hwif->OUTBSYNC = pmac_outbsync;
1216
1217 /* Tell common code _not_ to mess with resources */
2ad1e558 1218 hwif->mmio = 1;
1da177e4
LT		 1219 hwif->hwif_data = pmif;
1220 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1221 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1222 hwif->chipset = ide_pmac;
1223 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1224 hwif->hold = pmif->mediabay;
49521f97 1225 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 1226 hwif->drives[0].unmask = 1;
1227 hwif->drives[1].unmask = 1;
4099d143 1228 hwif->pio_mask = ATA_PIO4;
26bcb879 1229 hwif->set_pio_mode = pmac_ide_set_pio_mode;
1da177e4
LT		 1230 if (pmif->kind == controller_un_ata6
1231 || pmif->kind == controller_k2_ata6
1232 || pmif->kind == controller_sh_ata6)
1233 hwif->selectproc = pmac_ide_kauai_selectproc;
1234 else
1235 hwif->selectproc = pmac_ide_selectproc;
1236 hwif->speedproc = pmac_ide_tune_chipset;
1237
1da177e4
LT		 1238 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1239 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1240 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1241
8c870933 1242#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1243 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1244 hwif->noprobe = 0;
8c870933 1245#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1246
1247 hwif->sg_max_nents = MAX_DCMDS;
1248
1249#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1250 /* has a DBDMA controller channel */
1251 if (pmif->dma_regs)
1252 pmac_ide_setup_dma(pmif, hwif);
1253#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1254
1255 /* We probe the hwif now */
1256 probe_hwif_init(hwif);
1257
5cbf79cd
BZ		 1258 ide_proc_register_port(hwif);
1259
1da177e4
LT		 1260 return 0;
1261}
1262
1263/*
1264 * Attach to a macio probed interface
1265 */
1266static int __devinit
5e655772 1267pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1268{
1269 void __iomem *base;
1270 unsigned long regbase;
1271 int irq;
1272 ide_hwif_t *hwif;
1273 pmac_ide_hwif_t *pmif;
1274 int i, rc;
1275
1276 i = 0;
1277 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1278 || pmac_ide[i].node != NULL))
1279 ++i;
1280 if (i >= MAX_HWIFS) {
1281 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1282 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1283 return -ENODEV;
1284 }
1285
1286 pmif = &pmac_ide[i];
1287 hwif = &ide_hwifs[i];
1288
cc5d0189 1289 if (macio_resource_count(mdev) == 0) {
1da177e4
LT		 1290 printk(KERN_WARNING "ide%d: no address for %s\n",
1291 i, mdev->ofdev.node->full_name);
1292 return -ENXIO;
1293 }
1294
1295 /* Request memory resource for IO ports */
1296 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1297 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1298 return -EBUSY;
1299 }
1300
1301 /* XXX This is bogus. Should be fixed in the registry by checking
1302 * the kind of host interrupt controller, a bit like gatwick
1303 * fixes in irq.c. That works well enough for the single case
1304 * where that happens though...
1305 */
1306 if (macio_irq_count(mdev) == 0) {
1307 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1308 i, mdev->ofdev.node->full_name);
69917c26 1309 irq = irq_create_mapping(NULL, 13);
1da177e4
LT		 1310 } else
1311 irq = macio_irq(mdev, 0);
1312
1313 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1314 regbase = (unsigned long) base;
1315
1316 hwif->pci_dev = mdev->bus->pdev;
1317 hwif->gendev.parent = &mdev->ofdev.dev;
1318
1319 pmif->mdev = mdev;
1320 pmif->node = mdev->ofdev.node;
1321 pmif->regbase = regbase;
1322 pmif->irq = irq;
1323 pmif->kauai_fcr = NULL;
1324#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1325 if (macio_resource_count(mdev) >= 2) {
1326 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1327 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1328 else
1329 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1330 } else
1331 pmif->dma_regs = NULL;
1332#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1333 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1334
1335 rc = pmac_ide_setup_device(pmif, hwif);
1336 if (rc != 0) {
1337 /* The inteface is released to the common IDE layer */
1338 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1339 iounmap(base);
1340 if (pmif->dma_regs)
1341 iounmap(pmif->dma_regs);
1342 memset(pmif, 0, sizeof(*pmif));
1343 macio_release_resource(mdev, 0);
1344 if (pmif->dma_regs)
1345 macio_release_resource(mdev, 1);
1346 }
1347
1348 return rc;
1349}
1350
1351static int
8b4b8a24 1352pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1da177e4
LT		 1353{
1354 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1355 int rc = 0;
1356
8b4b8a24
DB		 1357 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1358 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1359 rc = pmac_ide_do_suspend(hwif);
1360 if (rc == 0)
8b4b8a24 1361 mdev->ofdev.dev.power.power_state = mesg;
1da177e4
LT		 1362 }
1363
1364 return rc;
1365}
1366
1367static int
1368pmac_ide_macio_resume(struct macio_dev *mdev)
1369{
1370 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1371 int rc = 0;
1372
ca078bae 1373 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1374 rc = pmac_ide_do_resume(hwif);
1375 if (rc == 0)
829ca9a3 1376 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1377 }
1378
1379 return rc;
1380}
1381
1382/*
1383 * Attach to a PCI probed interface
1384 */
1385static int __devinit
1386pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1387{
1388 ide_hwif_t *hwif;
1389 struct device_node *np;
1390 pmac_ide_hwif_t *pmif;
1391 void __iomem *base;
1392 unsigned long rbase, rlen;
1393 int i, rc;
1394
1395 np = pci_device_to_OF_node(pdev);
1396 if (np == NULL) {
1397 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1398 return -ENODEV;
1399 }
1400 i = 0;
1401 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1402 || pmac_ide[i].node != NULL))
1403 ++i;
1404 if (i >= MAX_HWIFS) {
1405 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1406 printk(KERN_ERR " %s\n", np->full_name);
1407 return -ENODEV;
1408 }
1409
1410 pmif = &pmac_ide[i];
1411 hwif = &ide_hwifs[i];
1412
1413 if (pci_enable_device(pdev)) {
1414 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1415 i, np->full_name);
1416 return -ENXIO;
1417 }
1418 pci_set_master(pdev);
1419
1420 if (pci_request_regions(pdev, "Kauai ATA")) {
1421 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1422 i, np->full_name);
1423 return -ENXIO;
1424 }
1425
1426 hwif->pci_dev = pdev;
1427 hwif->gendev.parent = &pdev->dev;
1428 pmif->mdev = NULL;
1429 pmif->node = np;
1430
1431 rbase = pci_resource_start(pdev, 0);
1432 rlen = pci_resource_len(pdev, 0);
1433
1434 base = ioremap(rbase, rlen);
1435 pmif->regbase = (unsigned long) base + 0x2000;
1436#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1437 pmif->dma_regs = base + 0x1000;
1438#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1439 pmif->kauai_fcr = base;
1440 pmif->irq = pdev->irq;
1441
1442 pci_set_drvdata(pdev, hwif);
1443
1444 rc = pmac_ide_setup_device(pmif, hwif);
1445 if (rc != 0) {
1446 /* The inteface is released to the common IDE layer */
1447 pci_set_drvdata(pdev, NULL);
1448 iounmap(base);
1449 memset(pmif, 0, sizeof(*pmif));
1450 pci_release_regions(pdev);
1451 }
1452
1453 return rc;
1454}
1455
1456static int
8b4b8a24 1457pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1da177e4
LT		 1458{
1459 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1460 int rc = 0;
1461
8b4b8a24
DB		 1462 if (mesg.event != pdev->dev.power.power_state.event
1463 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1464 rc = pmac_ide_do_suspend(hwif);
1465 if (rc == 0)
8b4b8a24 1466 pdev->dev.power.power_state = mesg;
1da177e4
LT		 1467 }
1468
1469 return rc;
1470}
1471
1472static int
1473pmac_ide_pci_resume(struct pci_dev *pdev)
1474{
1475 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1476 int rc = 0;
1477
ca078bae 1478 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1479 rc = pmac_ide_do_resume(hwif);
1480 if (rc == 0)
829ca9a3 1481 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1482 }
1483
1484 return rc;
1485}
1486
5e655772 1487static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1488{
1489 {
1490 .name = "IDE",
1da177e4
LT		 1491 },
1492 {
1493 .name = "ATA",
1da177e4
LT		 1494 },
1495 {
1da177e4 1496 .type = "ide",
1da177e4
LT		 1497 },
1498 {
1da177e4 1499 .type = "ata",
1da177e4
LT		 1500 },
1501 {},
1502};
1503
1504static struct macio_driver pmac_ide_macio_driver =
1505{
1506 .name = "ide-pmac",
1507 .match_table = pmac_ide_macio_match,
1508 .probe = pmac_ide_macio_attach,
1509 .suspend = pmac_ide_macio_suspend,
1510 .resume = pmac_ide_macio_resume,
1511};
1512
1513static struct pci_device_id pmac_ide_pci_match[] = {
7fce260a
OJ		 1514 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1516 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1518 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1520 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
7fce260a
OJ		 1522 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1523 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71e4eda8 1524 {},
1da177e4
LT		 1525};
1526
1527static struct pci_driver pmac_ide_pci_driver = {
1528 .name = "ide-pmac",
1529 .id_table = pmac_ide_pci_match,
1530 .probe = pmac_ide_pci_attach,
1531 .suspend = pmac_ide_pci_suspend,
1532 .resume = pmac_ide_pci_resume,
1533};
1534MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1535
9e5755bc 1536int __init pmac_ide_probe(void)
1da177e4 1537{
9e5755bc
AM		 1538 int error;
1539
e8222502 1540 if (!machine_is(powermac))
9e5755bc 1541 return -ENODEV;
1da177e4
LT		 1542
1543#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
9e5755bc
AM		 1544 error = pci_register_driver(&pmac_ide_pci_driver);
1545 if (error)
1546 goto out;
1547 error = macio_register_driver(&pmac_ide_macio_driver);
1548 if (error) {
1549 pci_unregister_driver(&pmac_ide_pci_driver);
1550 goto out;
1551 }
1da177e4 1552#else
9e5755bc
AM		 1553 error = macio_register_driver(&pmac_ide_macio_driver);
1554 if (error)
1555 goto out;
1556 error = pci_register_driver(&pmac_ide_pci_driver);
1557 if (error) {
1558 macio_unregister_driver(&pmac_ide_macio_driver);
1559 goto out;
1560 }
1beb6a7d 1561#endif
9e5755bc
AM		 1562out:
1563 return error;
1da177e4
LT		 1564}
1565
1566#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1567
1568/*
1569 * pmac_ide_build_dmatable builds the DBDMA command list
1570 * for a transfer and sets the DBDMA channel to point to it.
1571 */
aacaf9bd 1572static int
1da177e4
LT		 1573pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1574{
1575 struct dbdma_cmd *table;
1576 int i, count = 0;
1577 ide_hwif_t *hwif = HWIF(drive);
1578 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1579 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1580 struct scatterlist *sg;
1581 int wr = (rq_data_dir(rq) == WRITE);
1582
1583 /* DMA table is already aligned */
1584 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1585
1586 /* Make sure DMA controller is stopped (necessary ?) */
1587 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1588 while (readl(&dma->status) & RUN)
1589 udelay(1);
1590
1591 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1592
1593 if (!i)
1594 return 0;
1595
1596 /* Build DBDMA commands list */
1597 sg = hwif->sg_table;
1598 while (i && sg_dma_len(sg)) {
1599 u32 cur_addr;
1600 u32 cur_len;
1601
1602 cur_addr = sg_dma_address(sg);
1603 cur_len = sg_dma_len(sg);
1604
1605 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1606 if (pmif->broken_dma_warn == 0) {
1607 printk(KERN_WARNING "%s: DMA on non aligned address,"
1608 "switching to PIO on Ohare chipset\n", drive->name);
1609 pmif->broken_dma_warn = 1;
1610 }
1611 goto use_pio_instead;
1612 }
1613 while (cur_len) {
1614 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1615
1616 if (count++ >= MAX_DCMDS) {
1617 printk(KERN_WARNING "%s: DMA table too small\n",
1618 drive->name);
1619 goto use_pio_instead;
1620 }
1621 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1622 st_le16(&table->req_count, tc);
1623 st_le32(&table->phy_addr, cur_addr);
1624 table->cmd_dep = 0;
1625 table->xfer_status = 0;
1626 table->res_count = 0;
1627 cur_addr += tc;
1628 cur_len -= tc;
1629 ++table;
1630 }
1631 sg++;
1632 i--;
1633 }
1634
1635 /* convert the last command to an input/output last command */
1636 if (count) {
1637 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1638 /* add the stop command to the end of the list */
1639 memset(table, 0, sizeof(struct dbdma_cmd));
1640 st_le16(&table->command, DBDMA_STOP);
1641 mb();
1642 writel(hwif->dmatable_dma, &dma->cmdptr);
1643 return 1;
1644 }
1645
1646 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1647 use_pio_instead:
1648 pci_unmap_sg(hwif->pci_dev,
1649 hwif->sg_table,
1650 hwif->sg_nents,
1651 hwif->sg_dma_direction);
1652 return 0; /* revert to PIO for this request */
1653}
1654
1655/* Teardown mappings after DMA has completed. */
aacaf9bd 1656static void
1da177e4
LT		 1657pmac_ide_destroy_dmatable (ide_drive_t *drive)
1658{
1659 ide_hwif_t *hwif = drive->hwif;
1660 struct pci_dev *dev = HWIF(drive)->pci_dev;
1661 struct scatterlist *sg = hwif->sg_table;
1662 int nents = hwif->sg_nents;
1663
1664 if (nents) {
1665 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1666 hwif->sg_nents = 0;
1667 }
1668}
1669
1670/*
1671 * Pick up best MDMA timing for the drive and apply it
1672 */
aacaf9bd 1673static int
1da177e4
LT		 1674pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1675{
1676 ide_hwif_t *hwif = HWIF(drive);
1677 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1678 int drive_cycle_time;
1679 struct hd_driveid *id = drive->id;
1680 u32 *timings, *timings2;
1681 u32 timing_local[2];
1682 int ret;
1683
1684 /* which drive is it ? */
1685 timings = &pmif->timings[drive->select.b.unit & 0x01];
1686 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1687
1688 /* Check if drive provide explicit cycle time */
1689 if ((id->field_valid & 2) && (id->eide_dma_time))
1690 drive_cycle_time = id->eide_dma_time;
1691 else
1692 drive_cycle_time = 0;
1693
1694 /* Copy timings to local image */
1695 timing_local[0] = *timings;
1696 timing_local[1] = *timings2;
1697
1698 /* Calculate controller timings */
1699 ret = set_timings_mdma( drive, pmif->kind,
1700 &timing_local[0],
1701 &timing_local[1],
1702 mode,
1703 drive_cycle_time);
1704 if (ret)
1705 return 0;
1706
1707 /* Set feature on drive */
1708 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1709 ret = pmac_ide_do_setfeature(drive, mode);
1710 if (ret) {
1711 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1712 return 0;
1713 }
1714
1715 /* Apply timings to controller */
1716 *timings = timing_local[0];
1717 *timings2 = timing_local[1];
1da177e4
LT		 1718
1719 return 1;
1720}
1721
1722/*
1723 * Pick up best UDMA timing for the drive and apply it
1724 */
aacaf9bd 1725static int
1da177e4
LT		 1726pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1727{
1728 ide_hwif_t *hwif = HWIF(drive);
1729 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1730 u32 *timings, *timings2;
1731 u32 timing_local[2];
1732 int ret;
1733
1734 /* which drive is it ? */
1735 timings = &pmif->timings[drive->select.b.unit & 0x01];
1736 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1737
1738 /* Copy timings to local image */
1739 timing_local[0] = *timings;
1740 timing_local[1] = *timings2;
1741
1742 /* Calculate timings for interface */
1743 if (pmif->kind == controller_un_ata6
1744 || pmif->kind == controller_k2_ata6)
1745 ret = set_timings_udma_ata6( &timing_local[0],
1746 &timing_local[1],
1747 mode);
1748 else if (pmif->kind == controller_sh_ata6)
1749 ret = set_timings_udma_shasta( &timing_local[0],
1750 &timing_local[1],
1751 mode);
1752 else
1753 ret = set_timings_udma_ata4(&timing_local[0], mode);
1754 if (ret)
1755 return 0;
1756
1757 /* Set feature on drive */
1758 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1759 ret = pmac_ide_do_setfeature(drive, mode);
1760 if (ret) {
1761 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1762 return 0;
1763 }
1764
1765 /* Apply timings to controller */
1766 *timings = timing_local[0];
1767 *timings2 = timing_local[1];
1768
1da177e4
LT		 1769 return 1;
1770}
1771
1772/*
1773 * Check what is the best DMA timing setting for the drive and
1774 * call appropriate functions to apply it.
1775 */
aacaf9bd 1776static int
1da177e4
LT		 1777pmac_ide_dma_check(ide_drive_t *drive)
1778{
1779 struct hd_driveid *id = drive->id;
1780 ide_hwif_t *hwif = HWIF(drive);
1da177e4 1781 int enable = 1;
1da177e4
LT		 1782 drive->using_dma = 0;
1783
1784 if (drive->media == ide_floppy)
1785 enable = 0;
1786 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1787 enable = 0;
1788 if (__ide_dma_bad_drive(drive))
1789 enable = 0;
1790
1791 if (enable) {
75b1d975
BZ		 1792 u8 mode = ide_max_dma_mode(drive);
1793
1794 if (mode >= XFER_UDMA_0)
1da177e4 1795 drive->using_dma = pmac_ide_udma_enable(drive, mode);
75b1d975 1796 else if (mode >= XFER_MW_DMA_0)
1da177e4
LT		 1797 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1798 hwif->OUTB(0, IDE_CONTROL_REG);
1799 /* Apply settings to controller */
1800 pmac_ide_do_update_timings(drive);
1801 }
1802 return 0;
1803}
1804
1805/*
1806 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1807 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1808 */
aacaf9bd 1809static int
1da177e4
LT		 1810pmac_ide_dma_setup(ide_drive_t *drive)
1811{
1812 ide_hwif_t *hwif = HWIF(drive);
1813 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1814 struct request *rq = HWGROUP(drive)->rq;
1815 u8 unit = (drive->select.b.unit & 0x01);
1816 u8 ata4;
1817
1818 if (pmif == NULL)
1819 return 1;
1820 ata4 = (pmif->kind == controller_kl_ata4);
1821
1822 if (!pmac_ide_build_dmatable(drive, rq)) {
1823 ide_map_sg(drive, rq);
1824 return 1;
1825 }
1826
1827 /* Apple adds 60ns to wrDataSetup on reads */
1828 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1829 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1830 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1831 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1832 }
1833
1834 drive->waiting_for_dma = 1;
1835
1836 return 0;
1837}
1838
aacaf9bd 1839static void
1da177e4
LT		 1840pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1841{
1842 /* issue cmd to drive */
1843 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1844}
1845
1846/*
1847 * Kick the DMA controller into life after the DMA command has been issued
1848 * to the drive.
1849 */
aacaf9bd 1850static void
1da177e4
LT		 1851pmac_ide_dma_start(ide_drive_t *drive)
1852{
1853 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1854 volatile struct dbdma_regs __iomem *dma;
1855
1856 dma = pmif->dma_regs;
1857
1858 writel((RUN << 16) | RUN, &dma->control);
1859 /* Make sure it gets to the controller right now */
1860 (void)readl(&dma->control);
1861}
1862
1863/*
1864 * After a DMA transfer, make sure the controller is stopped
1865 */
aacaf9bd 1866static int
1da177e4
LT		 1867pmac_ide_dma_end (ide_drive_t *drive)
1868{
1869 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1870 volatile struct dbdma_regs __iomem *dma;
1871 u32 dstat;
1872
1873 if (pmif == NULL)
1874 return 0;
1875 dma = pmif->dma_regs;
1876
1877 drive->waiting_for_dma = 0;
1878 dstat = readl(&dma->status);
1879 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1880 pmac_ide_destroy_dmatable(drive);
1881 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1882 * in theory, but with ATAPI decices doing buffer underruns, that would
1883 * cause us to disable DMA, which isn't what we want
1884 */
1885 return (dstat & (RUN|DEAD)) != RUN;
1886}
1887
1888/*
1889 * Check out that the interrupt we got was for us. We can't always know this
1890 * for sure with those Apple interfaces (well, we could on the recent ones but
1891 * that's not implemented yet), on the other hand, we don't have shared interrupts
1892 * so it's not really a problem
1893 */
aacaf9bd 1894static int
1da177e4
LT		 1895pmac_ide_dma_test_irq (ide_drive_t *drive)
1896{
1897 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1898 volatile struct dbdma_regs __iomem *dma;
1899 unsigned long status, timeout;
1900
1901 if (pmif == NULL)
1902 return 0;
1903 dma = pmif->dma_regs;
1904
1905 /* We have to things to deal with here:
1906 *
1907 * - The dbdma won't stop if the command was started
1908 * but completed with an error without transferring all
1909 * datas. This happens when bad blocks are met during
1910 * a multi-block transfer.
1911 *
1912 * - The dbdma fifo hasn't yet finished flushing to
1913 * to system memory when the disk interrupt occurs.
1914 *
1915 */
1916
1917 /* If ACTIVE is cleared, the STOP command have passed and
1918 * transfer is complete.
1919 */
1920 status = readl(&dma->status);
1921 if (!(status & ACTIVE))
1922 return 1;
1923 if (!drive->waiting_for_dma)
1924 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1925 called while not waiting\n", HWIF(drive)->index);
1926
1927 /* If dbdma didn't execute the STOP command yet, the
1928 * active bit is still set. We consider that we aren't
1929 * sharing interrupts (which is hopefully the case with
1930 * those controllers) and so we just try to flush the
1931 * channel for pending data in the fifo
1932 */
1933 udelay(1);
1934 writel((FLUSH << 16) | FLUSH, &dma->control);
1935 timeout = 0;
1936 for (;;) {
1937 udelay(1);
1938 status = readl(&dma->status);
1939 if ((status & FLUSH) == 0)
1940 break;
1941 if (++timeout > 100) {
1942 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1943 timeout flushing channel\n", HWIF(drive)->index);
1944 break;
1945 }
1946 }
1947 return 1;
1948}
1949
7469aaf6 1950static void pmac_ide_dma_host_off(ide_drive_t *drive)
1da177e4 1951{
1da177e4
LT		 1952}
1953
9e5755bc 1954static void pmac_ide_dma_host_on(ide_drive_t *drive)
1da177e4 1955{
1da177e4
LT		 1956}
1957
841d2a9b
SS		 1958static void
1959pmac_ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 1960{
1961 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1962 volatile struct dbdma_regs __iomem *dma;
1963 unsigned long status;
1964
1965 if (pmif == NULL)
841d2a9b 1966 return;
1da177e4
LT		 1967 dma = pmif->dma_regs;
1968
1969 status = readl(&dma->status);
1970 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1da177e4
LT		 1971}
1972
1973/*
1974 * Allocate the data structures needed for using DMA with an interface
1975 * and fill the proper list of functions pointers
1976 */
1977static void __init
1978pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1979{
1980 /* We won't need pci_dev if we switch to generic consistent
1981 * DMA routines ...
1982 */
1983 if (hwif->pci_dev == NULL)
1984 return;
1985 /*
1986 * Allocate space for the DBDMA commands.
1987 * The +2 is +1 for the stop command and +1 to allow for
1988 * aligning the start address to a multiple of 16 bytes.
1989 */
1990 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1991 hwif->pci_dev,
1992 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1993 &hwif->dmatable_dma);
1994 if (pmif->dma_table_cpu == NULL) {
1995 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1996 hwif->name);
1997 return;
1998 }
1999
7469aaf6 2000 hwif->dma_off_quietly = &ide_dma_off_quietly;
1da177e4
LT		 2001 hwif->ide_dma_on = &__ide_dma_on;
2002 hwif->ide_dma_check = &pmac_ide_dma_check;
2003 hwif->dma_setup = &pmac_ide_dma_setup;
2004 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2005 hwif->dma_start = &pmac_ide_dma_start;
2006 hwif->ide_dma_end = &pmac_ide_dma_end;
2007 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
7469aaf6 2008 hwif->dma_host_off = &pmac_ide_dma_host_off;
ccf35289 2009 hwif->dma_host_on = &pmac_ide_dma_host_on;
c283f5db 2010 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b 2011 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
1da177e4
LT		 2012
2013 hwif->atapi_dma = 1;
2014 switch(pmif->kind) {
2015 case controller_sh_ata6:
2016 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2017 hwif->mwdma_mask = 0x07;
2018 hwif->swdma_mask = 0x00;
2019 break;
2020 case controller_un_ata6:
2021 case controller_k2_ata6:
2022 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2023 hwif->mwdma_mask = 0x07;
2024 hwif->swdma_mask = 0x00;
2025 break;
2026 case controller_kl_ata4:
2027 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2028 hwif->mwdma_mask = 0x07;
2029 hwif->swdma_mask = 0x00;
2030 break;
2031 default:
2032 hwif->ultra_mask = 0x00;
2033 hwif->mwdma_mask = 0x07;
2034 hwif->swdma_mask = 0x00;
2035 break;
2036 }
2037}
2038
2039#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linux kernel - Deliverables
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