Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Support for IDE interfaces on PowerMacs. |
58f189fc | 3 | * |
1da177e4 LT |
4 | * These IDE interfaces are memory-mapped and have a DBDMA channel |
5 | * for doing DMA. | |
6 | * | |
7 | * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt | |
c15d5d43 | 8 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * Some code taken from drivers/ide/ide-dma.c: | |
16 | * | |
17 | * Copyright (c) 1995-1998 Mark Lord | |
18 | * | |
19 | * TODO: - Use pre-calculated (kauai) timing tables all the time and | |
20 | * get rid of the "rounded" tables used previously, so we have the | |
21 | * same table format for all controllers and can then just have one | |
22 | * big table | |
23 | * | |
24 | */ | |
1da177e4 LT |
25 | #include <linux/types.h> |
26 | #include <linux/kernel.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/ide.h> | |
30 | #include <linux/notifier.h> | |
31 | #include <linux/reboot.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/adb.h> | |
34 | #include <linux/pmu.h> | |
35 | #include <linux/scatterlist.h> | |
36 | ||
37 | #include <asm/prom.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/dbdma.h> | |
40 | #include <asm/ide.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/machdep.h> | |
43 | #include <asm/pmac_feature.h> | |
44 | #include <asm/sections.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #ifndef CONFIG_PPC64 | |
48 | #include <asm/mediabay.h> | |
49 | #endif | |
50 | ||
1da177e4 LT |
51 | #undef IDE_PMAC_DEBUG |
52 | ||
53 | #define DMA_WAIT_TIMEOUT 50 | |
54 | ||
55 | typedef struct pmac_ide_hwif { | |
56 | unsigned long regbase; | |
57 | int irq; | |
58 | int kind; | |
59 | int aapl_bus_id; | |
1da177e4 LT |
60 | unsigned mediabay : 1; |
61 | unsigned broken_dma : 1; | |
62 | unsigned broken_dma_warn : 1; | |
63 | struct device_node* node; | |
64 | struct macio_dev *mdev; | |
65 | u32 timings[4]; | |
66 | volatile u32 __iomem * *kauai_fcr; | |
67 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
68 | /* Those fields are duplicating what is in hwif. We currently | |
69 | * can't use the hwif ones because of some assumptions that are | |
70 | * beeing done by the generic code about the kind of dma controller | |
71 | * and format of the dma table. This will have to be fixed though. | |
72 | */ | |
73 | volatile struct dbdma_regs __iomem * dma_regs; | |
74 | struct dbdma_cmd* dma_table_cpu; | |
75 | #endif | |
76 | ||
77 | } pmac_ide_hwif_t; | |
78 | ||
1da177e4 LT |
79 | enum { |
80 | controller_ohare, /* OHare based */ | |
81 | controller_heathrow, /* Heathrow/Paddington */ | |
82 | controller_kl_ata3, /* KeyLargo ATA-3 */ | |
83 | controller_kl_ata4, /* KeyLargo ATA-4 */ | |
84 | controller_un_ata6, /* UniNorth2 ATA-6 */ | |
85 | controller_k2_ata6, /* K2 ATA-6 */ | |
86 | controller_sh_ata6, /* Shasta ATA-6 */ | |
87 | }; | |
88 | ||
89 | static const char* model_name[] = { | |
90 | "OHare ATA", /* OHare based */ | |
91 | "Heathrow ATA", /* Heathrow/Paddington */ | |
92 | "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ | |
93 | "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ | |
94 | "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ | |
95 | "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ | |
96 | "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ | |
97 | }; | |
98 | ||
99 | /* | |
100 | * Extra registers, both 32-bit little-endian | |
101 | */ | |
102 | #define IDE_TIMING_CONFIG 0x200 | |
103 | #define IDE_INTERRUPT 0x300 | |
104 | ||
105 | /* Kauai (U2) ATA has different register setup */ | |
106 | #define IDE_KAUAI_PIO_CONFIG 0x200 | |
107 | #define IDE_KAUAI_ULTRA_CONFIG 0x210 | |
108 | #define IDE_KAUAI_POLL_CONFIG 0x220 | |
109 | ||
110 | /* | |
111 | * Timing configuration register definitions | |
112 | */ | |
113 | ||
114 | /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ | |
115 | #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) | |
116 | #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) | |
117 | #define IDE_SYSCLK_NS 30 /* 33Mhz cell */ | |
118 | #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ | |
119 | ||
120 | /* 133Mhz cell, found in shasta. | |
121 | * See comments about 100 Mhz Uninorth 2... | |
122 | * Note that PIO_MASK and MDMA_MASK seem to overlap | |
123 | */ | |
124 | #define TR_133_PIOREG_PIO_MASK 0xff000fff | |
125 | #define TR_133_PIOREG_MDMA_MASK 0x00fff800 | |
126 | #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff | |
127 | #define TR_133_UDMAREG_UDMA_EN 0x00000001 | |
128 | ||
129 | /* 100Mhz cell, found in Uninorth 2. I don't have much infos about | |
130 | * this one yet, it appears as a pci device (106b/0033) on uninorth | |
131 | * internal PCI bus and it's clock is controlled like gem or fw. It | |
132 | * appears to be an evolution of keylargo ATA4 with a timing register | |
133 | * extended to 2 32bits registers and a similar DBDMA channel. Other | |
134 | * registers seem to exist but I can't tell much about them. | |
135 | * | |
136 | * So far, I'm using pre-calculated tables for this extracted from | |
137 | * the values used by the MacOS X driver. | |
138 | * | |
139 | * The "PIO" register controls PIO and MDMA timings, the "ULTRA" | |
140 | * register controls the UDMA timings. At least, it seems bit 0 | |
141 | * of this one enables UDMA vs. MDMA, and bits 4..7 are the | |
142 | * cycle time in units of 10ns. Bits 8..15 are used by I don't | |
143 | * know their meaning yet | |
144 | */ | |
145 | #define TR_100_PIOREG_PIO_MASK 0xff000fff | |
146 | #define TR_100_PIOREG_MDMA_MASK 0x00fff000 | |
147 | #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff | |
148 | #define TR_100_UDMAREG_UDMA_EN 0x00000001 | |
149 | ||
150 | ||
151 | /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on | |
152 | * 40 connector cable and to 4 on 80 connector one. | |
153 | * Clock unit is 15ns (66Mhz) | |
154 | * | |
155 | * 3 Values can be programmed: | |
156 | * - Write data setup, which appears to match the cycle time. They | |
157 | * also call it DIOW setup. | |
158 | * - Ready to pause time (from spec) | |
159 | * - Address setup. That one is weird. I don't see where exactly | |
160 | * it fits in UDMA cycles, I got it's name from an obscure piece | |
161 | * of commented out code in Darwin. They leave it to 0, we do as | |
162 | * well, despite a comment that would lead to think it has a | |
163 | * min value of 45ns. | |
164 | * Apple also add 60ns to the write data setup (or cycle time ?) on | |
165 | * reads. | |
166 | */ | |
167 | #define TR_66_UDMA_MASK 0xfff00000 | |
168 | #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ | |
169 | #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */ | |
170 | #define TR_66_UDMA_ADDRSETUP_SHIFT 29 | |
171 | #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ | |
172 | #define TR_66_UDMA_RDY2PAUS_SHIFT 25 | |
173 | #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ | |
174 | #define TR_66_UDMA_WRDATASETUP_SHIFT 21 | |
175 | #define TR_66_MDMA_MASK 0x000ffc00 | |
176 | #define TR_66_MDMA_RECOVERY_MASK 0x000f8000 | |
177 | #define TR_66_MDMA_RECOVERY_SHIFT 15 | |
178 | #define TR_66_MDMA_ACCESS_MASK 0x00007c00 | |
179 | #define TR_66_MDMA_ACCESS_SHIFT 10 | |
180 | #define TR_66_PIO_MASK 0x000003ff | |
181 | #define TR_66_PIO_RECOVERY_MASK 0x000003e0 | |
182 | #define TR_66_PIO_RECOVERY_SHIFT 5 | |
183 | #define TR_66_PIO_ACCESS_MASK 0x0000001f | |
184 | #define TR_66_PIO_ACCESS_SHIFT 0 | |
185 | ||
186 | /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo | |
187 | * Can do pio & mdma modes, clock unit is 30ns (33Mhz) | |
188 | * | |
189 | * The access time and recovery time can be programmed. Some older | |
190 | * Darwin code base limit OHare to 150ns cycle time. I decided to do | |
191 | * the same here fore safety against broken old hardware ;) | |
192 | * The HalfTick bit, when set, adds half a clock (15ns) to the access | |
193 | * time and removes one from recovery. It's not supported on KeyLargo | |
194 | * implementation afaik. The E bit appears to be set for PIO mode 0 and | |
195 | * is used to reach long timings used in this mode. | |
196 | */ | |
197 | #define TR_33_MDMA_MASK 0x003ff800 | |
198 | #define TR_33_MDMA_RECOVERY_MASK 0x001f0000 | |
199 | #define TR_33_MDMA_RECOVERY_SHIFT 16 | |
200 | #define TR_33_MDMA_ACCESS_MASK 0x0000f800 | |
201 | #define TR_33_MDMA_ACCESS_SHIFT 11 | |
202 | #define TR_33_MDMA_HALFTICK 0x00200000 | |
203 | #define TR_33_PIO_MASK 0x000007ff | |
204 | #define TR_33_PIO_E 0x00000400 | |
205 | #define TR_33_PIO_RECOVERY_MASK 0x000003e0 | |
206 | #define TR_33_PIO_RECOVERY_SHIFT 5 | |
207 | #define TR_33_PIO_ACCESS_MASK 0x0000001f | |
208 | #define TR_33_PIO_ACCESS_SHIFT 0 | |
209 | ||
210 | /* | |
211 | * Interrupt register definitions | |
212 | */ | |
213 | #define IDE_INTR_DMA 0x80000000 | |
214 | #define IDE_INTR_DEVICE 0x40000000 | |
215 | ||
216 | /* | |
217 | * FCR Register on Kauai. Not sure what bit 0x4 is ... | |
218 | */ | |
219 | #define KAUAI_FCR_UATA_MAGIC 0x00000004 | |
220 | #define KAUAI_FCR_UATA_RESET_N 0x00000002 | |
221 | #define KAUAI_FCR_UATA_ENABLE 0x00000001 | |
222 | ||
223 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
224 | ||
225 | /* Rounded Multiword DMA timings | |
226 | * | |
227 | * I gave up finding a generic formula for all controller | |
228 | * types and instead, built tables based on timing values | |
229 | * used by Apple in Darwin's implementation. | |
230 | */ | |
231 | struct mdma_timings_t { | |
232 | int accessTime; | |
233 | int recoveryTime; | |
234 | int cycleTime; | |
235 | }; | |
236 | ||
aacaf9bd | 237 | struct mdma_timings_t mdma_timings_33[] = |
1da177e4 LT |
238 | { |
239 | { 240, 240, 480 }, | |
240 | { 180, 180, 360 }, | |
241 | { 135, 135, 270 }, | |
242 | { 120, 120, 240 }, | |
243 | { 105, 105, 210 }, | |
244 | { 90, 90, 180 }, | |
245 | { 75, 75, 150 }, | |
246 | { 75, 45, 120 }, | |
247 | { 0, 0, 0 } | |
248 | }; | |
249 | ||
aacaf9bd | 250 | struct mdma_timings_t mdma_timings_33k[] = |
1da177e4 LT |
251 | { |
252 | { 240, 240, 480 }, | |
253 | { 180, 180, 360 }, | |
254 | { 150, 150, 300 }, | |
255 | { 120, 120, 240 }, | |
256 | { 90, 120, 210 }, | |
257 | { 90, 90, 180 }, | |
258 | { 90, 60, 150 }, | |
259 | { 90, 30, 120 }, | |
260 | { 0, 0, 0 } | |
261 | }; | |
262 | ||
aacaf9bd | 263 | struct mdma_timings_t mdma_timings_66[] = |
1da177e4 LT |
264 | { |
265 | { 240, 240, 480 }, | |
266 | { 180, 180, 360 }, | |
267 | { 135, 135, 270 }, | |
268 | { 120, 120, 240 }, | |
269 | { 105, 105, 210 }, | |
270 | { 90, 90, 180 }, | |
271 | { 90, 75, 165 }, | |
272 | { 75, 45, 120 }, | |
273 | { 0, 0, 0 } | |
274 | }; | |
275 | ||
276 | /* KeyLargo ATA-4 Ultra DMA timings (rounded) */ | |
277 | struct { | |
278 | int addrSetup; /* ??? */ | |
279 | int rdy2pause; | |
280 | int wrDataSetup; | |
aacaf9bd | 281 | } kl66_udma_timings[] = |
1da177e4 LT |
282 | { |
283 | { 0, 180, 120 }, /* Mode 0 */ | |
284 | { 0, 150, 90 }, /* 1 */ | |
285 | { 0, 120, 60 }, /* 2 */ | |
286 | { 0, 90, 45 }, /* 3 */ | |
287 | { 0, 90, 30 } /* 4 */ | |
288 | }; | |
289 | ||
290 | /* UniNorth 2 ATA/100 timings */ | |
291 | struct kauai_timing { | |
292 | int cycle_time; | |
293 | u32 timing_reg; | |
294 | }; | |
295 | ||
aacaf9bd | 296 | static struct kauai_timing kauai_pio_timings[] = |
1da177e4 LT |
297 | { |
298 | { 930 , 0x08000fff }, | |
299 | { 600 , 0x08000a92 }, | |
300 | { 383 , 0x0800060f }, | |
301 | { 360 , 0x08000492 }, | |
302 | { 330 , 0x0800048f }, | |
303 | { 300 , 0x080003cf }, | |
304 | { 270 , 0x080003cc }, | |
305 | { 240 , 0x0800038b }, | |
306 | { 239 , 0x0800030c }, | |
307 | { 180 , 0x05000249 }, | |
c15d5d43 BZ |
308 | { 120 , 0x04000148 }, |
309 | { 0 , 0 }, | |
1da177e4 LT |
310 | }; |
311 | ||
aacaf9bd | 312 | static struct kauai_timing kauai_mdma_timings[] = |
1da177e4 LT |
313 | { |
314 | { 1260 , 0x00fff000 }, | |
315 | { 480 , 0x00618000 }, | |
316 | { 360 , 0x00492000 }, | |
317 | { 270 , 0x0038e000 }, | |
318 | { 240 , 0x0030c000 }, | |
319 | { 210 , 0x002cb000 }, | |
320 | { 180 , 0x00249000 }, | |
321 | { 150 , 0x00209000 }, | |
322 | { 120 , 0x00148000 }, | |
323 | { 0 , 0 }, | |
324 | }; | |
325 | ||
aacaf9bd | 326 | static struct kauai_timing kauai_udma_timings[] = |
1da177e4 LT |
327 | { |
328 | { 120 , 0x000070c0 }, | |
329 | { 90 , 0x00005d80 }, | |
330 | { 60 , 0x00004a60 }, | |
331 | { 45 , 0x00003a50 }, | |
332 | { 30 , 0x00002a30 }, | |
333 | { 20 , 0x00002921 }, | |
334 | { 0 , 0 }, | |
335 | }; | |
336 | ||
aacaf9bd | 337 | static struct kauai_timing shasta_pio_timings[] = |
1da177e4 LT |
338 | { |
339 | { 930 , 0x08000fff }, | |
340 | { 600 , 0x0A000c97 }, | |
341 | { 383 , 0x07000712 }, | |
342 | { 360 , 0x040003cd }, | |
343 | { 330 , 0x040003cd }, | |
344 | { 300 , 0x040003cd }, | |
345 | { 270 , 0x040003cd }, | |
346 | { 240 , 0x040003cd }, | |
347 | { 239 , 0x040003cd }, | |
348 | { 180 , 0x0400028b }, | |
c15d5d43 BZ |
349 | { 120 , 0x0400010a }, |
350 | { 0 , 0 }, | |
1da177e4 LT |
351 | }; |
352 | ||
aacaf9bd | 353 | static struct kauai_timing shasta_mdma_timings[] = |
1da177e4 LT |
354 | { |
355 | { 1260 , 0x00fff000 }, | |
356 | { 480 , 0x00820800 }, | |
357 | { 360 , 0x00820800 }, | |
358 | { 270 , 0x00820800 }, | |
359 | { 240 , 0x00820800 }, | |
360 | { 210 , 0x00820800 }, | |
361 | { 180 , 0x00820800 }, | |
362 | { 150 , 0x0028b000 }, | |
363 | { 120 , 0x001ca000 }, | |
364 | { 0 , 0 }, | |
365 | }; | |
366 | ||
aacaf9bd | 367 | static struct kauai_timing shasta_udma133_timings[] = |
1da177e4 LT |
368 | { |
369 | { 120 , 0x00035901, }, | |
370 | { 90 , 0x000348b1, }, | |
371 | { 60 , 0x00033881, }, | |
372 | { 45 , 0x00033861, }, | |
373 | { 30 , 0x00033841, }, | |
374 | { 20 , 0x00033031, }, | |
375 | { 15 , 0x00033021, }, | |
376 | { 0 , 0 }, | |
377 | }; | |
378 | ||
379 | ||
380 | static inline u32 | |
381 | kauai_lookup_timing(struct kauai_timing* table, int cycle_time) | |
382 | { | |
383 | int i; | |
384 | ||
385 | for (i=0; table[i].cycle_time; i++) | |
386 | if (cycle_time > table[i+1].cycle_time) | |
387 | return table[i].timing_reg; | |
90a87ea4 | 388 | BUG(); |
1da177e4 LT |
389 | return 0; |
390 | } | |
391 | ||
392 | /* allow up to 256 DBDMA commands per xfer */ | |
393 | #define MAX_DCMDS 256 | |
394 | ||
395 | /* | |
396 | * Wait 1s for disk to answer on IDE bus after a hard reset | |
397 | * of the device (via GPIO/FCR). | |
398 | * | |
399 | * Some devices seem to "pollute" the bus even after dropping | |
400 | * the BSY bit (typically some combo drives slave on the UDMA | |
401 | * bus) after a hard reset. Since we hard reset all drives on | |
402 | * KeyLargo ATA66, we have to keep that delay around. I may end | |
403 | * up not hard resetting anymore on these and keep the delay only | |
404 | * for older interfaces instead (we have to reset when coming | |
405 | * from MacOS...) --BenH. | |
406 | */ | |
407 | #define IDE_WAKEUP_DELAY (1*HZ) | |
408 | ||
0d071922 | 409 | static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); |
1da177e4 | 410 | static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq); |
1da177e4 LT |
411 | static void pmac_ide_selectproc(ide_drive_t *drive); |
412 | static void pmac_ide_kauai_selectproc(ide_drive_t *drive); | |
413 | ||
414 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
415 | ||
23579a2a | 416 | #define PMAC_IDE_REG(x) \ |
4c3032d8 | 417 | ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) |
1da177e4 LT |
418 | |
419 | /* | |
420 | * Apply the timings of the proper unit (master/slave) to the shared | |
421 | * timing register when selecting that unit. This version is for | |
422 | * ASICs with a single timing register | |
423 | */ | |
aacaf9bd | 424 | static void |
1da177e4 LT |
425 | pmac_ide_selectproc(ide_drive_t *drive) |
426 | { | |
427 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
428 | ||
429 | if (pmif == NULL) | |
430 | return; | |
431 | ||
432 | if (drive->select.b.unit & 0x01) | |
433 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
434 | else | |
435 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
436 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
437 | } | |
438 | ||
439 | /* | |
440 | * Apply the timings of the proper unit (master/slave) to the shared | |
441 | * timing register when selecting that unit. This version is for | |
442 | * ASICs with a dual timing register (Kauai) | |
443 | */ | |
aacaf9bd | 444 | static void |
1da177e4 LT |
445 | pmac_ide_kauai_selectproc(ide_drive_t *drive) |
446 | { | |
447 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
448 | ||
449 | if (pmif == NULL) | |
450 | return; | |
451 | ||
452 | if (drive->select.b.unit & 0x01) { | |
453 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
454 | writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
455 | } else { | |
456 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
457 | writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
458 | } | |
459 | (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
460 | } | |
461 | ||
462 | /* | |
463 | * Force an update of controller timing values for a given drive | |
464 | */ | |
aacaf9bd | 465 | static void |
1da177e4 LT |
466 | pmac_ide_do_update_timings(ide_drive_t *drive) |
467 | { | |
468 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
469 | ||
470 | if (pmif == NULL) | |
471 | return; | |
472 | ||
473 | if (pmif->kind == controller_sh_ata6 || | |
474 | pmif->kind == controller_un_ata6 || | |
475 | pmif->kind == controller_k2_ata6) | |
476 | pmac_ide_kauai_selectproc(drive); | |
477 | else | |
478 | pmac_ide_selectproc(drive); | |
479 | } | |
480 | ||
f8c4bd0a | 481 | static void pmac_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port) |
1da177e4 LT |
482 | { |
483 | u32 tmp; | |
484 | ||
485 | writeb(value, (void __iomem *) port); | |
f8c4bd0a BZ |
486 | tmp = readl((void __iomem *)(hwif->io_ports.data_addr |
487 | + IDE_TIMING_CONFIG)); | |
1da177e4 LT |
488 | } |
489 | ||
1da177e4 LT |
490 | /* |
491 | * Old tuning functions (called on hdparm -p), sets up drive PIO timings | |
492 | */ | |
aacaf9bd | 493 | static void |
26bcb879 | 494 | pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 495 | { |
0b46ff2e | 496 | u32 *timings, t; |
1da177e4 LT |
497 | unsigned accessTicks, recTicks; |
498 | unsigned accessTime, recTime; | |
499 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
7dd00083 BZ |
500 | unsigned int cycle_time; |
501 | ||
1da177e4 LT |
502 | if (pmif == NULL) |
503 | return; | |
504 | ||
505 | /* which drive is it ? */ | |
506 | timings = &pmif->timings[drive->select.b.unit & 0x01]; | |
0b46ff2e | 507 | t = *timings; |
1da177e4 | 508 | |
7dd00083 | 509 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 LT |
510 | |
511 | switch (pmif->kind) { | |
512 | case controller_sh_ata6: { | |
513 | /* 133Mhz cell */ | |
7dd00083 | 514 | u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time); |
0b46ff2e | 515 | t = (t & ~TR_133_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
516 | break; |
517 | } | |
518 | case controller_un_ata6: | |
519 | case controller_k2_ata6: { | |
520 | /* 100Mhz cell */ | |
7dd00083 | 521 | u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time); |
0b46ff2e | 522 | t = (t & ~TR_100_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
523 | break; |
524 | } | |
525 | case controller_kl_ata4: | |
526 | /* 66Mhz cell */ | |
7dd00083 | 527 | recTime = cycle_time - ide_pio_timings[pio].active_time |
1da177e4 LT |
528 | - ide_pio_timings[pio].setup_time; |
529 | recTime = max(recTime, 150U); | |
530 | accessTime = ide_pio_timings[pio].active_time; | |
531 | accessTime = max(accessTime, 150U); | |
532 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
533 | accessTicks = min(accessTicks, 0x1fU); | |
534 | recTicks = SYSCLK_TICKS_66(recTime); | |
535 | recTicks = min(recTicks, 0x1fU); | |
0b46ff2e BH |
536 | t = (t & ~TR_66_PIO_MASK) | |
537 | (accessTicks << TR_66_PIO_ACCESS_SHIFT) | | |
538 | (recTicks << TR_66_PIO_RECOVERY_SHIFT); | |
1da177e4 LT |
539 | break; |
540 | default: { | |
541 | /* 33Mhz cell */ | |
542 | int ebit = 0; | |
7dd00083 | 543 | recTime = cycle_time - ide_pio_timings[pio].active_time |
1da177e4 LT |
544 | - ide_pio_timings[pio].setup_time; |
545 | recTime = max(recTime, 150U); | |
546 | accessTime = ide_pio_timings[pio].active_time; | |
547 | accessTime = max(accessTime, 150U); | |
548 | accessTicks = SYSCLK_TICKS(accessTime); | |
549 | accessTicks = min(accessTicks, 0x1fU); | |
550 | accessTicks = max(accessTicks, 4U); | |
551 | recTicks = SYSCLK_TICKS(recTime); | |
552 | recTicks = min(recTicks, 0x1fU); | |
553 | recTicks = max(recTicks, 5U) - 4; | |
554 | if (recTicks > 9) { | |
555 | recTicks--; /* guess, but it's only for PIO0, so... */ | |
556 | ebit = 1; | |
557 | } | |
0b46ff2e | 558 | t = (t & ~TR_33_PIO_MASK) | |
1da177e4 LT |
559 | (accessTicks << TR_33_PIO_ACCESS_SHIFT) | |
560 | (recTicks << TR_33_PIO_RECOVERY_SHIFT); | |
561 | if (ebit) | |
0b46ff2e | 562 | t |= TR_33_PIO_E; |
1da177e4 LT |
563 | break; |
564 | } | |
565 | } | |
566 | ||
567 | #ifdef IDE_PMAC_DEBUG | |
568 | printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", | |
569 | drive->name, pio, *timings); | |
570 | #endif | |
571 | ||
0b46ff2e | 572 | *timings = t; |
c15d5d43 | 573 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
574 | } |
575 | ||
576 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
577 | ||
578 | /* | |
579 | * Calculate KeyLargo ATA/66 UDMA timings | |
580 | */ | |
aacaf9bd | 581 | static int |
1da177e4 LT |
582 | set_timings_udma_ata4(u32 *timings, u8 speed) |
583 | { | |
584 | unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; | |
585 | ||
586 | if (speed > XFER_UDMA_4) | |
587 | return 1; | |
588 | ||
589 | rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause); | |
590 | wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup); | |
591 | addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup); | |
592 | ||
593 | *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) | | |
594 | (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | | |
595 | (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) | | |
596 | (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) | | |
597 | TR_66_UDMA_EN; | |
598 | #ifdef IDE_PMAC_DEBUG | |
599 | printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", | |
600 | speed & 0xf, *timings); | |
601 | #endif | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | /* | |
607 | * Calculate Kauai ATA/100 UDMA timings | |
608 | */ | |
aacaf9bd | 609 | static int |
1da177e4 LT |
610 | set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
611 | { | |
612 | struct ide_timing *t = ide_timing_find_mode(speed); | |
613 | u32 tr; | |
614 | ||
615 | if (speed > XFER_UDMA_5 || t == NULL) | |
616 | return 1; | |
617 | tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma); | |
1da177e4 LT |
618 | *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr; |
619 | *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN; | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Calculate Shasta ATA/133 UDMA timings | |
626 | */ | |
aacaf9bd | 627 | static int |
1da177e4 LT |
628 | set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
629 | { | |
630 | struct ide_timing *t = ide_timing_find_mode(speed); | |
631 | u32 tr; | |
632 | ||
633 | if (speed > XFER_UDMA_6 || t == NULL) | |
634 | return 1; | |
635 | tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma); | |
1da177e4 LT |
636 | *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr; |
637 | *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN; | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | /* | |
643 | * Calculate MDMA timings for all cells | |
644 | */ | |
90f72eca | 645 | static void |
1da177e4 | 646 | set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, |
90f72eca | 647 | u8 speed) |
1da177e4 LT |
648 | { |
649 | int cycleTime, accessTime = 0, recTime = 0; | |
650 | unsigned accessTicks, recTicks; | |
90f72eca | 651 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
652 | struct mdma_timings_t* tm = NULL; |
653 | int i; | |
654 | ||
655 | /* Get default cycle time for mode */ | |
656 | switch(speed & 0xf) { | |
657 | case 0: cycleTime = 480; break; | |
658 | case 1: cycleTime = 150; break; | |
659 | case 2: cycleTime = 120; break; | |
660 | default: | |
90f72eca BZ |
661 | BUG(); |
662 | break; | |
1da177e4 | 663 | } |
90f72eca BZ |
664 | |
665 | /* Check if drive provides explicit DMA cycle time */ | |
666 | if ((id->field_valid & 2) && id->eide_dma_time) | |
667 | cycleTime = max_t(int, id->eide_dma_time, cycleTime); | |
668 | ||
1da177e4 LT |
669 | /* OHare limits according to some old Apple sources */ |
670 | if ((intf_type == controller_ohare) && (cycleTime < 150)) | |
671 | cycleTime = 150; | |
672 | /* Get the proper timing array for this controller */ | |
673 | switch(intf_type) { | |
674 | case controller_sh_ata6: | |
675 | case controller_un_ata6: | |
676 | case controller_k2_ata6: | |
677 | break; | |
678 | case controller_kl_ata4: | |
679 | tm = mdma_timings_66; | |
680 | break; | |
681 | case controller_kl_ata3: | |
682 | tm = mdma_timings_33k; | |
683 | break; | |
684 | default: | |
685 | tm = mdma_timings_33; | |
686 | break; | |
687 | } | |
688 | if (tm != NULL) { | |
689 | /* Lookup matching access & recovery times */ | |
690 | i = -1; | |
691 | for (;;) { | |
692 | if (tm[i+1].cycleTime < cycleTime) | |
693 | break; | |
694 | i++; | |
695 | } | |
1da177e4 LT |
696 | cycleTime = tm[i].cycleTime; |
697 | accessTime = tm[i].accessTime; | |
698 | recTime = tm[i].recoveryTime; | |
699 | ||
700 | #ifdef IDE_PMAC_DEBUG | |
701 | printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", | |
702 | drive->name, cycleTime, accessTime, recTime); | |
703 | #endif | |
704 | } | |
705 | switch(intf_type) { | |
706 | case controller_sh_ata6: { | |
707 | /* 133Mhz cell */ | |
708 | u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime); | |
1da177e4 LT |
709 | *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr; |
710 | *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN; | |
711 | } | |
712 | case controller_un_ata6: | |
713 | case controller_k2_ata6: { | |
714 | /* 100Mhz cell */ | |
715 | u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime); | |
1da177e4 LT |
716 | *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr; |
717 | *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN; | |
718 | } | |
719 | break; | |
720 | case controller_kl_ata4: | |
721 | /* 66Mhz cell */ | |
722 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
723 | accessTicks = min(accessTicks, 0x1fU); | |
724 | accessTicks = max(accessTicks, 0x1U); | |
725 | recTicks = SYSCLK_TICKS_66(recTime); | |
726 | recTicks = min(recTicks, 0x1fU); | |
727 | recTicks = max(recTicks, 0x3U); | |
728 | /* Clear out mdma bits and disable udma */ | |
729 | *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) | | |
730 | (accessTicks << TR_66_MDMA_ACCESS_SHIFT) | | |
731 | (recTicks << TR_66_MDMA_RECOVERY_SHIFT); | |
732 | break; | |
733 | case controller_kl_ata3: | |
734 | /* 33Mhz cell on KeyLargo */ | |
735 | accessTicks = SYSCLK_TICKS(accessTime); | |
736 | accessTicks = max(accessTicks, 1U); | |
737 | accessTicks = min(accessTicks, 0x1fU); | |
738 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
739 | recTicks = SYSCLK_TICKS(recTime); | |
740 | recTicks = max(recTicks, 1U); | |
741 | recTicks = min(recTicks, 0x1fU); | |
742 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
743 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
744 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
745 | break; | |
746 | default: { | |
747 | /* 33Mhz cell on others */ | |
748 | int halfTick = 0; | |
749 | int origAccessTime = accessTime; | |
750 | int origRecTime = recTime; | |
751 | ||
752 | accessTicks = SYSCLK_TICKS(accessTime); | |
753 | accessTicks = max(accessTicks, 1U); | |
754 | accessTicks = min(accessTicks, 0x1fU); | |
755 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
756 | recTicks = SYSCLK_TICKS(recTime); | |
757 | recTicks = max(recTicks, 2U) - 1; | |
758 | recTicks = min(recTicks, 0x1fU); | |
759 | recTime = (recTicks + 1) * IDE_SYSCLK_NS; | |
760 | if ((accessTicks > 1) && | |
761 | ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) && | |
762 | ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) { | |
763 | halfTick = 1; | |
764 | accessTicks--; | |
765 | } | |
766 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
767 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
768 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
769 | if (halfTick) | |
770 | *timings |= TR_33_MDMA_HALFTICK; | |
771 | } | |
772 | } | |
773 | #ifdef IDE_PMAC_DEBUG | |
774 | printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", | |
775 | drive->name, speed & 0xf, *timings); | |
776 | #endif | |
1da177e4 LT |
777 | } |
778 | #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
779 | ||
88b2b32b | 780 | static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
781 | { |
782 | int unit = (drive->select.b.unit & 0x01); | |
783 | int ret = 0; | |
784 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
085798b1 | 785 | u32 *timings, *timings2, tl[2]; |
1da177e4 | 786 | |
1da177e4 LT |
787 | timings = &pmif->timings[unit]; |
788 | timings2 = &pmif->timings[unit+2]; | |
085798b1 BZ |
789 | |
790 | /* Copy timings to local image */ | |
791 | tl[0] = *timings; | |
792 | tl[1] = *timings2; | |
793 | ||
1da177e4 | 794 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC |
4db90a14 BZ |
795 | if (speed >= XFER_UDMA_0) { |
796 | if (pmif->kind == controller_kl_ata4) | |
797 | ret = set_timings_udma_ata4(&tl[0], speed); | |
798 | else if (pmif->kind == controller_un_ata6 | |
799 | || pmif->kind == controller_k2_ata6) | |
800 | ret = set_timings_udma_ata6(&tl[0], &tl[1], speed); | |
801 | else if (pmif->kind == controller_sh_ata6) | |
802 | ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); | |
803 | else | |
804 | ret = -1; | |
805 | } else | |
806 | set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); | |
1da177e4 | 807 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ |
1da177e4 | 808 | if (ret) |
88b2b32b | 809 | return; |
085798b1 BZ |
810 | |
811 | /* Apply timings to controller */ | |
812 | *timings = tl[0]; | |
813 | *timings2 = tl[1]; | |
814 | ||
1da177e4 | 815 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
816 | } |
817 | ||
818 | /* | |
819 | * Blast some well known "safe" values to the timing registers at init or | |
820 | * wakeup from sleep time, before we do real calculation | |
821 | */ | |
aacaf9bd | 822 | static void |
1da177e4 LT |
823 | sanitize_timings(pmac_ide_hwif_t *pmif) |
824 | { | |
825 | unsigned int value, value2 = 0; | |
826 | ||
827 | switch(pmif->kind) { | |
828 | case controller_sh_ata6: | |
829 | value = 0x0a820c97; | |
830 | value2 = 0x00033031; | |
831 | break; | |
832 | case controller_un_ata6: | |
833 | case controller_k2_ata6: | |
834 | value = 0x08618a92; | |
835 | value2 = 0x00002921; | |
836 | break; | |
837 | case controller_kl_ata4: | |
838 | value = 0x0008438c; | |
839 | break; | |
840 | case controller_kl_ata3: | |
841 | value = 0x00084526; | |
842 | break; | |
843 | case controller_heathrow: | |
844 | case controller_ohare: | |
845 | default: | |
846 | value = 0x00074526; | |
847 | break; | |
848 | } | |
849 | pmif->timings[0] = pmif->timings[1] = value; | |
850 | pmif->timings[2] = pmif->timings[3] = value2; | |
851 | } | |
852 | ||
1da177e4 LT |
853 | /* Suspend call back, should be called after the child devices |
854 | * have actually been suspended | |
855 | */ | |
856 | static int | |
857 | pmac_ide_do_suspend(ide_hwif_t *hwif) | |
858 | { | |
859 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
860 | ||
861 | /* We clear the timings */ | |
862 | pmif->timings[0] = 0; | |
863 | pmif->timings[1] = 0; | |
864 | ||
616299af BH |
865 | disable_irq(pmif->irq); |
866 | ||
1da177e4 LT |
867 | /* The media bay will handle itself just fine */ |
868 | if (pmif->mediabay) | |
869 | return 0; | |
870 | ||
871 | /* Kauai has bus control FCRs directly here */ | |
872 | if (pmif->kauai_fcr) { | |
873 | u32 fcr = readl(pmif->kauai_fcr); | |
874 | fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); | |
875 | writel(fcr, pmif->kauai_fcr); | |
876 | } | |
877 | ||
878 | /* Disable the bus on older machines and the cell on kauai */ | |
879 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, | |
880 | 0); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | /* Resume call back, should be called before the child devices | |
886 | * are resumed | |
887 | */ | |
888 | static int | |
889 | pmac_ide_do_resume(ide_hwif_t *hwif) | |
890 | { | |
891 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
892 | ||
893 | /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ | |
894 | if (!pmif->mediabay) { | |
895 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); | |
896 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); | |
897 | msleep(10); | |
898 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0); | |
1da177e4 LT |
899 | |
900 | /* Kauai has it different */ | |
901 | if (pmif->kauai_fcr) { | |
902 | u32 fcr = readl(pmif->kauai_fcr); | |
903 | fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; | |
904 | writel(fcr, pmif->kauai_fcr); | |
905 | } | |
616299af BH |
906 | |
907 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1da177e4 LT |
908 | } |
909 | ||
910 | /* Sanitize drive timings */ | |
911 | sanitize_timings(pmif); | |
912 | ||
616299af BH |
913 | enable_irq(pmif->irq); |
914 | ||
1da177e4 LT |
915 | return 0; |
916 | } | |
917 | ||
07a6c66d BZ |
918 | static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) |
919 | { | |
920 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)ide_get_hwifdata(hwif); | |
921 | struct device_node *np = pmif->node; | |
922 | const char *cable = of_get_property(np, "cable-type", NULL); | |
923 | ||
924 | /* Get cable type from device-tree. */ | |
925 | if (cable && !strncmp(cable, "80-", 3)) | |
926 | return ATA_CBL_PATA80; | |
927 | ||
928 | /* | |
929 | * G5's seem to have incorrect cable type in device-tree. | |
930 | * Let's assume they have a 80 conductor cable, this seem | |
931 | * to be always the case unless the user mucked around. | |
932 | */ | |
933 | if (of_device_is_compatible(np, "K2-UATA") || | |
934 | of_device_is_compatible(np, "shasta-ata")) | |
935 | return ATA_CBL_PATA80; | |
936 | ||
937 | return ATA_CBL_PATA40; | |
938 | } | |
939 | ||
ac95beed BZ |
940 | static const struct ide_port_ops pmac_ide_ata6_port_ops = { |
941 | .set_pio_mode = pmac_ide_set_pio_mode, | |
942 | .set_dma_mode = pmac_ide_set_dma_mode, | |
943 | .selectproc = pmac_ide_kauai_selectproc, | |
07a6c66d BZ |
944 | .cable_detect = pmac_ide_cable_detect, |
945 | }; | |
946 | ||
947 | static const struct ide_port_ops pmac_ide_ata4_port_ops = { | |
948 | .set_pio_mode = pmac_ide_set_pio_mode, | |
949 | .set_dma_mode = pmac_ide_set_dma_mode, | |
950 | .selectproc = pmac_ide_selectproc, | |
951 | .cable_detect = pmac_ide_cable_detect, | |
ac95beed BZ |
952 | }; |
953 | ||
954 | static const struct ide_port_ops pmac_ide_port_ops = { | |
955 | .set_pio_mode = pmac_ide_set_pio_mode, | |
956 | .set_dma_mode = pmac_ide_set_dma_mode, | |
957 | .selectproc = pmac_ide_selectproc, | |
958 | }; | |
959 | ||
f37afdac | 960 | static const struct ide_dma_ops pmac_dma_ops; |
5e37bdc0 | 961 | |
c413b9b9 | 962 | static const struct ide_port_info pmac_port_info = { |
0d071922 | 963 | .init_dma = pmac_ide_init_dma, |
c413b9b9 | 964 | .chipset = ide_pmac, |
5e37bdc0 BZ |
965 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC |
966 | .dma_ops = &pmac_dma_ops, | |
967 | #endif | |
ac95beed | 968 | .port_ops = &pmac_ide_port_ops, |
c413b9b9 | 969 | .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | |
c413b9b9 | 970 | IDE_HFLAG_POST_SET_MODE | |
c5dd43ec | 971 | IDE_HFLAG_MMIO | |
c413b9b9 BZ |
972 | IDE_HFLAG_UNMASK_IRQS, |
973 | .pio_mask = ATA_PIO4, | |
974 | .mwdma_mask = ATA_MWDMA2, | |
975 | }; | |
976 | ||
1da177e4 LT |
977 | /* |
978 | * Setup, register & probe an IDE channel driven by this driver, this is | |
5b16464a | 979 | * called by one of the 2 probe functions (macio or PCI). |
1da177e4 | 980 | */ |
468e4681 | 981 | static int __devinit |
57c802e8 | 982 | pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) |
1da177e4 LT |
983 | { |
984 | struct device_node *np = pmif->node; | |
018a3d1d | 985 | const int *bidp; |
8447d9d5 | 986 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
c413b9b9 | 987 | struct ide_port_info d = pmac_port_info; |
1da177e4 | 988 | |
1da177e4 | 989 | pmif->broken_dma = pmif->broken_dma_warn = 0; |
c413b9b9 | 990 | if (of_device_is_compatible(np, "shasta-ata")) { |
1da177e4 | 991 | pmif->kind = controller_sh_ata6; |
ac95beed | 992 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
993 | d.udma_mask = ATA_UDMA6; |
994 | } else if (of_device_is_compatible(np, "kauai-ata")) { | |
1da177e4 | 995 | pmif->kind = controller_un_ata6; |
ac95beed | 996 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
997 | d.udma_mask = ATA_UDMA5; |
998 | } else if (of_device_is_compatible(np, "K2-UATA")) { | |
1da177e4 | 999 | pmif->kind = controller_k2_ata6; |
ac95beed | 1000 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1001 | d.udma_mask = ATA_UDMA5; |
1002 | } else if (of_device_is_compatible(np, "keylargo-ata")) { | |
1003 | if (strcmp(np->name, "ata-4") == 0) { | |
1da177e4 | 1004 | pmif->kind = controller_kl_ata4; |
07a6c66d | 1005 | d.port_ops = &pmac_ide_ata4_port_ops; |
c413b9b9 BZ |
1006 | d.udma_mask = ATA_UDMA4; |
1007 | } else | |
1da177e4 | 1008 | pmif->kind = controller_kl_ata3; |
c413b9b9 | 1009 | } else if (of_device_is_compatible(np, "heathrow-ata")) { |
1da177e4 | 1010 | pmif->kind = controller_heathrow; |
c413b9b9 | 1011 | } else { |
1da177e4 LT |
1012 | pmif->kind = controller_ohare; |
1013 | pmif->broken_dma = 1; | |
1014 | } | |
1015 | ||
40cd3a45 | 1016 | bidp = of_get_property(np, "AAPL,bus-id", NULL); |
1da177e4 LT |
1017 | pmif->aapl_bus_id = bidp ? *bidp : 0; |
1018 | ||
1da177e4 LT |
1019 | /* On Kauai-type controllers, we make sure the FCR is correct */ |
1020 | if (pmif->kauai_fcr) | |
1021 | writel(KAUAI_FCR_UATA_MAGIC | | |
1022 | KAUAI_FCR_UATA_RESET_N | | |
1023 | KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); | |
1024 | ||
1025 | pmif->mediabay = 0; | |
1026 | ||
1027 | /* Make sure we have sane timings */ | |
1028 | sanitize_timings(pmif); | |
1029 | ||
1030 | #ifndef CONFIG_PPC64 | |
1031 | /* XXX FIXME: Media bay stuff need re-organizing */ | |
1032 | if (np->parent && np->parent->name | |
1033 | && strcasecmp(np->parent->name, "media-bay") == 0) { | |
8c870933 | 1034 | #ifdef CONFIG_PMAC_MEDIABAY |
2dde7861 BZ |
1035 | media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, |
1036 | hwif); | |
8c870933 | 1037 | #endif /* CONFIG_PMAC_MEDIABAY */ |
1da177e4 LT |
1038 | pmif->mediabay = 1; |
1039 | if (!bidp) | |
1040 | pmif->aapl_bus_id = 1; | |
1041 | } else if (pmif->kind == controller_ohare) { | |
1042 | /* The code below is having trouble on some ohare machines | |
1043 | * (timing related ?). Until I can put my hand on one of these | |
1044 | * units, I keep the old way | |
1045 | */ | |
1046 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); | |
1047 | } else | |
1048 | #endif | |
1049 | { | |
1050 | /* This is necessary to enable IDE when net-booting */ | |
1051 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); | |
1052 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); | |
1053 | msleep(10); | |
1054 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0); | |
1055 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1056 | } | |
1057 | ||
1058 | /* Setup MMIO ops */ | |
1059 | default_hwif_mmiops(hwif); | |
1060 | hwif->OUTBSYNC = pmac_outbsync; | |
1061 | ||
1da177e4 | 1062 | hwif->hwif_data = pmif; |
57c802e8 | 1063 | ide_init_port_hw(hwif, hw); |
1da177e4 | 1064 | |
1da177e4 LT |
1065 | printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", |
1066 | hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, | |
1067 | pmif->mediabay ? " (mediabay)" : "", hwif->irq); | |
e53cd458 BZ |
1068 | |
1069 | if (pmif->mediabay) { | |
8c870933 | 1070 | #ifdef CONFIG_PMAC_MEDIABAY |
e53cd458 BZ |
1071 | if (check_media_bay_by_base(pmif->regbase, MB_CD)) { |
1072 | #else | |
1073 | if (1) { | |
1074 | #endif | |
1075 | hwif->drives[0].noprobe = 1; | |
1076 | hwif->drives[1].noprobe = 1; | |
1077 | } | |
1078 | } | |
1da177e4 | 1079 | |
8447d9d5 | 1080 | idx[0] = hwif->index; |
1da177e4 | 1081 | |
c413b9b9 | 1082 | ide_device_add(idx, &d); |
5cbf79cd | 1083 | |
1da177e4 LT |
1084 | return 0; |
1085 | } | |
1086 | ||
5c58666f BZ |
1087 | static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base) |
1088 | { | |
1089 | int i; | |
1090 | ||
1091 | for (i = 0; i < 8; ++i) | |
4c3032d8 BZ |
1092 | hw->io_ports_array[i] = base + i * 0x10; |
1093 | ||
1094 | hw->io_ports.ctl_addr = base + 0x160; | |
5c58666f BZ |
1095 | } |
1096 | ||
1da177e4 LT |
1097 | /* |
1098 | * Attach to a macio probed interface | |
1099 | */ | |
1100 | static int __devinit | |
5e655772 | 1101 | pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
1102 | { |
1103 | void __iomem *base; | |
1104 | unsigned long regbase; | |
1da177e4 LT |
1105 | ide_hwif_t *hwif; |
1106 | pmac_ide_hwif_t *pmif; | |
939b0f1d | 1107 | int irq, rc; |
57c802e8 | 1108 | hw_regs_t hw; |
1da177e4 | 1109 | |
5297a3e5 BZ |
1110 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); |
1111 | if (pmif == NULL) | |
1112 | return -ENOMEM; | |
1113 | ||
939b0f1d BZ |
1114 | hwif = ide_find_port(); |
1115 | if (hwif == NULL) { | |
1da177e4 LT |
1116 | printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n"); |
1117 | printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1118 | rc = -ENODEV; |
1119 | goto out_free_pmif; | |
1da177e4 LT |
1120 | } |
1121 | ||
cc5d0189 | 1122 | if (macio_resource_count(mdev) == 0) { |
939b0f1d BZ |
1123 | printk(KERN_WARNING "ide-pmac: no address for %s\n", |
1124 | mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1125 | rc = -ENXIO; |
1126 | goto out_free_pmif; | |
1da177e4 LT |
1127 | } |
1128 | ||
1129 | /* Request memory resource for IO ports */ | |
1130 | if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) { | |
939b0f1d BZ |
1131 | printk(KERN_ERR "ide-pmac: can't request MMIO resource for " |
1132 | "%s!\n", mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1133 | rc = -EBUSY; |
1134 | goto out_free_pmif; | |
1da177e4 LT |
1135 | } |
1136 | ||
1137 | /* XXX This is bogus. Should be fixed in the registry by checking | |
1138 | * the kind of host interrupt controller, a bit like gatwick | |
1139 | * fixes in irq.c. That works well enough for the single case | |
1140 | * where that happens though... | |
1141 | */ | |
1142 | if (macio_irq_count(mdev) == 0) { | |
939b0f1d BZ |
1143 | printk(KERN_WARNING "ide-pmac: no intrs for device %s, using " |
1144 | "13\n", mdev->ofdev.node->full_name); | |
69917c26 | 1145 | irq = irq_create_mapping(NULL, 13); |
1da177e4 LT |
1146 | } else |
1147 | irq = macio_irq(mdev, 0); | |
1148 | ||
1149 | base = ioremap(macio_resource_start(mdev, 0), 0x400); | |
1150 | regbase = (unsigned long) base; | |
1151 | ||
36501650 | 1152 | hwif->dev = &mdev->bus->pdev->dev; |
1da177e4 LT |
1153 | |
1154 | pmif->mdev = mdev; | |
1155 | pmif->node = mdev->ofdev.node; | |
1156 | pmif->regbase = regbase; | |
1157 | pmif->irq = irq; | |
1158 | pmif->kauai_fcr = NULL; | |
1159 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1160 | if (macio_resource_count(mdev) >= 2) { | |
1161 | if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) | |
939b0f1d BZ |
1162 | printk(KERN_WARNING "ide-pmac: can't request DMA " |
1163 | "resource for %s!\n", | |
1164 | mdev->ofdev.node->full_name); | |
1da177e4 LT |
1165 | else |
1166 | pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); | |
1167 | } else | |
1168 | pmif->dma_regs = NULL; | |
1169 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1170 | dev_set_drvdata(&mdev->ofdev.dev, hwif); | |
1171 | ||
57c802e8 | 1172 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1173 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 BZ |
1174 | hw.irq = irq; |
1175 | hw.dev = &mdev->ofdev.dev; | |
1176 | ||
1177 | rc = pmac_ide_setup_device(pmif, hwif, &hw); | |
1da177e4 LT |
1178 | if (rc != 0) { |
1179 | /* The inteface is released to the common IDE layer */ | |
1180 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1181 | iounmap(base); | |
ed908fa1 | 1182 | if (pmif->dma_regs) { |
1da177e4 | 1183 | iounmap(pmif->dma_regs); |
ed908fa1 BZ |
1184 | macio_release_resource(mdev, 1); |
1185 | } | |
1da177e4 | 1186 | macio_release_resource(mdev, 0); |
5297a3e5 | 1187 | kfree(pmif); |
1da177e4 LT |
1188 | } |
1189 | ||
1190 | return rc; | |
5297a3e5 BZ |
1191 | |
1192 | out_free_pmif: | |
1193 | kfree(pmif); | |
1194 | return rc; | |
1da177e4 LT |
1195 | } |
1196 | ||
1197 | static int | |
8b4b8a24 | 1198 | pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) |
1da177e4 LT |
1199 | { |
1200 | ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1201 | int rc = 0; | |
1202 | ||
8b4b8a24 | 1203 | if (mesg.event != mdev->ofdev.dev.power.power_state.event |
3a2d5b70 | 1204 | && (mesg.event & PM_EVENT_SLEEP)) { |
1da177e4 LT |
1205 | rc = pmac_ide_do_suspend(hwif); |
1206 | if (rc == 0) | |
8b4b8a24 | 1207 | mdev->ofdev.dev.power.power_state = mesg; |
1da177e4 LT |
1208 | } |
1209 | ||
1210 | return rc; | |
1211 | } | |
1212 | ||
1213 | static int | |
1214 | pmac_ide_macio_resume(struct macio_dev *mdev) | |
1215 | { | |
1216 | ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1217 | int rc = 0; | |
1218 | ||
ca078bae | 1219 | if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) { |
1da177e4 LT |
1220 | rc = pmac_ide_do_resume(hwif); |
1221 | if (rc == 0) | |
829ca9a3 | 1222 | mdev->ofdev.dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1223 | } |
1224 | ||
1225 | return rc; | |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * Attach to a PCI probed interface | |
1230 | */ | |
1231 | static int __devinit | |
1232 | pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) | |
1233 | { | |
1234 | ide_hwif_t *hwif; | |
1235 | struct device_node *np; | |
1236 | pmac_ide_hwif_t *pmif; | |
1237 | void __iomem *base; | |
1238 | unsigned long rbase, rlen; | |
939b0f1d | 1239 | int rc; |
57c802e8 | 1240 | hw_regs_t hw; |
1da177e4 LT |
1241 | |
1242 | np = pci_device_to_OF_node(pdev); | |
1243 | if (np == NULL) { | |
1244 | printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n"); | |
1245 | return -ENODEV; | |
1246 | } | |
5297a3e5 BZ |
1247 | |
1248 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); | |
1249 | if (pmif == NULL) | |
1250 | return -ENOMEM; | |
1251 | ||
939b0f1d BZ |
1252 | hwif = ide_find_port(); |
1253 | if (hwif == NULL) { | |
1da177e4 LT |
1254 | printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n"); |
1255 | printk(KERN_ERR " %s\n", np->full_name); | |
5297a3e5 BZ |
1256 | rc = -ENODEV; |
1257 | goto out_free_pmif; | |
1da177e4 LT |
1258 | } |
1259 | ||
1da177e4 | 1260 | if (pci_enable_device(pdev)) { |
939b0f1d BZ |
1261 | printk(KERN_WARNING "ide-pmac: Can't enable PCI device for " |
1262 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1263 | rc = -ENXIO; |
1264 | goto out_free_pmif; | |
1da177e4 LT |
1265 | } |
1266 | pci_set_master(pdev); | |
1267 | ||
1268 | if (pci_request_regions(pdev, "Kauai ATA")) { | |
939b0f1d BZ |
1269 | printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for " |
1270 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1271 | rc = -ENXIO; |
1272 | goto out_free_pmif; | |
1da177e4 LT |
1273 | } |
1274 | ||
36501650 | 1275 | hwif->dev = &pdev->dev; |
1da177e4 LT |
1276 | pmif->mdev = NULL; |
1277 | pmif->node = np; | |
1278 | ||
1279 | rbase = pci_resource_start(pdev, 0); | |
1280 | rlen = pci_resource_len(pdev, 0); | |
1281 | ||
1282 | base = ioremap(rbase, rlen); | |
1283 | pmif->regbase = (unsigned long) base + 0x2000; | |
1284 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1285 | pmif->dma_regs = base + 0x1000; | |
1286 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1287 | pmif->kauai_fcr = base; | |
1288 | pmif->irq = pdev->irq; | |
1289 | ||
1290 | pci_set_drvdata(pdev, hwif); | |
1291 | ||
57c802e8 | 1292 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1293 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 BZ |
1294 | hw.irq = pdev->irq; |
1295 | hw.dev = &pdev->dev; | |
1296 | ||
1297 | rc = pmac_ide_setup_device(pmif, hwif, &hw); | |
1da177e4 LT |
1298 | if (rc != 0) { |
1299 | /* The inteface is released to the common IDE layer */ | |
1300 | pci_set_drvdata(pdev, NULL); | |
1301 | iounmap(base); | |
1da177e4 | 1302 | pci_release_regions(pdev); |
5297a3e5 | 1303 | kfree(pmif); |
1da177e4 LT |
1304 | } |
1305 | ||
1306 | return rc; | |
5297a3e5 BZ |
1307 | |
1308 | out_free_pmif: | |
1309 | kfree(pmif); | |
1310 | return rc; | |
1da177e4 LT |
1311 | } |
1312 | ||
1313 | static int | |
8b4b8a24 | 1314 | pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1da177e4 LT |
1315 | { |
1316 | ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev); | |
1317 | int rc = 0; | |
1318 | ||
8b4b8a24 | 1319 | if (mesg.event != pdev->dev.power.power_state.event |
3a2d5b70 | 1320 | && (mesg.event & PM_EVENT_SLEEP)) { |
1da177e4 LT |
1321 | rc = pmac_ide_do_suspend(hwif); |
1322 | if (rc == 0) | |
8b4b8a24 | 1323 | pdev->dev.power.power_state = mesg; |
1da177e4 LT |
1324 | } |
1325 | ||
1326 | return rc; | |
1327 | } | |
1328 | ||
1329 | static int | |
1330 | pmac_ide_pci_resume(struct pci_dev *pdev) | |
1331 | { | |
1332 | ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev); | |
1333 | int rc = 0; | |
1334 | ||
ca078bae | 1335 | if (pdev->dev.power.power_state.event != PM_EVENT_ON) { |
1da177e4 LT |
1336 | rc = pmac_ide_do_resume(hwif); |
1337 | if (rc == 0) | |
829ca9a3 | 1338 | pdev->dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1339 | } |
1340 | ||
1341 | return rc; | |
1342 | } | |
1343 | ||
5e655772 | 1344 | static struct of_device_id pmac_ide_macio_match[] = |
1da177e4 LT |
1345 | { |
1346 | { | |
1347 | .name = "IDE", | |
1da177e4 LT |
1348 | }, |
1349 | { | |
1350 | .name = "ATA", | |
1da177e4 LT |
1351 | }, |
1352 | { | |
1da177e4 | 1353 | .type = "ide", |
1da177e4 LT |
1354 | }, |
1355 | { | |
1da177e4 | 1356 | .type = "ata", |
1da177e4 LT |
1357 | }, |
1358 | {}, | |
1359 | }; | |
1360 | ||
1361 | static struct macio_driver pmac_ide_macio_driver = | |
1362 | { | |
1363 | .name = "ide-pmac", | |
1364 | .match_table = pmac_ide_macio_match, | |
1365 | .probe = pmac_ide_macio_attach, | |
1366 | .suspend = pmac_ide_macio_suspend, | |
1367 | .resume = pmac_ide_macio_resume, | |
1368 | }; | |
1369 | ||
9cbcc5e3 BZ |
1370 | static const struct pci_device_id pmac_ide_pci_match[] = { |
1371 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, | |
1372 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, | |
1373 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, | |
1374 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, | |
1375 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, | |
71e4eda8 | 1376 | {}, |
1da177e4 LT |
1377 | }; |
1378 | ||
1379 | static struct pci_driver pmac_ide_pci_driver = { | |
1380 | .name = "ide-pmac", | |
1381 | .id_table = pmac_ide_pci_match, | |
1382 | .probe = pmac_ide_pci_attach, | |
1383 | .suspend = pmac_ide_pci_suspend, | |
1384 | .resume = pmac_ide_pci_resume, | |
1385 | }; | |
1386 | MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match); | |
1387 | ||
9e5755bc | 1388 | int __init pmac_ide_probe(void) |
1da177e4 | 1389 | { |
9e5755bc AM |
1390 | int error; |
1391 | ||
e8222502 | 1392 | if (!machine_is(powermac)) |
9e5755bc | 1393 | return -ENODEV; |
1da177e4 LT |
1394 | |
1395 | #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST | |
9e5755bc AM |
1396 | error = pci_register_driver(&pmac_ide_pci_driver); |
1397 | if (error) | |
1398 | goto out; | |
1399 | error = macio_register_driver(&pmac_ide_macio_driver); | |
1400 | if (error) { | |
1401 | pci_unregister_driver(&pmac_ide_pci_driver); | |
1402 | goto out; | |
1403 | } | |
1da177e4 | 1404 | #else |
9e5755bc AM |
1405 | error = macio_register_driver(&pmac_ide_macio_driver); |
1406 | if (error) | |
1407 | goto out; | |
1408 | error = pci_register_driver(&pmac_ide_pci_driver); | |
1409 | if (error) { | |
1410 | macio_unregister_driver(&pmac_ide_macio_driver); | |
1411 | goto out; | |
1412 | } | |
1beb6a7d | 1413 | #endif |
9e5755bc AM |
1414 | out: |
1415 | return error; | |
1da177e4 LT |
1416 | } |
1417 | ||
1418 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1419 | ||
1420 | /* | |
1421 | * pmac_ide_build_dmatable builds the DBDMA command list | |
1422 | * for a transfer and sets the DBDMA channel to point to it. | |
1423 | */ | |
aacaf9bd | 1424 | static int |
1da177e4 LT |
1425 | pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) |
1426 | { | |
1427 | struct dbdma_cmd *table; | |
1428 | int i, count = 0; | |
1429 | ide_hwif_t *hwif = HWIF(drive); | |
1430 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
1431 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; | |
1432 | struct scatterlist *sg; | |
1433 | int wr = (rq_data_dir(rq) == WRITE); | |
1434 | ||
1435 | /* DMA table is already aligned */ | |
1436 | table = (struct dbdma_cmd *) pmif->dma_table_cpu; | |
1437 | ||
1438 | /* Make sure DMA controller is stopped (necessary ?) */ | |
1439 | writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); | |
1440 | while (readl(&dma->status) & RUN) | |
1441 | udelay(1); | |
1442 | ||
1443 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
1444 | ||
1445 | if (!i) | |
1446 | return 0; | |
1447 | ||
1448 | /* Build DBDMA commands list */ | |
1449 | sg = hwif->sg_table; | |
1450 | while (i && sg_dma_len(sg)) { | |
1451 | u32 cur_addr; | |
1452 | u32 cur_len; | |
1453 | ||
1454 | cur_addr = sg_dma_address(sg); | |
1455 | cur_len = sg_dma_len(sg); | |
1456 | ||
1457 | if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) { | |
1458 | if (pmif->broken_dma_warn == 0) { | |
aca38a51 | 1459 | printk(KERN_WARNING "%s: DMA on non aligned address, " |
1da177e4 LT |
1460 | "switching to PIO on Ohare chipset\n", drive->name); |
1461 | pmif->broken_dma_warn = 1; | |
1462 | } | |
1463 | goto use_pio_instead; | |
1464 | } | |
1465 | while (cur_len) { | |
1466 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
1467 | ||
1468 | if (count++ >= MAX_DCMDS) { | |
1469 | printk(KERN_WARNING "%s: DMA table too small\n", | |
1470 | drive->name); | |
1471 | goto use_pio_instead; | |
1472 | } | |
1473 | st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE); | |
1474 | st_le16(&table->req_count, tc); | |
1475 | st_le32(&table->phy_addr, cur_addr); | |
1476 | table->cmd_dep = 0; | |
1477 | table->xfer_status = 0; | |
1478 | table->res_count = 0; | |
1479 | cur_addr += tc; | |
1480 | cur_len -= tc; | |
1481 | ++table; | |
1482 | } | |
55c16a70 | 1483 | sg = sg_next(sg); |
1da177e4 LT |
1484 | i--; |
1485 | } | |
1486 | ||
1487 | /* convert the last command to an input/output last command */ | |
1488 | if (count) { | |
1489 | st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST); | |
1490 | /* add the stop command to the end of the list */ | |
1491 | memset(table, 0, sizeof(struct dbdma_cmd)); | |
1492 | st_le16(&table->command, DBDMA_STOP); | |
1493 | mb(); | |
1494 | writel(hwif->dmatable_dma, &dma->cmdptr); | |
1495 | return 1; | |
1496 | } | |
1497 | ||
1498 | printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name); | |
f6fb786d BZ |
1499 | |
1500 | use_pio_instead: | |
1501 | ide_destroy_dmatable(drive); | |
1502 | ||
1da177e4 LT |
1503 | return 0; /* revert to PIO for this request */ |
1504 | } | |
1505 | ||
1506 | /* Teardown mappings after DMA has completed. */ | |
aacaf9bd | 1507 | static void |
1da177e4 LT |
1508 | pmac_ide_destroy_dmatable (ide_drive_t *drive) |
1509 | { | |
1510 | ide_hwif_t *hwif = drive->hwif; | |
1da177e4 | 1511 | |
f6fb786d BZ |
1512 | if (hwif->sg_nents) { |
1513 | ide_destroy_dmatable(drive); | |
1da177e4 LT |
1514 | hwif->sg_nents = 0; |
1515 | } | |
1516 | } | |
1517 | ||
1da177e4 LT |
1518 | /* |
1519 | * Prepare a DMA transfer. We build the DMA table, adjust the timings for | |
1520 | * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion | |
1521 | */ | |
aacaf9bd | 1522 | static int |
1da177e4 LT |
1523 | pmac_ide_dma_setup(ide_drive_t *drive) |
1524 | { | |
1525 | ide_hwif_t *hwif = HWIF(drive); | |
1526 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
1527 | struct request *rq = HWGROUP(drive)->rq; | |
1528 | u8 unit = (drive->select.b.unit & 0x01); | |
1529 | u8 ata4; | |
1530 | ||
1531 | if (pmif == NULL) | |
1532 | return 1; | |
1533 | ata4 = (pmif->kind == controller_kl_ata4); | |
1534 | ||
1535 | if (!pmac_ide_build_dmatable(drive, rq)) { | |
1536 | ide_map_sg(drive, rq); | |
1537 | return 1; | |
1538 | } | |
1539 | ||
1540 | /* Apple adds 60ns to wrDataSetup on reads */ | |
1541 | if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { | |
1542 | writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0), | |
1543 | PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1544 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1545 | } | |
1546 | ||
1547 | drive->waiting_for_dma = 1; | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
aacaf9bd | 1552 | static void |
1da177e4 LT |
1553 | pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1554 | { | |
1555 | /* issue cmd to drive */ | |
1556 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL); | |
1557 | } | |
1558 | ||
1559 | /* | |
1560 | * Kick the DMA controller into life after the DMA command has been issued | |
1561 | * to the drive. | |
1562 | */ | |
aacaf9bd | 1563 | static void |
1da177e4 LT |
1564 | pmac_ide_dma_start(ide_drive_t *drive) |
1565 | { | |
1566 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1567 | volatile struct dbdma_regs __iomem *dma; | |
1568 | ||
1569 | dma = pmif->dma_regs; | |
1570 | ||
1571 | writel((RUN << 16) | RUN, &dma->control); | |
1572 | /* Make sure it gets to the controller right now */ | |
1573 | (void)readl(&dma->control); | |
1574 | } | |
1575 | ||
1576 | /* | |
1577 | * After a DMA transfer, make sure the controller is stopped | |
1578 | */ | |
aacaf9bd | 1579 | static int |
1da177e4 LT |
1580 | pmac_ide_dma_end (ide_drive_t *drive) |
1581 | { | |
1582 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1583 | volatile struct dbdma_regs __iomem *dma; | |
1584 | u32 dstat; | |
1585 | ||
1586 | if (pmif == NULL) | |
1587 | return 0; | |
1588 | dma = pmif->dma_regs; | |
1589 | ||
1590 | drive->waiting_for_dma = 0; | |
1591 | dstat = readl(&dma->status); | |
1592 | writel(((RUN|WAKE|DEAD) << 16), &dma->control); | |
1593 | pmac_ide_destroy_dmatable(drive); | |
1594 | /* verify good dma status. we don't check for ACTIVE beeing 0. We should... | |
1595 | * in theory, but with ATAPI decices doing buffer underruns, that would | |
1596 | * cause us to disable DMA, which isn't what we want | |
1597 | */ | |
1598 | return (dstat & (RUN|DEAD)) != RUN; | |
1599 | } | |
1600 | ||
1601 | /* | |
1602 | * Check out that the interrupt we got was for us. We can't always know this | |
1603 | * for sure with those Apple interfaces (well, we could on the recent ones but | |
1604 | * that's not implemented yet), on the other hand, we don't have shared interrupts | |
1605 | * so it's not really a problem | |
1606 | */ | |
aacaf9bd | 1607 | static int |
1da177e4 LT |
1608 | pmac_ide_dma_test_irq (ide_drive_t *drive) |
1609 | { | |
1610 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1611 | volatile struct dbdma_regs __iomem *dma; | |
1612 | unsigned long status, timeout; | |
1613 | ||
1614 | if (pmif == NULL) | |
1615 | return 0; | |
1616 | dma = pmif->dma_regs; | |
1617 | ||
1618 | /* We have to things to deal with here: | |
1619 | * | |
1620 | * - The dbdma won't stop if the command was started | |
1621 | * but completed with an error without transferring all | |
1622 | * datas. This happens when bad blocks are met during | |
1623 | * a multi-block transfer. | |
1624 | * | |
1625 | * - The dbdma fifo hasn't yet finished flushing to | |
1626 | * to system memory when the disk interrupt occurs. | |
1627 | * | |
1628 | */ | |
1629 | ||
1630 | /* If ACTIVE is cleared, the STOP command have passed and | |
1631 | * transfer is complete. | |
1632 | */ | |
1633 | status = readl(&dma->status); | |
1634 | if (!(status & ACTIVE)) | |
1635 | return 1; | |
1636 | if (!drive->waiting_for_dma) | |
1637 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1638 | called while not waiting\n", HWIF(drive)->index); | |
1639 | ||
1640 | /* If dbdma didn't execute the STOP command yet, the | |
1641 | * active bit is still set. We consider that we aren't | |
1642 | * sharing interrupts (which is hopefully the case with | |
1643 | * those controllers) and so we just try to flush the | |
1644 | * channel for pending data in the fifo | |
1645 | */ | |
1646 | udelay(1); | |
1647 | writel((FLUSH << 16) | FLUSH, &dma->control); | |
1648 | timeout = 0; | |
1649 | for (;;) { | |
1650 | udelay(1); | |
1651 | status = readl(&dma->status); | |
1652 | if ((status & FLUSH) == 0) | |
1653 | break; | |
1654 | if (++timeout > 100) { | |
1655 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1656 | timeout flushing channel\n", HWIF(drive)->index); | |
1657 | break; | |
1658 | } | |
1659 | } | |
1660 | return 1; | |
1661 | } | |
1662 | ||
15ce926a | 1663 | static void pmac_ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 1664 | { |
1da177e4 LT |
1665 | } |
1666 | ||
841d2a9b SS |
1667 | static void |
1668 | pmac_ide_dma_lost_irq (ide_drive_t *drive) | |
1da177e4 LT |
1669 | { |
1670 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1671 | volatile struct dbdma_regs __iomem *dma; | |
1672 | unsigned long status; | |
1673 | ||
1674 | if (pmif == NULL) | |
841d2a9b | 1675 | return; |
1da177e4 LT |
1676 | dma = pmif->dma_regs; |
1677 | ||
1678 | status = readl(&dma->status); | |
1679 | printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status); | |
1da177e4 LT |
1680 | } |
1681 | ||
f37afdac | 1682 | static const struct ide_dma_ops pmac_dma_ops = { |
5e37bdc0 BZ |
1683 | .dma_host_set = pmac_ide_dma_host_set, |
1684 | .dma_setup = pmac_ide_dma_setup, | |
1685 | .dma_exec_cmd = pmac_ide_dma_exec_cmd, | |
1686 | .dma_start = pmac_ide_dma_start, | |
1687 | .dma_end = pmac_ide_dma_end, | |
1688 | .dma_test_irq = pmac_ide_dma_test_irq, | |
1689 | .dma_timeout = ide_dma_timeout, | |
1690 | .dma_lost_irq = pmac_ide_dma_lost_irq, | |
1691 | }; | |
1692 | ||
1da177e4 LT |
1693 | /* |
1694 | * Allocate the data structures needed for using DMA with an interface | |
1695 | * and fill the proper list of functions pointers | |
1696 | */ | |
0d071922 BZ |
1697 | static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, |
1698 | const struct ide_port_info *d) | |
1da177e4 | 1699 | { |
0d071922 | 1700 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data; |
36501650 BZ |
1701 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1702 | ||
1da177e4 LT |
1703 | /* We won't need pci_dev if we switch to generic consistent |
1704 | * DMA routines ... | |
1705 | */ | |
0d071922 | 1706 | if (dev == NULL || pmif->dma_regs == 0) |
c413b9b9 | 1707 | return -ENODEV; |
1da177e4 LT |
1708 | /* |
1709 | * Allocate space for the DBDMA commands. | |
1710 | * The +2 is +1 for the stop command and +1 to allow for | |
1711 | * aligning the start address to a multiple of 16 bytes. | |
1712 | */ | |
1713 | pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent( | |
36501650 | 1714 | dev, |
1da177e4 LT |
1715 | (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), |
1716 | &hwif->dmatable_dma); | |
1717 | if (pmif->dma_table_cpu == NULL) { | |
1718 | printk(KERN_ERR "%s: unable to allocate DMA command list\n", | |
1719 | hwif->name); | |
c413b9b9 | 1720 | return -ENOMEM; |
1da177e4 LT |
1721 | } |
1722 | ||
4f52a329 BZ |
1723 | hwif->sg_max_nents = MAX_DCMDS; |
1724 | ||
c413b9b9 | 1725 | return 0; |
1da177e4 | 1726 | } |
0d071922 BZ |
1727 | #else |
1728 | static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, | |
1729 | const struct ide_port_info *d) | |
1730 | { | |
1731 | return -EOPNOTSUPP; | |
1732 | } | |
1da177e4 | 1733 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ |
ade2daf9 BZ |
1734 | |
1735 | module_init(pmac_ide_probe); | |
de9facbf AB |
1736 | |
1737 | MODULE_LICENSE("GPL"); |