Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/irq.h> | |
22 | ||
1da177e4 LT |
23 | /** |
24 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
25 | * @dev: PCI device of interface to switch native | |
26 | * @name: Name of interface | |
27 | * | |
28 | * We attempt to place the PCI interface into PCI native mode. If | |
29 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 30 | * Returns 0 on success or an errno code. |
1da177e4 LT |
31 | * |
32 | * FIXME: if we program the interface and then fail to set the BARS | |
33 | * we don't switch it back to legacy mode. Do we actually care ?? | |
34 | */ | |
846bb88a PC |
35 | |
36 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
37 | { |
38 | u8 progif = 0; | |
39 | ||
40 | /* | |
41 | * Place both IDE interfaces into PCI "native" mode: | |
42 | */ | |
43 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
44 | (progif & 5) != 5) { | |
45 | if ((progif & 0xa) != 0xa) { | |
46 | printk(KERN_INFO "%s: device not capable of full " | |
47 | "native PCI mode\n", name); | |
48 | return -EOPNOTSUPP; | |
49 | } | |
50 | printk("%s: placing both ports into native PCI mode\n", name); | |
51 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
52 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
53 | (progif & 5) != 5) { | |
54 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
55 | "0x%04x, got 0x%04x\n", | |
56 | name, progif|5, progif); | |
57 | return -EOPNOTSUPP; | |
58 | } | |
59 | } | |
60 | return 0; | |
61 | } | |
62 | ||
63 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
64 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
65 | { | |
66 | u8 dma_stat = inb(dma_base + 2); | |
67 | ||
68 | outb(dma_stat & 0x60, dma_base + 2); | |
69 | dma_stat = inb(dma_base + 2); | |
70 | if (dma_stat & 0x80) | |
71 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
72 | } | |
73 | ||
1da177e4 | 74 | /** |
b123f56e | 75 | * ide_pci_dma_base - setup BMIBA |
039788e1 | 76 | * @hwif: IDE interface |
b123f56e | 77 | * @d: IDE port info |
1da177e4 | 78 | * |
c58e79dd BZ |
79 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
80 | * Where a device has a partner that is already in DMA mode we check | |
81 | * and enforce IDE simplex rules. | |
1da177e4 LT |
82 | */ |
83 | ||
b123f56e | 84 | unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 85 | { |
36501650 BZ |
86 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
87 | unsigned long dma_base = 0; | |
8ac2b42a | 88 | u8 dma_stat = 0; |
1da177e4 | 89 | |
1da177e4 LT |
90 | if (hwif->mmio) |
91 | return hwif->dma_base; | |
92 | ||
93 | if (hwif->mate && hwif->mate->dma_base) { | |
94 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
95 | } else { | |
9ffcf364 BZ |
96 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
97 | ||
98 | dma_base = pci_resource_start(dev, baridx); | |
99 | ||
aea5d375 | 100 | if (dma_base == 0) { |
9ffcf364 | 101 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
102 | return 0; |
103 | } | |
1da177e4 LT |
104 | } |
105 | ||
aea5d375 BZ |
106 | if (hwif->channel) |
107 | dma_base += 8; | |
108 | ||
8ac2b42a BZ |
109 | if (d->host_flags & IDE_HFLAG_CS5520) |
110 | goto out; | |
111 | ||
112 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
113 | ide_pci_clear_simplex(dma_base, d->name); | |
114 | goto out; | |
115 | } | |
116 | ||
117 | /* | |
118 | * If the device claims "simplex" DMA, this means that only one of | |
119 | * the two interfaces can be trusted with DMA at any point in time | |
120 | * (so we should enable DMA only on one of the two interfaces). | |
121 | * | |
122 | * FIXME: At this point we haven't probed the drives so we can't make | |
123 | * the appropriate decision. Really we should defer this problem until | |
124 | * we tune the drive then try to grab DMA ownership if we want to be | |
125 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
126 | */ | |
127 | dma_stat = hwif->INB(dma_base + 2); | |
128 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
129 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
130 | dma_base = 0; | |
1da177e4 | 131 | } |
8ac2b42a | 132 | out: |
1da177e4 LT |
133 | return dma_base; |
134 | } | |
b123f56e | 135 | EXPORT_SYMBOL_GPL(ide_pci_dma_base); |
d54452fb BZ |
136 | |
137 | /* | |
138 | * Set up BM-DMA capability (PnP BIOS should have done this) | |
139 | */ | |
b123f56e | 140 | int ide_pci_set_master(struct pci_dev *dev, const char *name) |
d54452fb BZ |
141 | { |
142 | u16 pcicmd; | |
143 | ||
144 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
145 | ||
146 | if ((pcicmd & PCI_COMMAND_MASTER) == 0) { | |
147 | pci_set_master(dev); | |
148 | ||
149 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || | |
150 | (pcicmd & PCI_COMMAND_MASTER) == 0) { | |
151 | printk(KERN_ERR "%s: error updating PCICMD on %s\n", | |
152 | name, pci_name(dev)); | |
153 | return -EIO; | |
154 | } | |
155 | } | |
156 | ||
157 | return 0; | |
158 | } | |
b123f56e | 159 | EXPORT_SYMBOL_GPL(ide_pci_set_master); |
1da177e4 LT |
160 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
161 | ||
85620436 | 162 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 163 | { |
bde07e5e BZ |
164 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
165 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
166 | dev->revision, pci_name(dev)); | |
1da177e4 | 167 | } |
1da177e4 LT |
168 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
169 | ||
170 | ||
171 | /** | |
172 | * ide_pci_enable - do PCI enables | |
173 | * @dev: PCI device | |
039788e1 | 174 | * @d: IDE port info |
1da177e4 LT |
175 | * |
176 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
177 | * but if that fails then we only need IO space. The PCI code should |
178 | * have setup the proper resources for us already for controllers in | |
179 | * legacy mode. | |
846bb88a | 180 | * |
1da177e4 LT |
181 | * Returns zero on success or an error code |
182 | */ | |
039788e1 | 183 | |
85620436 | 184 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 185 | { |
0d1bad21 | 186 | int ret, bars; |
1da177e4 LT |
187 | |
188 | if (pci_enable_device(dev)) { | |
09483916 | 189 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
190 | if (ret < 0) { |
191 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
192 | "Could not enable device.\n", d->name); | |
193 | goto out; | |
194 | } | |
195 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
196 | } | |
197 | ||
198 | /* | |
039788e1 BZ |
199 | * assume all devices can do 32-bit DMA for now, we can add |
200 | * a DMA mask field to the struct ide_port_info if we need it | |
201 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
202 | */ |
203 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
204 | if (ret < 0) { | |
205 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
206 | goto out; | |
207 | } | |
208 | ||
0d1bad21 BZ |
209 | if (d->host_flags & IDE_HFLAG_SINGLE) |
210 | bars = (1 << 2) - 1; | |
211 | else | |
212 | bars = (1 << 4) - 1; | |
1da177e4 | 213 | |
0d1bad21 BZ |
214 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
215 | if (d->host_flags & IDE_HFLAG_CS5520) | |
216 | bars |= (1 << 2); | |
217 | else | |
218 | bars |= (1 << 4); | |
219 | } | |
220 | ||
221 | ret = pci_request_selected_regions(dev, bars, d->name); | |
222 | if (ret < 0) | |
223 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
224 | out: |
225 | return ret; | |
226 | } | |
227 | ||
228 | /** | |
229 | * ide_pci_configure - configure an unconfigured device | |
230 | * @dev: PCI device | |
039788e1 | 231 | * @d: IDE port info |
1da177e4 LT |
232 | * |
233 | * Enable and configure the PCI device we have been passed. | |
234 | * Returns zero on success or an error code. | |
235 | */ | |
039788e1 | 236 | |
85620436 | 237 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
238 | { |
239 | u16 pcicmd = 0; | |
240 | /* | |
241 | * PnP BIOS was *supposed* to have setup this device, but we | |
242 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
243 | * (or possibly the device is using a "legacy header" for IRQs). | |
244 | * Maybe the user deliberately *disabled* the device, | |
245 | * but we'll eventually ignore it again if no drives respond. | |
246 | */ | |
846bb88a PC |
247 | if (ide_setup_pci_baseregs(dev, d->name) || |
248 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
249 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
250 | return -ENODEV; | |
251 | } | |
252 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
253 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
254 | return -EIO; | |
255 | } | |
256 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
257 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
258 | return -ENXIO; | |
259 | } | |
260 | return 0; | |
261 | } | |
262 | ||
263 | /** | |
264 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
265 | * @dev: PCI device |
266 | * @d: IDE port info | |
267 | * @bar: BAR number | |
1da177e4 | 268 | * |
1baccff8 SS |
269 | * Checks if a BAR is configured and points to MMIO space. If so, |
270 | * return an error code. Otherwise return 0 | |
1da177e4 | 271 | */ |
039788e1 | 272 | |
1baccff8 SS |
273 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
274 | int bar) | |
1da177e4 LT |
275 | { |
276 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 277 | |
1da177e4 LT |
278 | /* Unconfigured ? */ |
279 | if (!flags || pci_resource_len(dev, bar) == 0) | |
280 | return 0; | |
281 | ||
1baccff8 SS |
282 | /* I/O space */ |
283 | if (flags & IORESOURCE_IO) | |
1da177e4 | 284 | return 0; |
846bb88a | 285 | |
1da177e4 | 286 | /* Bad */ |
1da177e4 LT |
287 | return -EINVAL; |
288 | } | |
289 | ||
290 | /** | |
291 | * ide_hwif_configure - configure an IDE interface | |
292 | * @dev: PCI device holding interface | |
039788e1 | 293 | * @d: IDE port info |
1ebf7493 BZ |
294 | * @port: port number |
295 | * @irq: PCI IRQ | |
1da177e4 LT |
296 | * |
297 | * Perform the initial set up for the hardware interface structure. This | |
298 | * is done per interface port rather than per PCI device. There may be | |
299 | * more than one port per device. | |
300 | * | |
301 | * Returns the new hardware interface structure, or NULL on a failure | |
302 | */ | |
039788e1 | 303 | |
1ebf7493 BZ |
304 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
305 | const struct ide_port_info *d, | |
306 | unsigned int port, int irq) | |
1da177e4 LT |
307 | { |
308 | unsigned long ctl = 0, base = 0; | |
309 | ide_hwif_t *hwif; | |
79127c37 | 310 | struct hw_regs_s hw; |
1da177e4 | 311 | |
a5d8c5c8 | 312 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
313 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
314 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
315 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
316 | "as MEM for port %d!\n", d->name, port); | |
317 | return NULL; | |
318 | } | |
846bb88a | 319 | |
1da177e4 LT |
320 | ctl = pci_resource_start(dev, 2*port+1); |
321 | base = pci_resource_start(dev, 2*port); | |
322 | if ((ctl && !base) || (base && !ctl)) { | |
323 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
324 | "for port %d, skipping\n", d->name, port); | |
325 | return NULL; | |
326 | } | |
327 | } | |
846bb88a | 328 | if (!ctl) { |
1da177e4 LT |
329 | /* Use default values */ |
330 | ctl = port ? 0x374 : 0x3f4; | |
331 | base = port ? 0x170 : 0x1f0; | |
332 | } | |
bad7c825 | 333 | |
fe80b937 | 334 | hwif = ide_find_port_slot(d); |
bad7c825 BZ |
335 | if (hwif == NULL) { |
336 | printk(KERN_ERR "%s: too many IDE interfaces, no room in " | |
337 | "table\n", d->name); | |
338 | return NULL; | |
339 | } | |
79127c37 BZ |
340 | |
341 | memset(&hw, 0, sizeof(hw)); | |
aab8ad9e | 342 | hw.irq = irq; |
79127c37 BZ |
343 | hw.dev = &dev->dev; |
344 | hw.chipset = d->chipset ? d->chipset : ide_pci; | |
345 | ide_std_init_ports(&hw, base, ctl | 2); | |
346 | ||
79127c37 BZ |
347 | ide_init_port_hw(hwif, &hw); |
348 | ||
36501650 | 349 | hwif->dev = &dev->dev; |
1da177e4 | 350 | |
1da177e4 LT |
351 | return hwif; |
352 | } | |
353 | ||
c413b9b9 | 354 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
355 | /** |
356 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 357 | * @hwif: IDE interface |
c413b9b9 | 358 | * @d: IDE port info |
1da177e4 LT |
359 | * |
360 | * Set up the DMA base for the interface. Enable the master bits as | |
361 | * necessary and attempt to bring the device DMA into a ready to use | |
362 | * state | |
363 | */ | |
039788e1 | 364 | |
b123f56e | 365 | int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 366 | { |
c413b9b9 | 367 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 368 | |
47b68788 | 369 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
370 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
371 | (dev->class & 0x80))) { | |
b123f56e | 372 | unsigned long base = ide_pci_dma_base(hwif, d); |
d54452fb | 373 | |
63158d5c | 374 | if (base == 0 || ide_pci_set_master(dev, d->name) < 0) |
b123f56e | 375 | return -1; |
d54452fb | 376 | |
63158d5c BZ |
377 | if (hwif->mmio) |
378 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); | |
379 | else | |
380 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", | |
381 | hwif->name, base, base + 7); | |
382 | ||
383 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
384 | ||
b123f56e BZ |
385 | if (ide_allocate_dma_engine(hwif)) |
386 | return -1; | |
d54452fb | 387 | |
f37afdac | 388 | ide_setup_dma(hwif, base); |
b123f56e | 389 | } |
d54452fb | 390 | |
b123f56e | 391 | return 0; |
039788e1 | 392 | } |
c413b9b9 | 393 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
394 | |
395 | /** | |
396 | * ide_setup_pci_controller - set up IDE PCI | |
397 | * @dev: PCI device | |
039788e1 | 398 | * @d: IDE port info |
1da177e4 LT |
399 | * @noisy: verbose flag |
400 | * @config: returned as 1 if we configured the hardware | |
401 | * | |
402 | * Set up the PCI and controller side of the IDE interface. This brings | |
403 | * up the PCI side of the device, checks that the device is enabled | |
404 | * and enables it if need be | |
405 | */ | |
039788e1 | 406 | |
85620436 | 407 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
408 | { |
409 | int ret; | |
1da177e4 LT |
410 | u16 pcicmd; |
411 | ||
412 | if (noisy) | |
413 | ide_setup_pci_noise(dev, d); | |
414 | ||
415 | ret = ide_pci_enable(dev, d); | |
416 | if (ret < 0) | |
417 | goto out; | |
418 | ||
419 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
420 | if (ret < 0) { | |
421 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
422 | goto out; | |
423 | } | |
424 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
425 | ret = ide_pci_configure(dev, d); | |
426 | if (ret < 0) | |
427 | goto out; | |
428 | *config = 1; | |
429 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
430 | } | |
431 | ||
1da177e4 LT |
432 | out: |
433 | return ret; | |
434 | } | |
435 | ||
436 | /** | |
437 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
438 | * @dev: PCI device | |
039788e1 | 439 | * @d: IDE port info |
1da177e4 | 440 | * @pciirq: IRQ line |
8447d9d5 | 441 | * @idx: ATA index table to update |
1da177e4 LT |
442 | * |
443 | * Scan the interfaces attached to this device and do any | |
444 | * necessary per port setup. Attach the devices and ask the | |
445 | * generic DMA layer to do its work for us. | |
446 | * | |
447 | * Normally called automaticall from do_ide_pci_setup_device, | |
448 | * but is also used directly as a helper function by some controllers | |
449 | * where the chipset setup is not the default PCI IDE one. | |
450 | */ | |
8447d9d5 | 451 | |
85620436 | 452 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx) |
1da177e4 | 453 | { |
a5d8c5c8 | 454 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 455 | ide_hwif_t *hwif; |
1da177e4 LT |
456 | u8 tmp; |
457 | ||
1da177e4 LT |
458 | /* |
459 | * Set up the IDE ports | |
460 | */ | |
cf6e854e | 461 | |
a5d8c5c8 | 462 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
463 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
464 | ||
1da177e4 | 465 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
466 | (tmp & e->mask) != e->val)) { |
467 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 468 | continue; /* port not enabled */ |
cf6e854e | 469 | } |
1da177e4 | 470 | |
1ebf7493 BZ |
471 | hwif = ide_hwif_configure(dev, d, port, pciirq); |
472 | if (hwif == NULL) | |
1da177e4 LT |
473 | continue; |
474 | ||
8447d9d5 | 475 | *(idx + port) = hwif->index; |
1ebf7493 | 476 | } |
1da177e4 | 477 | } |
1da177e4 LT |
478 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
479 | ||
480 | /* | |
481 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
482 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
483 | * for use with them. This generic code works for most PCI chipsets. | |
484 | * | |
485 | * One thing that is not standardized is the location of the | |
486 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 487 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
488 | * for all other chipsets, we just assume both interfaces are enabled. |
489 | */ | |
039788e1 | 490 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 491 | const struct ide_port_info *d, |
8447d9d5 | 492 | u8 *idx, u8 noisy) |
1da177e4 | 493 | { |
1da177e4 LT |
494 | int tried_config = 0; |
495 | int pciirq, ret; | |
496 | ||
497 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
498 | if (ret < 0) | |
499 | goto out; | |
500 | ||
501 | /* | |
502 | * Can we trust the reported IRQ? | |
503 | */ | |
504 | pciirq = dev->irq; | |
505 | ||
506 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
507 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
508 | if (noisy) | |
509 | printk(KERN_INFO "%s: not 100%% native mode: " | |
510 | "will probe irqs later\n", d->name); | |
511 | /* | |
512 | * This allows offboard ide-pci cards the enable a BIOS, | |
513 | * verify interrupt settings of split-mirror pci-config | |
514 | * space, place chipset into init-mode, and/or preserve | |
515 | * an interrupt if the card is not native ide support. | |
516 | */ | |
517 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
518 | if (ret < 0) | |
519 | goto out; | |
520 | pciirq = ret; | |
521 | } else if (tried_config) { | |
522 | if (noisy) | |
523 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
524 | pciirq = 0; | |
525 | } else if (!pciirq) { | |
526 | if (noisy) | |
527 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
528 | d->name, pciirq); | |
529 | pciirq = 0; | |
530 | } else { | |
531 | if (d->init_chipset) { | |
532 | ret = d->init_chipset(dev, d->name); | |
533 | if (ret < 0) | |
534 | goto out; | |
535 | } | |
536 | if (noisy) | |
1da177e4 LT |
537 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
538 | d->name, pciirq); | |
1da177e4 LT |
539 | } |
540 | ||
541 | /* FIXME: silent failure can happen */ | |
542 | ||
8447d9d5 | 543 | ide_pci_setup_ports(dev, d, pciirq, idx); |
1da177e4 LT |
544 | out: |
545 | return ret; | |
546 | } | |
547 | ||
85620436 | 548 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 549 | { |
8447d9d5 | 550 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
551 | int ret; |
552 | ||
8447d9d5 | 553 | ret = do_ide_setup_pci_device(dev, d, &idx[0], 1); |
1da177e4 | 554 | |
8447d9d5 | 555 | if (ret >= 0) |
c413b9b9 | 556 | ide_device_add(idx, d); |
1da177e4 | 557 | |
1da177e4 LT |
558 | return ret; |
559 | } | |
1da177e4 LT |
560 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
561 | ||
562 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 563 | const struct ide_port_info *d) |
1da177e4 LT |
564 | { |
565 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 566 | int ret, i; |
8447d9d5 | 567 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
568 | |
569 | for (i = 0; i < 2; i++) { | |
8447d9d5 | 570 | ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i); |
1da177e4 LT |
571 | /* |
572 | * FIXME: Mom, mom, they stole me the helper function to undo | |
573 | * do_ide_setup_pci_device() on the first device! | |
574 | */ | |
575 | if (ret < 0) | |
576 | goto out; | |
577 | } | |
578 | ||
c413b9b9 | 579 | ide_device_add(idx, d); |
1da177e4 LT |
580 | out: |
581 | return ret; | |
582 | } | |
1da177e4 | 583 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |