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ide: set hwif->expiry prior to calling [__]ide_set_handler()
[deliverable/linux.git] / drivers / ide / tx4939ide.c
CommitLineData
37897989
AN		 1/*
2 * TX4939 internal IDE driver
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2005-2007
10 */
11
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/ide.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/scatterlist.h>
20
15a453a9
BZ		 21#include <asm/ide.h>
22
37897989
AN		 23#define MODNAME "tx4939ide"
24
25/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
26#define TX4939IDE_Data 0x000
27#define TX4939IDE_Error_Feature 0x001
28#define TX4939IDE_Sec 0x002
29#define TX4939IDE_LBA0 0x003
30#define TX4939IDE_LBA1 0x004
31#define TX4939IDE_LBA2 0x005
32#define TX4939IDE_DevHead 0x006
33#define TX4939IDE_Stat_Cmd 0x007
34#define TX4939IDE_AltStat_DevCtl 0x402
35/* H/W DMA Registers */
36#define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
37#define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
38#define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
39/* ATA100 CORE Registers (16-bit) */
40#define TX4939IDE_Sys_Ctl 0xc00
41#define TX4939IDE_Xfer_Cnt_1 0xc08
42#define TX4939IDE_Xfer_Cnt_2 0xc0a
43#define TX4939IDE_Sec_Cnt 0xc10
44#define TX4939IDE_Start_Lo_Addr 0xc18
45#define TX4939IDE_Start_Up_Addr 0xc20
46#define TX4939IDE_Add_Ctl 0xc28
47#define TX4939IDE_Lo_Burst_Cnt 0xc30
48#define TX4939IDE_Up_Burst_Cnt 0xc38
49#define TX4939IDE_PIO_Addr 0xc88
50#define TX4939IDE_H_Rst_Tim 0xc90
51#define TX4939IDE_Int_Ctl 0xc98
52#define TX4939IDE_Pkt_Cmd 0xcb8
53#define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
54#define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
55#define TX4939IDE_Dev_TErr 0xcd0
56#define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
57#define TX4939IDE_Start_TAddr 0xce0
58
59/* bits for Int_Ctl */
60#define TX4939IDE_INT_ADDRERR 0x80
61#define TX4939IDE_INT_REACHMUL 0x40
62#define TX4939IDE_INT_DEVTIMING 0x20
63#define TX4939IDE_INT_UDMATERM 0x10
64#define TX4939IDE_INT_TIMER 0x08
65#define TX4939IDE_INT_BUSERR 0x04
66#define TX4939IDE_INT_XFEREND 0x02
67#define TX4939IDE_INT_HOST 0x01
68
69#define TX4939IDE_IGNORE_INTS \
70 (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
71 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
72 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
73
74#ifdef __BIG_ENDIAN
75#define tx4939ide_swizzlel(a) ((a) ^ 4)
76#define tx4939ide_swizzlew(a) ((a) ^ 6)
77#define tx4939ide_swizzleb(a) ((a) ^ 7)
78#else
79#define tx4939ide_swizzlel(a) (a)
80#define tx4939ide_swizzlew(a) (a)
81#define tx4939ide_swizzleb(a) (a)
82#endif
83
84static u16 tx4939ide_readw(void __iomem *base, u32 reg)
85{
86 return __raw_readw(base + tx4939ide_swizzlew(reg));
87}
88static u8 tx4939ide_readb(void __iomem *base, u32 reg)
89{
90 return __raw_readb(base + tx4939ide_swizzleb(reg));
91}
92static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
93{
94 __raw_writel(val, base + tx4939ide_swizzlel(reg));
95}
96static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
97{
98 __raw_writew(val, base + tx4939ide_swizzlew(reg));
99}
100static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
101{
102 __raw_writeb(val, base + tx4939ide_swizzleb(reg));
103}
104
105#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106
107static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
108{
109 ide_hwif_t *hwif = drive->hwif;
110 int is_slave = drive->dn;
111 u32 mask, val;
112 u8 safe = pio;
113 ide_drive_t *pair;
114
115 pair = ide_get_pair_dev(drive);
116 if (pair)
117 safe = min(safe, ide_get_best_pio_mode(pair, 255, 4));
118 /*
119 * Update Command Transfer Mode for master/slave and Data
120 * Transfer Mode for this drive.
121 */
122 mask = is_slave ? 0x07f00000 : 0x000007f0;
123 val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
124 hwif->select_data = (hwif->select_data & ~mask) | val;
125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126}
127
128static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
129{
130 ide_hwif_t *hwif = drive->hwif;
131 u32 mask, val;
132
133 /* Update Data Transfer Mode for this drive. */
134 if (mode >= XFER_UDMA_0)
135 val = mode - XFER_UDMA_0 + 8;
136 else
137 val = mode - XFER_MW_DMA_0 + 5;
138 if (drive->dn) {
139 mask = 0x00f00000;
140 val <<= 20;
141 } else {
142 mask = 0x000000f0;
143 val <<= 4;
144 }
145 hwif->select_data = (hwif->select_data & ~mask) | val;
146 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
147}
148
149static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
150{
151 void __iomem *base = TX4939IDE_BASE(hwif);
152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
153
154 if (ctl & TX4939IDE_INT_BUSERR) {
155 /* reset FIFO */
156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
157
158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
159 mmiowb();
160 /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
161 ndelay(270);
162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
163 }
164 if (ctl & (TX4939IDE_INT_ADDRERR |
165 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
166 pr_err("%s: Error interrupt %#x (%s%s%s )\n",
167 hwif->name, ctl,
168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
171 return ctl;
172}
173
174static void tx4939ide_clear_irq(ide_drive_t *drive)
175{
176 ide_hwif_t *hwif;
177 void __iomem *base;
178 u16 ctl;
179
180 /*
181 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
182 * for DMA case.
183 */
184 if (drive->waiting_for_dma)
185 return;
186 hwif = drive->hwif;
187 base = TX4939IDE_BASE(hwif);
188 ctl = tx4939ide_check_error_ints(hwif);
189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
190}
191
192static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
193{
194 void __iomem *base = TX4939IDE_BASE(hwif);
195
196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
197 ATA_CBL_PATA40 : ATA_CBL_PATA80;
198}
199
200#ifdef __BIG_ENDIAN
201static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
202{
203 ide_hwif_t *hwif = drive->hwif;
204 u8 unit = drive->dn;
205 void __iomem *base = TX4939IDE_BASE(hwif);
206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
207
208 if (on)
209 dma_stat |= (1 << (5 + unit));
210 else
211 dma_stat &= ~(1 << (5 + unit));
212
213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
214}
215#else
216#define tx4939ide_dma_host_set ide_dma_host_set
217#endif
218
219static u8 tx4939ide_clear_dma_status(void __iomem *base)
220{
221 u8 dma_stat;
222
223 /* read DMA status for INTR & ERROR flags */
224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
225 /* clear INTR & ERROR flags */
226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
227 TX4939IDE_DMA_Stat);
228 /* recover intmask cleared by writing to bit2 of DMA_Stat */
229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
230 return dma_stat;
231}
232
233#ifdef __BIG_ENDIAN
234/* custom ide_build_dmatable to handle swapped layout */
22981694 235static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
37897989
AN		 236{
237 ide_hwif_t *hwif = drive->hwif;
238 u32 *table = (u32 *)hwif->dmatable_cpu;
239 unsigned int count = 0;
240 int i;
241 struct scatterlist *sg;
242
22981694 243 for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
37897989
AN		 244 u32 cur_addr, cur_len, bcount;
245
246 cur_addr = sg_dma_address(sg);
247 cur_len = sg_dma_len(sg);
248
249 /*
250 * Fill in the DMA table, without crossing any 64kB boundaries.
251 */
252
253 while (cur_len) {
254 if (count++ >= PRD_ENTRIES)
255 goto use_pio_instead;
256
257 bcount = 0x10000 - (cur_addr & 0xffff);
258 if (bcount > cur_len)
259 bcount = cur_len;
a0fce792
AN		 260 /*
261 * This workaround for zero count seems required.
9711a537 262 * (standard ide_build_dmatable does it too)
a0fce792 263 */
9711a537 264 if (bcount == 0x10000)
a0fce792 265 bcount = 0x8000;
37897989
AN		 266 *table++ = bcount & 0xffff;
267 *table++ = cur_addr;
268 cur_addr += bcount;
269 cur_len -= bcount;
270 }
271 }
272
273 if (count) {
274 *(table - 2) |= 0x80000000;
275 return count;
276 }
277
278use_pio_instead:
279 printk(KERN_ERR "%s: %s\n", drive->name,
280 count ? "DMA table too small" : "empty DMA table?");
281
282 ide_destroy_dmatable(drive);
283
284 return 0; /* revert to PIO for this request */
285}
286#else
287#define tx4939ide_build_dmatable ide_build_dmatable
288#endif
289
22981694 290static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
37897989
AN		 291{
292 ide_hwif_t *hwif = drive->hwif;
293 void __iomem *base = TX4939IDE_BASE(hwif);
22981694 294 u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
37897989
AN		 295
296 /* fall back to PIO! */
22981694
BZ		 297 if (tx4939ide_build_dmatable(drive, cmd) == 0) {
298 ide_map_sg(drive, cmd);
37897989
AN		 299 return 1;
300 }
301
302 /* PRD table */
303 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
304
305 /* specify r/w */
22981694 306 tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
37897989
AN		 307
308 /* clear INTR & ERROR flags */
309 tx4939ide_clear_dma_status(base);
310
311 drive->waiting_for_dma = 1;
312
313 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
314 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
22981694
BZ		 315
316 tx4939ide_writew(cmd->rq->nr_sectors, base, TX4939IDE_Sec_Cnt);
317
37897989
AN		 318 return 0;
319}
320
321static int tx4939ide_dma_end(ide_drive_t *drive)
322{
323 ide_hwif_t *hwif = drive->hwif;
324 u8 dma_stat, dma_cmd;
325 void __iomem *base = TX4939IDE_BASE(hwif);
326 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
327
328 drive->waiting_for_dma = 0;
329
330 /* get DMA command mode */
331 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
332 /* stop DMA */
333 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
334
335 /* read and clear the INTR & ERROR bits */
336 dma_stat = tx4939ide_clear_dma_status(base);
337
338 /* purge DMA mappings */
339 ide_destroy_dmatable(drive);
340 /* verify good DMA status */
341 wmb();
342
343 if ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) == 0 &&
344 (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
345 (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
346 /* INT_IDE lost... bug? */
347 return 0;
348 return ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) !=
349 ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
350}
351
352/* returns 1 if DMA IRQ issued, 0 otherwise */
353static int tx4939ide_dma_test_irq(ide_drive_t *drive)
354{
355 ide_hwif_t *hwif = drive->hwif;
356 void __iomem *base = TX4939IDE_BASE(hwif);
357 u16 ctl, ide_int;
358 u8 dma_stat, stat;
359 int found = 0;
360
361 ctl = tx4939ide_check_error_ints(hwif);
362 ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
363 switch (ide_int) {
364 case TX4939IDE_INT_HOST:
365 /* On error, XFEREND might not be asserted. */
366 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
367 if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
368 found = 1;
369 else
370 /* Wait for XFEREND (Mask HOST and unmask XFEREND) */
371 ctl &= ~TX4939IDE_INT_XFEREND << 8;
372 ctl |= ide_int << 8;
373 break;
374 case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
375 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
376 if (!(dma_stat & ATA_DMA_INTR))
377 pr_warning("%s: weird interrupt status. "
378 "DMA_Stat %#02x int_ctl %#04x\n",
379 hwif->name, dma_stat, ctl);
380 found = 1;
381 break;
382 }
383 /*
384 * Do not clear XFEREND, HOST now. They will be cleared by
385 * clearing bit2 of DMA_Stat.
386 */
387 ctl &= ~ide_int;
388 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
389 return found;
390}
391
592b5315
SS		 392#ifdef __BIG_ENDIAN
393static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
394{
395 void __iomem *base = TX4939IDE_BASE(hwif);
396
397 return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
398}
399#else
400#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
401#endif
402
37897989
AN		 403static void tx4939ide_init_hwif(ide_hwif_t *hwif)
404{
405 void __iomem *base = TX4939IDE_BASE(hwif);
406
407 /* Soft Reset */
408 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
409 mmiowb();
410 /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
411 ndelay(450);
412 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
413 /* mask some interrupts and clear all interrupts */
414 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
415 TX4939IDE_Int_Ctl);
416
417 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
418 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
419}
420
421static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
422{
423 hwif->dma_base =
424 hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
425 /*
426 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
427 * for big endian.
428 */
429 return ide_allocate_dma_engine(hwif);
430}
431
22aa4b32 432static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
37897989
AN		 433{
434 ide_hwif_t *hwif = drive->hwif;
435 void __iomem *base = TX4939IDE_BASE(hwif);
436 u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
437
438 /*
439 * Fix ATA100 CORE System Control Register. (The write to the
440 * Device/Head register may write wrong data to the System
441 * Control Register)
442 * While Sys_Ctl is written here, selectproc is not needed.
443 */
444 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
445}
446
447#ifdef __BIG_ENDIAN
448
37897989
AN		 449/* custom iops (independent from SWAP_IO_SPACE) */
450static u8 tx4939ide_inb(unsigned long port)
451{
452 return __raw_readb((void __iomem *)port);
453}
454
455static void tx4939ide_outb(u8 value, unsigned long port)
456{
457 __raw_writeb(value, (void __iomem *)port);
458}
459
22aa4b32 460static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
37897989
AN		 461{
462 ide_hwif_t *hwif = drive->hwif;
463 struct ide_io_ports *io_ports = &hwif->io_ports;
22aa4b32
BZ		 464 struct ide_taskfile *tf = &cmd->tf;
465 u8 HIHI = cmd->tf_flags & IDE_TFLAG_LBA48 ? 0xE0 : 0xEF;
37897989 466
22aa4b32 467 if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED)
37897989
AN		 468 HIHI = 0xFF;
469
22aa4b32 470 if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA) {
37897989
AN		 471 u16 data = (tf->hob_data << 8) | tf->data;
472
473 /* no endian swap */
474 __raw_writew(data, (void __iomem *)io_ports->data_addr);
475 }
476
22aa4b32 477 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
37897989 478 tx4939ide_outb(tf->hob_feature, io_ports->feature_addr);
22aa4b32 479 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
37897989 480 tx4939ide_outb(tf->hob_nsect, io_ports->nsect_addr);
22aa4b32 481 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
37897989 482 tx4939ide_outb(tf->hob_lbal, io_ports->lbal_addr);
22aa4b32 483 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
37897989 484 tx4939ide_outb(tf->hob_lbam, io_ports->lbam_addr);
22aa4b32 485 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
37897989
AN		 486 tx4939ide_outb(tf->hob_lbah, io_ports->lbah_addr);
487
22aa4b32 488 if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE)
37897989 489 tx4939ide_outb(tf->feature, io_ports->feature_addr);
22aa4b32 490 if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT)
37897989 491 tx4939ide_outb(tf->nsect, io_ports->nsect_addr);
22aa4b32 492 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL)
37897989 493 tx4939ide_outb(tf->lbal, io_ports->lbal_addr);
22aa4b32 494 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM)
37897989 495 tx4939ide_outb(tf->lbam, io_ports->lbam_addr);
22aa4b32 496 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH)
37897989
AN		 497 tx4939ide_outb(tf->lbah, io_ports->lbah_addr);
498
22aa4b32 499 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) {
37897989
AN		 500 tx4939ide_outb((tf->device & HIHI) | drive->select,
501 io_ports->device_addr);
22aa4b32 502 tx4939ide_tf_load_fixup(drive);
37897989
AN		 503 }
504}
505
22aa4b32 506static void tx4939ide_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
37897989
AN		 507{
508 ide_hwif_t *hwif = drive->hwif;
509 struct ide_io_ports *io_ports = &hwif->io_ports;
22aa4b32 510 struct ide_taskfile *tf = &cmd->tf;
37897989 511
22aa4b32 512 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
37897989
AN		 513 u16 data;
514
515 /* no endian swap */
516 data = __raw_readw((void __iomem *)io_ports->data_addr);
517 tf->data = data & 0xff;
518 tf->hob_data = (data >> 8) & 0xff;
519 }
520
521 /* be sure we're looking at the low order bits */
522 tx4939ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
523
22aa4b32 524 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
37897989 525 tf->feature = tx4939ide_inb(io_ports->feature_addr);
22aa4b32 526 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
37897989 527 tf->nsect = tx4939ide_inb(io_ports->nsect_addr);
22aa4b32 528 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
37897989 529 tf->lbal = tx4939ide_inb(io_ports->lbal_addr);
22aa4b32 530 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
37897989 531 tf->lbam = tx4939ide_inb(io_ports->lbam_addr);
22aa4b32 532 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
37897989 533 tf->lbah = tx4939ide_inb(io_ports->lbah_addr);
22aa4b32 534 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
37897989
AN		 535 tf->device = tx4939ide_inb(io_ports->device_addr);
536
22aa4b32 537 if (cmd->tf_flags & IDE_TFLAG_LBA48) {
37897989
AN		 538 tx4939ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
539
22aa4b32 540 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
37897989
AN		 541 tf->hob_feature =
542 tx4939ide_inb(io_ports->feature_addr);
22aa4b32 543 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
37897989 544 tf->hob_nsect = tx4939ide_inb(io_ports->nsect_addr);
22aa4b32 545 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
37897989 546 tf->hob_lbal = tx4939ide_inb(io_ports->lbal_addr);
22aa4b32 547 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
37897989 548 tf->hob_lbam = tx4939ide_inb(io_ports->lbam_addr);
22aa4b32 549 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
37897989
AN		 550 tf->hob_lbah = tx4939ide_inb(io_ports->lbah_addr);
551 }
552}
553
554static void tx4939ide_input_data_swap(ide_drive_t *drive, struct request *rq,
555 void *buf, unsigned int len)
556{
557 unsigned long port = drive->hwif->io_ports.data_addr;
558 unsigned short *ptr = buf;
559 unsigned int count = (len + 1) / 2;
560
561 while (count--)
562 *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
f26f6cea 563 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
37897989
AN		 564}
565
566static void tx4939ide_output_data_swap(ide_drive_t *drive, struct request *rq,
567 void *buf, unsigned int len)
568{
569 unsigned long port = drive->hwif->io_ports.data_addr;
570 unsigned short *ptr = buf;
571 unsigned int count = (len + 1) / 2;
572
573 while (count--) {
574 __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
575 ptr++;
576 }
f26f6cea 577 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
37897989
AN		 578}
579
580static const struct ide_tp_ops tx4939ide_tp_ops = {
581 .exec_command = ide_exec_command,
582 .read_status = ide_read_status,
583 .read_altstatus = ide_read_altstatus,
37897989
AN		 584
585 .set_irq = ide_set_irq,
586
587 .tf_load = tx4939ide_tf_load,
588 .tf_read = tx4939ide_tf_read,
589
590 .input_data = tx4939ide_input_data_swap,
591 .output_data = tx4939ide_output_data_swap,
592};
593
594#else /* __LITTLE_ENDIAN */
595
22aa4b32 596static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
37897989 597{
22aa4b32
BZ		 598 ide_tf_load(drive, cmd);
599
600 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE)
601 tx4939ide_tf_load_fixup(drive);
37897989
AN		 602}
603
604static const struct ide_tp_ops tx4939ide_tp_ops = {
605 .exec_command = ide_exec_command,
606 .read_status = ide_read_status,
607 .read_altstatus = ide_read_altstatus,
37897989
AN		 608
609 .set_irq = ide_set_irq,
610
611 .tf_load = tx4939ide_tf_load,
612 .tf_read = ide_tf_read,
613
614 .input_data = ide_input_data,
615 .output_data = ide_output_data,
616};
617
618#endif /* __LITTLE_ENDIAN */
619
620static const struct ide_port_ops tx4939ide_port_ops = {
3ee86dcd
BZ		 621 .set_pio_mode = tx4939ide_set_pio_mode,
622 .set_dma_mode = tx4939ide_set_dma_mode,
623 .clear_irq = tx4939ide_clear_irq,
624 .cable_detect = tx4939ide_cable_detect,
37897989
AN		 625};
626
627static const struct ide_dma_ops tx4939ide_dma_ops = {
3ee86dcd
BZ		 628 .dma_host_set = tx4939ide_dma_host_set,
629 .dma_setup = tx4939ide_dma_setup,
630 .dma_exec_cmd = ide_dma_exec_cmd,
631 .dma_start = ide_dma_start,
632 .dma_end = tx4939ide_dma_end,
633 .dma_test_irq = tx4939ide_dma_test_irq,
634 .dma_lost_irq = ide_dma_lost_irq,
635 .dma_timeout = ide_dma_timeout,
592b5315 636 .dma_sff_read_status = tx4939ide_dma_sff_read_status,
37897989
AN		 637};
638
639static const struct ide_port_info tx4939ide_port_info __initdata = {
3ee86dcd
BZ		 640 .init_hwif = tx4939ide_init_hwif,
641 .init_dma = tx4939ide_init_dma,
642 .port_ops = &tx4939ide_port_ops,
643 .dma_ops = &tx4939ide_dma_ops,
644 .tp_ops = &tx4939ide_tp_ops,
645 .host_flags = IDE_HFLAG_MMIO,
646 .pio_mask = ATA_PIO4,
647 .mwdma_mask = ATA_MWDMA2,
648 .udma_mask = ATA_UDMA5,
b1d249e8 649 .chipset = ide_generic,
37897989
AN		 650};
651
652static int __init tx4939ide_probe(struct platform_device *pdev)
653{
654 hw_regs_t hw;
655 hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
656 struct ide_host *host;
657 struct resource *res;
658 int irq, ret;
659 unsigned long mapbase;
660
661 irq = platform_get_irq(pdev, 0);
662 if (irq < 0)
663 return -ENODEV;
664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
665 if (!res)
666 return -ENODEV;
667
668 if (!devm_request_mem_region(&pdev->dev, res->start,
669 res->end - res->start + 1, "tx4938ide"))
670 return -EBUSY;
671 mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
672 res->end - res->start + 1);
673 if (!mapbase)
674 return -EBUSY;
675 memset(&hw, 0, sizeof(hw));
676 hw.io_ports.data_addr =
677 mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
678 hw.io_ports.error_addr =
679 mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
680 hw.io_ports.nsect_addr =
681 mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
682 hw.io_ports.lbal_addr =
683 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
684 hw.io_ports.lbam_addr =
685 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
686 hw.io_ports.lbah_addr =
687 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
688 hw.io_ports.device_addr =
689 mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
690 hw.io_ports.command_addr =
691 mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
692 hw.io_ports.ctl_addr =
693 mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
694 hw.irq = irq;
695 hw.dev = &pdev->dev;
696
697 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
698 host = ide_host_alloc(&tx4939ide_port_info, hws);
699 if (!host)
700 return -ENOMEM;
701 /* use extra_base for base address of the all registers */
702 host->ports[0]->extra_base = mapbase;
703 ret = ide_host_register(host, &tx4939ide_port_info, hws);
704 if (ret) {
705 ide_host_free(host);
706 return ret;
707 }
708 platform_set_drvdata(pdev, host);
709 return 0;
710}
711
712static int __exit tx4939ide_remove(struct platform_device *pdev)
713{
714 struct ide_host *host = platform_get_drvdata(pdev);
715
716 ide_host_remove(host);
717 return 0;
718}
719
720#ifdef CONFIG_PM
721static int tx4939ide_resume(struct platform_device *dev)
722{
723 struct ide_host *host = platform_get_drvdata(dev);
724 ide_hwif_t *hwif = host->ports[0];
725
726 tx4939ide_init_hwif(hwif);
727 return 0;
728}
729#else
730#define tx4939ide_resume NULL
731#endif
732
733static struct platform_driver tx4939ide_driver = {
734 .driver = {
735 .name = MODNAME,
736 .owner = THIS_MODULE,
737 },
738 .remove = __exit_p(tx4939ide_remove),
739 .resume = tx4939ide_resume,
740};
741
742static int __init tx4939ide_init(void)
743{
744 return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
745}
746
747static void __exit tx4939ide_exit(void)
748{
749 platform_driver_unregister(&tx4939ide_driver);
750}
751
752module_init(tx4939ide_init);
753module_exit(tx4939ide_exit);
754
755MODULE_DESCRIPTION("TX4939 internal IDE driver");
756MODULE_LICENSE("GPL");
757MODULE_ALIAS("platform:tx4939ide");
Linux kernel - Deliverables
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