[deliverable/linux.git] / drivers / idle / intel_idle.c

/*
 * intel_idle.c - native hardware idle loop for modern Intel processors
 *
 * Copyright (c) 2010, Intel Corporation.
 * Len Brown <len.brown@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

/*
 * intel_idle is a cpuidle driver that loads on specific Intel processors
 * in lieu of the legacy ACPI processor_idle driver.  The intent is to
 * make Linux more efficient on these processors, as intel_idle knows
 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
 */

/*
 * Design Assumptions
 *
 * All CPUs have same idle states as boot CPU
 *
 * Chipset BM_STS (bus master status) bit is a NOP
 *	for preventing entry into deep C-stats
 */

/*
 * Known limitations
 *
 * The driver currently initializes for_each_online_cpu() upon modprobe.
 * It it unaware of subsequent processors hot-added to the system.
 * This means that if you boot with maxcpus=n and later online
 * processors above n, those processors will use C1 only.
 *
 * ACPI has a .suspend hack to turn off deep c-statees during suspend
 * to avoid complications with the lapic timer workaround.
 * Have not seen issues with suspend, but may need same workaround here.
 *
 * There is currently no kernel-based automatic probing/loading mechanism
 * if the driver is built as a module.
 */

/* un-comment DEBUG to enable pr_debug() statements */
#define DEBUG

#include <linux/kernel.h>
#include <linux/cpuidle.h>
#include <linux/clockchips.h>
#include <linux/hrtimer.h>	/* ktime_get_real() */
#include <trace/events/power.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <asm/cpu_device_id.h>
#include <asm/mwait.h>
#include <asm/msr.h>

#define INTEL_IDLE_VERSION "0.4"
#define PREFIX "intel_idle: "

static struct cpuidle_driver intel_idle_driver = {
	.name = "intel_idle",
	.owner = THIS_MODULE,
};
/* intel_idle.max_cstate=0 disables driver */
static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;

static unsigned int mwait_substates;

#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
/* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
static unsigned int lapic_timer_reliable_states = (1 << 1);	 /* Default to only C1 */

struct idle_cpu {
	struct cpuidle_state *state_table;

	/*
	 * Hardware C-state auto-demotion may not always be optimal.
	 * Indicate which enable bits to clear here.
	 */
	unsigned long auto_demotion_disable_flags;
};

static const struct idle_cpu *icpu;
static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
static int intel_idle(struct cpuidle_device *dev,
			struct cpuidle_driver *drv, int index);
static int intel_idle_cpu_init(int cpu);

static struct cpuidle_state *cpuidle_state_table;

/*
 * Set this flag for states where the HW flushes the TLB for us
 * and so we don't need cross-calls to keep it consistent.
 * If this flag is set, SW flushes the TLB, so even if the
 * HW doesn't do the flushing, this flag is safe to use.
 */
#define CPUIDLE_FLAG_TLB_FLUSHED	0x10000

/*
 * States are indexed by the cstate number,
 * which is also the index into the MWAIT hint array.
 * Thus C0 is a dummy.
 */
static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-NHM",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 3,
		.target_residency = 6,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-NHM",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-NHM",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 200,
		.target_residency = 800,
		.enter = &intel_idle },
};

static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-SNB",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 1,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-SNB",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 80,
		.target_residency = 211,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-SNB",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 104,
		.target_residency = 345,
		.enter = &intel_idle },
	{ /* MWAIT C4 */
		.name = "C7-SNB",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 109,
		.target_residency = 345,
		.enter = &intel_idle },
};

static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-IVB",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 1,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-IVB",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 59,
		.target_residency = 156,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-IVB",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 80,
		.target_residency = 300,
		.enter = &intel_idle },
	{ /* MWAIT C4 */
		.name = "C7-IVB",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 87,
		.target_residency = 300,
		.enter = &intel_idle },
};

static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-ATM",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 4,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C2-ATM",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */ },
	{ /* MWAIT C4 */
		.name = "C4-ATM",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 100,
		.target_residency = 400,
		.enter = &intel_idle },
	{ /* MWAIT C5 */ },
	{ /* MWAIT C6 */
		.name = "C6-ATM",
		.desc = "MWAIT 0x52",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 140,
		.target_residency = 560,
		.enter = &intel_idle },
};

static long get_driver_data(int cstate)
{
	int driver_data;
	switch (cstate) {

	case 1:	/* MWAIT C1 */
		driver_data = 0x00;
		break;
	case 2:	/* MWAIT C2 */
		driver_data = 0x10;
		break;
	case 3:	/* MWAIT C3 */
		driver_data = 0x20;
		break;
	case 4:	/* MWAIT C4 */
		driver_data = 0x30;
		break;
	case 5:	/* MWAIT C5 */
		driver_data = 0x40;
		break;
	case 6:	/* MWAIT C6 */
		driver_data = 0x52;
		break;
	default:
		driver_data = 0x00;
	}
	return driver_data;
}

/**
 * intel_idle
 * @dev: cpuidle_device
 * @drv: cpuidle driver
 * @index: index of cpuidle state
 *
 * Must be called under local_irq_disable().
 */
static int intel_idle(struct cpuidle_device *dev,
		struct cpuidle_driver *drv, int index)
{
	unsigned long ecx = 1; /* break on interrupt flag */
	struct cpuidle_state *state = &drv->states[index];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
	unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
	unsigned int cstate;
	ktime_t kt_before, kt_after;
	s64 usec_delta;
	int cpu = smp_processor_id();

	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;

	/*
	 * leave_mm() to avoid costly and often unnecessary wakeups
	 * for flushing the user TLB's associated with the active mm.
	 */
	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
		leave_mm(cpu);

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

	kt_before = ktime_get_real();

	stop_critical_timings();
	if (!need_resched()) {

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(eax, ecx);
	}

	start_critical_timings();

	kt_after = ktime_get_real();
	usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));

	local_irq_enable();

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);

	/* Update cpuidle counters */
	dev->last_residency = (int)usec_delta;

	return index;
}

static void __setup_broadcast_timer(void *arg)
{
	unsigned long reason = (unsigned long)arg;
	int cpu = smp_processor_id();

	reason = reason ?
		CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;

	clockevents_notify(reason, &cpu);
}

static int cpu_hotplug_notify(struct notifier_block *n,
			      unsigned long action, void *hcpu)
{
	int hotcpu = (unsigned long)hcpu;
	struct cpuidle_device *dev;

	switch (action & 0xf) {
	case CPU_ONLINE:

		if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
			smp_call_function_single(hotcpu, __setup_broadcast_timer,
						 (void *)true, 1);

		/*
		 * Some systems can hotplug a cpu at runtime after
		 * the kernel has booted, we have to initialize the
		 * driver in this case
		 */
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
		if (!dev->registered)
			intel_idle_cpu_init(hotcpu);

		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block cpu_hotplug_notifier = {
	.notifier_call = cpu_hotplug_notify,
};

static void auto_demotion_disable(void *dummy)
{
	unsigned long long msr_bits;

	rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
	msr_bits &= ~(icpu->auto_demotion_disable_flags);
	wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
}

static const struct idle_cpu idle_cpu_nehalem = {
	.state_table = nehalem_cstates,
	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
};

static const struct idle_cpu idle_cpu_atom = {
	.state_table = atom_cstates,
};

static const struct idle_cpu idle_cpu_lincroft = {
	.state_table = atom_cstates,
	.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
};

static const struct idle_cpu idle_cpu_snb = {
	.state_table = snb_cstates,
};

static const struct idle_cpu idle_cpu_ivb = {
	.state_table = ivb_cstates,
};

#define ICPU(model, cpu) \
	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }

static const struct x86_cpu_id intel_idle_ids[] = {
	ICPU(0x1a, idle_cpu_nehalem),
	ICPU(0x1e, idle_cpu_nehalem),
	ICPU(0x1f, idle_cpu_nehalem),
	ICPU(0x25, idle_cpu_nehalem),
	ICPU(0x2c, idle_cpu_nehalem),
	ICPU(0x2e, idle_cpu_nehalem),
	ICPU(0x1c, idle_cpu_atom),
	ICPU(0x26, idle_cpu_lincroft),
	ICPU(0x2f, idle_cpu_nehalem),
	ICPU(0x2a, idle_cpu_snb),
	ICPU(0x2d, idle_cpu_snb),
	ICPU(0x3a, idle_cpu_ivb),
	ICPU(0x3e, idle_cpu_ivb),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);

/*
 * intel_idle_probe()
 */
static int intel_idle_probe(void)
{
	unsigned int eax, ebx, ecx;
	const struct x86_cpu_id *id;

	if (max_cstate == 0) {
		pr_debug(PREFIX "disabled\n");
		return -EPERM;
	}

	id = x86_match_cpu(intel_idle_ids);
	if (!id) {
		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
		    boot_cpu_data.x86 == 6)
			pr_debug(PREFIX "does not run on family %d model %d\n",
				boot_cpu_data.x86, boot_cpu_data.x86_model);
		return -ENODEV;
	}

	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
		return -ENODEV;

	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);

	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
	    !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
	    !mwait_substates)
			return -ENODEV;

	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);

	icpu = (const struct idle_cpu *)id->driver_data;
	cpuidle_state_table = icpu->state_table;

	if (boot_cpu_has(X86_FEATURE_ARAT))	/* Always Reliable APIC Timer */
		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
	else
		on_each_cpu(__setup_broadcast_timer, (void *)true, 1);

	register_cpu_notifier(&cpu_hotplug_notifier);

	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
		" model 0x%X\n", boot_cpu_data.x86_model);

	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
		lapic_timer_reliable_states);
	return 0;
}

/*
 * intel_idle_cpuidle_devices_uninit()
 * unregister, free cpuidle_devices
 */
static void intel_idle_cpuidle_devices_uninit(void)
{
	int i;
	struct cpuidle_device *dev;

	for_each_online_cpu(i) {
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
		cpuidle_unregister_device(dev);
	}

	free_percpu(intel_idle_cpuidle_devices);
	return;
}
/*
 * intel_idle_cpuidle_driver_init()
 * allocate, initialize cpuidle_states
 */
static int intel_idle_cpuidle_driver_init(void)
{
	int cstate;
	struct cpuidle_driver *drv = &intel_idle_driver;

	drv->state_count = 1;

	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
		int num_substates;

		if (cstate > max_cstate) {
			printk(PREFIX "max_cstate %d reached\n",
				max_cstate);
			break;
		}

		/* does the state exist in CPUID.MWAIT? */
		num_substates = (mwait_substates >> ((cstate) * 4))
					& MWAIT_SUBSTATE_MASK;
		if (num_substates == 0)
			continue;
		/* is the state not enabled? */
		if (cpuidle_state_table[cstate].enter == NULL) {
			/* does the driver not know about the state? */
			if (*cpuidle_state_table[cstate].name == '\0')
				pr_debug(PREFIX "unaware of model 0x%x"
					" MWAIT %d please"
					" contact lenb@kernel.org",
				boot_cpu_data.x86_model, cstate);
			continue;
		}

		if ((cstate > 2) &&
			!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
			mark_tsc_unstable("TSC halts in idle"
					" states deeper than C2");

		drv->states[drv->state_count] =	/* structure copy */
			cpuidle_state_table[cstate];

		drv->state_count += 1;
	}

	if (icpu->auto_demotion_disable_flags)
		on_each_cpu(auto_demotion_disable, NULL, 1);

	return 0;
}


/*
 * intel_idle_cpu_init()
 * allocate, initialize, register cpuidle_devices
 * @cpu: cpu/core to initialize
 */
static int intel_idle_cpu_init(int cpu)
{
	int cstate;
	struct cpuidle_device *dev;

	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);

	dev->state_count = 1;

	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
		int num_substates;

		if (cstate > max_cstate) {
			printk(PREFIX "max_cstate %d reached\n", max_cstate);
			break;
		}

		/* does the state exist in CPUID.MWAIT? */
		num_substates = (mwait_substates >> ((cstate) * 4))
			& MWAIT_SUBSTATE_MASK;
		if (num_substates == 0)
			continue;
		/* is the state not enabled? */
		if (cpuidle_state_table[cstate].enter == NULL)
			continue;

		dev->states_usage[dev->state_count].driver_data =
			(void *)get_driver_data(cstate);

		dev->state_count += 1;
	}

	dev->cpu = cpu;

	if (cpuidle_register_device(dev)) {
		pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
		intel_idle_cpuidle_devices_uninit();
		return -EIO;
	}

	if (icpu->auto_demotion_disable_flags)
		smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);

	return 0;
}

static int __init intel_idle_init(void)
{
	int retval, i;

	/* Do not load intel_idle at all for now if idle= is passed */
	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
		return -ENODEV;

	retval = intel_idle_probe();
	if (retval)
		return retval;

	intel_idle_cpuidle_driver_init();
	retval = cpuidle_register_driver(&intel_idle_driver);
	if (retval) {
		struct cpuidle_driver *drv = cpuidle_get_driver();
		printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
			drv ? drv->name : "none");
		return retval;
	}

	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	if (intel_idle_cpuidle_devices == NULL)
		return -ENOMEM;

	for_each_online_cpu(i) {
		retval = intel_idle_cpu_init(i);
		if (retval) {
			cpuidle_unregister_driver(&intel_idle_driver);
			return retval;
		}
	}

	return 0;
}

static void __exit intel_idle_exit(void)
{
	intel_idle_cpuidle_devices_uninit();
	cpuidle_unregister_driver(&intel_idle_driver);


	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
		on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
	unregister_cpu_notifier(&cpu_hotplug_notifier);

	return;
}

module_init(intel_idle_init);
module_exit(intel_idle_exit);

module_param(max_cstate, int, 0444);

MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
MODULE_LICENSE("GPL");
Commit	Line	Data
26717172 LB	1	/*
	2	* intel_idle.c - native hardware idle loop for modern Intel processors
	3	*
	4	* Copyright (c) 2010, Intel Corporation.
	5	* Len Brown <len.brown@intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	/*
	22	* intel_idle is a cpuidle driver that loads on specific Intel processors
	23	* in lieu of the legacy ACPI processor_idle driver. The intent is to
	24	* make Linux more efficient on these processors, as intel_idle knows
	25	* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
	26	*/
	27
	28	/*
	29	* Design Assumptions
	30	*
	31	* All CPUs have same idle states as boot CPU
	32	*
	33	* Chipset BM_STS (bus master status) bit is a NOP
	34	* for preventing entry into deep C-stats
	35	*/
	36
	37	/*
	38	* Known limitations
	39	*
	40	* The driver currently initializes for_each_online_cpu() upon modprobe.
	41	* It it unaware of subsequent processors hot-added to the system.
	42	* This means that if you boot with maxcpus=n and later online
	43	* processors above n, those processors will use C1 only.
	44	*
	45	* ACPI has a .suspend hack to turn off deep c-statees during suspend
	46	* to avoid complications with the lapic timer workaround.
	47	* Have not seen issues with suspend, but may need same workaround here.
	48	*
	49	* There is currently no kernel-based automatic probing/loading mechanism
	50	* if the driver is built as a module.
	51	*/
	52
	53	/* un-comment DEBUG to enable pr_debug() statements */
	54	#define DEBUG
	55
	56	#include <linux/kernel.h>
	57	#include <linux/cpuidle.h>
	58	#include <linux/clockchips.h>
	59	#include <linux/hrtimer.h> /* ktime_get_real() */
	60	#include <trace/events/power.h>
	61	#include <linux/sched.h>
2a2d31c8 SL	62	#include <linux/notifier.h>
2a2d31c8 SL	63	#include <linux/cpu.h>
7c52d551	64	#include <linux/module.h>
b66b8b9a	65	#include <asm/cpu_device_id.h>
bc83cccc	66	#include <asm/mwait.h>
14796fca	67	#include <asm/msr.h>
26717172 LB	68
	69	#define INTEL_IDLE_VERSION "0.4"
	70	#define PREFIX "intel_idle: "
	71
26717172 LB	72	static struct cpuidle_driver intel_idle_driver = {
	73	.name = "intel_idle",
	74	.owner = THIS_MODULE,
	75	};
	76	/* intel_idle.max_cstate=0 disables driver */
	77	static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
26717172	78
c4236282	79	static unsigned int mwait_substates;
26717172	80
2a2d31c8	81	#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
26717172	82	/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
d13780d4	83	static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
26717172	84
b66b8b9a AK	85	struct idle_cpu {
	86	struct cpuidle_state *state_table;
	87
	88	/*
	89	* Hardware C-state auto-demotion may not always be optimal.
	90	* Indicate which enable bits to clear here.
	91	*/
	92	unsigned long auto_demotion_disable_flags;
	93	};
	94
	95	static const struct idle_cpu *icpu;
3265eba0	96	static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
46bcfad7 DD	97	static int intel_idle(struct cpuidle_device *dev,
46bcfad7 DD	98	struct cpuidle_driver *drv, int index);
25ac7761	99	static int intel_idle_cpu_init(int cpu);
26717172 LB	100
	101	static struct cpuidle_state *cpuidle_state_table;
	102
956d033f LB	103	/*
	104	* Set this flag for states where the HW flushes the TLB for us
	105	* and so we don't need cross-calls to keep it consistent.
	106	* If this flag is set, SW flushes the TLB, so even if the
	107	* HW doesn't do the flushing, this flag is safe to use.
	108	*/
	109	#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
	110
26717172 LB	111	/*
	112	* States are indexed by the cstate number,
	113	* which is also the index into the MWAIT hint array.
	114	* Thus C0 is a dummy.
	115	*/
	116	static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	117	{ /* MWAIT C0 */ },
	118	{ /* MWAIT C1 */
15e123e5	119	.name = "C1-NHM",
26717172	120	.desc = "MWAIT 0x00",
26717172 LB	121	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	122	.exit_latency = 3,
26717172 LB	123	.target_residency = 6,
	124	.enter = &intel_idle },
	125	{ /* MWAIT C2 */
15e123e5	126	.name = "C3-NHM",
26717172	127	.desc = "MWAIT 0x10",
6110a1f4	128	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	129	.exit_latency = 20,
26717172 LB	130	.target_residency = 80,
	131	.enter = &intel_idle },
	132	{ /* MWAIT C3 */
15e123e5	133	.name = "C6-NHM",
26717172	134	.desc = "MWAIT 0x20",
6110a1f4	135	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	136	.exit_latency = 200,
26717172 LB	137	.target_residency = 800,
	138	.enter = &intel_idle },
	139	};
	140
d13780d4 LB	141	static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	142	{ /* MWAIT C0 */ },
	143	{ /* MWAIT C1 */
15e123e5	144	.name = "C1-SNB",
d13780d4	145	.desc = "MWAIT 0x00",
d13780d4 LB	146	.flags = CPUIDLE_FLAG_TIME_VALID,
d13780d4 LB	147	.exit_latency = 1,
ddbd550d	148	.target_residency = 1,
d13780d4 LB	149	.enter = &intel_idle },
d13780d4 LB	150	{ /* MWAIT C2 */
15e123e5	151	.name = "C3-SNB",
d13780d4	152	.desc = "MWAIT 0x10",
00527cc6	153	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	154	.exit_latency = 80,
ddbd550d	155	.target_residency = 211,
d13780d4 LB	156	.enter = &intel_idle },
d13780d4 LB	157	{ /* MWAIT C3 */
15e123e5	158	.name = "C6-SNB",
d13780d4	159	.desc = "MWAIT 0x20",
00527cc6	160	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	161	.exit_latency = 104,
ddbd550d	162	.target_residency = 345,
d13780d4 LB	163	.enter = &intel_idle },
d13780d4 LB	164	{ /* MWAIT C4 */
15e123e5	165	.name = "C7-SNB",
d13780d4	166	.desc = "MWAIT 0x30",
00527cc6	167	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	168	.exit_latency = 109,
ddbd550d	169	.target_residency = 345,
d13780d4 LB	170	.enter = &intel_idle },
	171	};
	172
6edab08c LB	173	static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	174	{ /* MWAIT C0 */ },
	175	{ /* MWAIT C1 */
	176	.name = "C1-IVB",
	177	.desc = "MWAIT 0x00",
	178	.flags = CPUIDLE_FLAG_TIME_VALID,
	179	.exit_latency = 1,
	180	.target_residency = 1,
	181	.enter = &intel_idle },
	182	{ /* MWAIT C2 */
	183	.name = "C3-IVB",
	184	.desc = "MWAIT 0x10",
	185	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	186	.exit_latency = 59,
	187	.target_residency = 156,
	188	.enter = &intel_idle },
	189	{ /* MWAIT C3 */
	190	.name = "C6-IVB",
	191	.desc = "MWAIT 0x20",
	192	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	193	.exit_latency = 80,
	194	.target_residency = 300,
	195	.enter = &intel_idle },
	196	{ /* MWAIT C4 */
	197	.name = "C7-IVB",
	198	.desc = "MWAIT 0x30",
	199	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	200	.exit_latency = 87,
	201	.target_residency = 300,
	202	.enter = &intel_idle },
	203	};
	204
26717172 LB	205	static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	206	{ /* MWAIT C0 */ },
	207	{ /* MWAIT C1 */
15e123e5	208	.name = "C1-ATM",
26717172	209	.desc = "MWAIT 0x00",
26717172 LB	210	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	211	.exit_latency = 1,
26717172 LB	212	.target_residency = 4,
	213	.enter = &intel_idle },
	214	{ /* MWAIT C2 */
15e123e5	215	.name = "C2-ATM",
26717172	216	.desc = "MWAIT 0x10",
26717172 LB	217	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	218	.exit_latency = 20,
26717172 LB	219	.target_residency = 80,
	220	.enter = &intel_idle },
	221	{ /* MWAIT C3 */ },
	222	{ /* MWAIT C4 */
15e123e5	223	.name = "C4-ATM",
26717172	224	.desc = "MWAIT 0x30",
6110a1f4	225	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	226	.exit_latency = 100,
26717172 LB	227	.target_residency = 400,
	228	.enter = &intel_idle },
	229	{ /* MWAIT C5 */ },
	230	{ /* MWAIT C6 */
15e123e5	231	.name = "C6-ATM",
7fcca7d9	232	.desc = "MWAIT 0x52",
6110a1f4	233	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
7fcca7d9	234	.exit_latency = 140,
7fcca7d9 LB	235	.target_residency = 560,
7fcca7d9 LB	236	.enter = &intel_idle },
26717172 LB	237	};
26717172 LB	238
95e3ec11	239	static long get_driver_data(int cstate)
4202735e DD	240	{
	241	int driver_data;
	242	switch (cstate) {
	243
	244	case 1: /* MWAIT C1 */
	245	driver_data = 0x00;
	246	break;
	247	case 2: /* MWAIT C2 */
	248	driver_data = 0x10;
	249	break;
	250	case 3: /* MWAIT C3 */
	251	driver_data = 0x20;
	252	break;
	253	case 4: /* MWAIT C4 */
	254	driver_data = 0x30;
	255	break;
	256	case 5: /* MWAIT C5 */
	257	driver_data = 0x40;
	258	break;
	259	case 6: /* MWAIT C6 */
	260	driver_data = 0x52;
	261	break;
	262	default:
	263	driver_data = 0x00;
	264	}
	265	return driver_data;
	266	}
	267
26717172 LB	268	/**
	269	* intel_idle
	270	* @dev: cpuidle_device
46bcfad7	271	* @drv: cpuidle driver
e978aa7d	272	* @index: index of cpuidle state
26717172	273	*
63ff07be	274	* Must be called under local_irq_disable().
26717172	275	*/
46bcfad7 DD	276	static int intel_idle(struct cpuidle_device *dev,
46bcfad7 DD	277	struct cpuidle_driver *drv, int index)
26717172 LB	278	{
26717172 LB	279	unsigned long ecx = 1; /* break on interrupt flag */
46bcfad7	280	struct cpuidle_state *state = &drv->states[index];
4202735e DD	281	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
4202735e DD	282	unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
26717172 LB	283	unsigned int cstate;
	284	ktime_t kt_before, kt_after;
	285	s64 usec_delta;
	286	int cpu = smp_processor_id();
	287
	288	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
	289
6110a1f4	290	/*
c8381cc3 LB	291	* leave_mm() to avoid costly and often unnecessary wakeups
c8381cc3 LB	292	* for flushing the user TLB's associated with the active mm.
6110a1f4	293	*/
c8381cc3	294	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
6110a1f4 SS	295	leave_mm(cpu);
6110a1f4 SS	296
26717172 LB	297	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	298	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
	299
	300	kt_before = ktime_get_real();
	301
	302	stop_critical_timings();
26717172 LB	303	if (!need_resched()) {
	304
	305	__monitor((void *)&current_thread_info()->flags, 0, 0);
	306	smp_mb();
	307	if (!need_resched())
	308	__mwait(eax, ecx);
	309	}
	310
	311	start_critical_timings();
	312
	313	kt_after = ktime_get_real();
	314	usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
	315
	316	local_irq_enable();
	317
	318	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	319	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	320
e978aa7d DD	321	/* Update cpuidle counters */
	322	dev->last_residency = (int)usec_delta;
	323
	324	return index;
26717172 LB	325	}
26717172 LB	326
2a2d31c8 SL	327	static void __setup_broadcast_timer(void *arg)
	328	{
	329	unsigned long reason = (unsigned long)arg;
	330	int cpu = smp_processor_id();
	331
	332	reason = reason ?
	333	CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
	334
	335	clockevents_notify(reason, &cpu);
	336	}
	337
25ac7761 DL	338	static int cpu_hotplug_notify(struct notifier_block *n,
25ac7761 DL	339	unsigned long action, void *hcpu)
2a2d31c8 SL	340	{
2a2d31c8 SL	341	int hotcpu = (unsigned long)hcpu;
25ac7761	342	struct cpuidle_device *dev;
2a2d31c8 SL	343
	344	switch (action & 0xf) {
	345	case CPU_ONLINE:
25ac7761 DL	346
	347	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
	348	smp_call_function_single(hotcpu, __setup_broadcast_timer,
	349	(void *)true, 1);
	350
	351	/*
	352	* Some systems can hotplug a cpu at runtime after
	353	* the kernel has booted, we have to initialize the
	354	* driver in this case
	355	*/
	356	dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
	357	if (!dev->registered)
	358	intel_idle_cpu_init(hotcpu);
	359
2a2d31c8	360	break;
2a2d31c8 SL	361	}
	362	return NOTIFY_OK;
	363	}
	364
25ac7761 DL	365	static struct notifier_block cpu_hotplug_notifier = {
25ac7761 DL	366	.notifier_call = cpu_hotplug_notify,
2a2d31c8 SL	367	};
2a2d31c8 SL	368
14796fca LB	369	static void auto_demotion_disable(void *dummy)
	370	{
	371	unsigned long long msr_bits;
	372
	373	rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
b66b8b9a	374	msr_bits &= ~(icpu->auto_demotion_disable_flags);
14796fca LB	375	wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
	376	}
	377
b66b8b9a AK	378	static const struct idle_cpu idle_cpu_nehalem = {
b66b8b9a AK	379	.state_table = nehalem_cstates,
b66b8b9a AK	380	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE \| NHM_C3_AUTO_DEMOTE,
	381	};
	382
	383	static const struct idle_cpu idle_cpu_atom = {
	384	.state_table = atom_cstates,
	385	};
	386
	387	static const struct idle_cpu idle_cpu_lincroft = {
	388	.state_table = atom_cstates,
	389	.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
	390	};
	391
	392	static const struct idle_cpu idle_cpu_snb = {
	393	.state_table = snb_cstates,
	394	};
	395
6edab08c LB	396	static const struct idle_cpu idle_cpu_ivb = {
	397	.state_table = ivb_cstates,
	398	};
	399
b66b8b9a AK	400	#define ICPU(model, cpu) \
	401	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
	402
	403	static const struct x86_cpu_id intel_idle_ids[] = {
	404	ICPU(0x1a, idle_cpu_nehalem),
	405	ICPU(0x1e, idle_cpu_nehalem),
	406	ICPU(0x1f, idle_cpu_nehalem),
8bf11938 BH	407	ICPU(0x25, idle_cpu_nehalem),
	408	ICPU(0x2c, idle_cpu_nehalem),
	409	ICPU(0x2e, idle_cpu_nehalem),
b66b8b9a AK	410	ICPU(0x1c, idle_cpu_atom),
b66b8b9a AK	411	ICPU(0x26, idle_cpu_lincroft),
8bf11938	412	ICPU(0x2f, idle_cpu_nehalem),
b66b8b9a AK	413	ICPU(0x2a, idle_cpu_snb),
b66b8b9a AK	414	ICPU(0x2d, idle_cpu_snb),
6edab08c	415	ICPU(0x3a, idle_cpu_ivb),
23795e58	416	ICPU(0x3e, idle_cpu_ivb),
b66b8b9a AK	417	{}
	418	};
	419	MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
	420
26717172 LB	421	/*
	422	* intel_idle_probe()
	423	*/
	424	static int intel_idle_probe(void)
	425	{
c4236282	426	unsigned int eax, ebx, ecx;
b66b8b9a	427	const struct x86_cpu_id *id;
26717172 LB	428
	429	if (max_cstate == 0) {
	430	pr_debug(PREFIX "disabled\n");
	431	return -EPERM;
	432	}
	433
b66b8b9a AK	434	id = x86_match_cpu(intel_idle_ids);
	435	if (!id) {
	436	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	437	boot_cpu_data.x86 == 6)
	438	pr_debug(PREFIX "does not run on family %d model %d\n",
	439	boot_cpu_data.x86, boot_cpu_data.x86_model);
26717172	440	return -ENODEV;
b66b8b9a	441	}
26717172 LB	442
	443	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
	444	return -ENODEV;
	445
c4236282	446	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
26717172 LB	447
26717172 LB	448	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) \|\|
5c2a9f06 TR	449	!(ecx & CPUID5_ECX_INTERRUPT_BREAK) \|\|
5c2a9f06 TR	450	!mwait_substates)
26717172	451	return -ENODEV;
26717172	452
c4236282	453	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
26717172	454
b66b8b9a AK	455	icpu = (const struct idle_cpu *)id->driver_data;
b66b8b9a AK	456	cpuidle_state_table = icpu->state_table;
26717172	457
56b9aea3	458	if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
2a2d31c8	459	lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
25ac7761	460	else
39a74fde	461	on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
25ac7761 DL	462
25ac7761 DL	463	register_cpu_notifier(&cpu_hotplug_notifier);
56b9aea3	464
26717172 LB	465	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
	466	" model 0x%X\n", boot_cpu_data.x86_model);
	467
	468	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
	469	lapic_timer_reliable_states);
	470	return 0;
	471	}
	472
	473	/*
	474	* intel_idle_cpuidle_devices_uninit()
	475	* unregister, free cpuidle_devices
	476	*/
	477	static void intel_idle_cpuidle_devices_uninit(void)
	478	{
	479	int i;
	480	struct cpuidle_device *dev;
	481
	482	for_each_online_cpu(i) {
	483	dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
	484	cpuidle_unregister_device(dev);
	485	}
	486
	487	free_percpu(intel_idle_cpuidle_devices);
	488	return;
	489	}
46bcfad7 DD	490	/*
	491	* intel_idle_cpuidle_driver_init()
	492	* allocate, initialize cpuidle_states
	493	*/
	494	static int intel_idle_cpuidle_driver_init(void)
	495	{
	496	int cstate;
	497	struct cpuidle_driver *drv = &intel_idle_driver;
	498
	499	drv->state_count = 1;
	500
	501	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
	502	int num_substates;
	503
	504	if (cstate > max_cstate) {
	505	printk(PREFIX "max_cstate %d reached\n",
	506	max_cstate);
	507	break;
	508	}
	509
	510	/* does the state exist in CPUID.MWAIT? */
	511	num_substates = (mwait_substates >> ((cstate) * 4))
	512	& MWAIT_SUBSTATE_MASK;
	513	if (num_substates == 0)
	514	continue;
	515	/* is the state not enabled? */
	516	if (cpuidle_state_table[cstate].enter == NULL) {
	517	/* does the driver not know about the state? */
	518	if (*cpuidle_state_table[cstate].name == '\0')
	519	pr_debug(PREFIX "unaware of model 0x%x"
	520	" MWAIT %d please"
	521	" contact lenb@kernel.org",
	522	boot_cpu_data.x86_model, cstate);
	523	continue;
	524	}
	525
	526	if ((cstate > 2) &&
	527	!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
	528	mark_tsc_unstable("TSC halts in idle"
	529	" states deeper than C2");
	530
	531	drv->states[drv->state_count] = /* structure copy */
	532	cpuidle_state_table[cstate];
	533
	534	drv->state_count += 1;
	535	}
	536
b66b8b9a	537	if (icpu->auto_demotion_disable_flags)
39a74fde	538	on_each_cpu(auto_demotion_disable, NULL, 1);
46bcfad7 DD	539
	540	return 0;
	541	}
	542
	543
26717172	544	/*
65b7f839	545	* intel_idle_cpu_init()
26717172	546	* allocate, initialize, register cpuidle_devices
65b7f839	547	* @cpu: cpu/core to initialize
26717172	548	*/
25ac7761	549	static int intel_idle_cpu_init(int cpu)
26717172	550	{
65b7f839	551	int cstate;
26717172 LB	552	struct cpuidle_device *dev;
26717172 LB	553
65b7f839	554	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
26717172	555
65b7f839	556	dev->state_count = 1;
26717172	557
65b7f839 TR	558	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
65b7f839 TR	559	int num_substates;
26717172	560
65b7f839	561	if (cstate > max_cstate) {
dc716e96	562	printk(PREFIX "max_cstate %d reached\n", max_cstate);
65b7f839 TR	563	break;
65b7f839 TR	564	}
26717172	565
65b7f839 TR	566	/* does the state exist in CPUID.MWAIT? */
	567	num_substates = (mwait_substates >> ((cstate) * 4))
	568	& MWAIT_SUBSTATE_MASK;
	569	if (num_substates == 0)
	570	continue;
	571	/* is the state not enabled? */
	572	if (cpuidle_state_table[cstate].enter == NULL)
	573	continue;
26717172	574
65b7f839 TR	575	dev->states_usage[dev->state_count].driver_data =
65b7f839 TR	576	(void *)get_driver_data(cstate);
26717172	577
dc716e96 MPS	578	dev->state_count += 1;
	579	}
	580
65b7f839	581	dev->cpu = cpu;
26717172	582
65b7f839 TR	583	if (cpuidle_register_device(dev)) {
	584	pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
	585	intel_idle_cpuidle_devices_uninit();
	586	return -EIO;
26717172 LB	587	}
26717172 LB	588
b66b8b9a	589	if (icpu->auto_demotion_disable_flags)
65b7f839 TR	590	smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
65b7f839 TR	591
26717172 LB	592	return 0;
26717172 LB	593	}
26717172 LB	594
	595	static int __init intel_idle_init(void)
	596	{
65b7f839	597	int retval, i;
26717172	598
d1896049 TR	599	/* Do not load intel_idle at all for now if idle= is passed */
	600	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
	601	return -ENODEV;
	602
26717172 LB	603	retval = intel_idle_probe();
	604	if (retval)
	605	return retval;
	606
46bcfad7	607	intel_idle_cpuidle_driver_init();
26717172 LB	608	retval = cpuidle_register_driver(&intel_idle_driver);
26717172 LB	609	if (retval) {
3735d524	610	struct cpuidle_driver *drv = cpuidle_get_driver();
26717172	611	printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
3735d524	612	drv ? drv->name : "none");
26717172 LB	613	return retval;
	614	}
	615
65b7f839 TR	616	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	617	if (intel_idle_cpuidle_devices == NULL)
	618	return -ENOMEM;
	619
	620	for_each_online_cpu(i) {
	621	retval = intel_idle_cpu_init(i);
	622	if (retval) {
	623	cpuidle_unregister_driver(&intel_idle_driver);
	624	return retval;
	625	}
26717172 LB	626	}
	627
	628	return 0;
	629	}
	630
	631	static void __exit intel_idle_exit(void)
	632	{
	633	intel_idle_cpuidle_devices_uninit();
	634	cpuidle_unregister_driver(&intel_idle_driver);
	635
25ac7761 DL	636
25ac7761 DL	637	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
39a74fde	638	on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
25ac7761	639	unregister_cpu_notifier(&cpu_hotplug_notifier);
2a2d31c8	640
26717172 LB	641	return;
	642	}
	643
	644	module_init(intel_idle_init);
	645	module_exit(intel_idle_exit);
	646
26717172	647	module_param(max_cstate, int, 0444);
26717172 LB	648
	649	MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
	650	MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
	651	MODULE_LICENSE("GPL");