[deliverable/linux.git] / drivers / iio / adc / ad7298.c

/*
 * AD7298 SPI ADC driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include <linux/platform_data/ad7298.h>

#define AD7298_WRITE	BIT(15) /* write to the control register */
#define AD7298_REPEAT	BIT(14) /* repeated conversion enable */
#define AD7298_CH(x)	BIT(13 - (x)) /* channel select */
#define AD7298_TSENSE	BIT(5) /* temperature conversion enable */
#define AD7298_EXTREF	BIT(2) /* external reference enable */
#define AD7298_TAVG	BIT(1) /* temperature sensor averaging enable */
#define AD7298_PDD	BIT(0) /* partial power down enable */

#define AD7298_MAX_CHAN		8
#define AD7298_INTREF_mV	2500

#define AD7298_CH_TEMP		9

struct ad7298_state {
	struct spi_device		*spi;
	struct regulator		*reg;
	unsigned			ext_ref;
	struct spi_transfer		ring_xfer[10];
	struct spi_transfer		scan_single_xfer[3];
	struct spi_message		ring_msg;
	struct spi_message		scan_single_msg;
	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	__be16				rx_buf[12] ____cacheline_aligned;
	__be16				tx_buf[2];
};

#define AD7298_V_CHAN(index)						\
	{								\
		.type = IIO_VOLTAGE,					\
		.indexed = 1,						\
		.channel = index,					\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
		.address = index,					\
		.scan_index = index,					\
		.scan_type = {						\
			.sign = 'u',					\
			.realbits = 12,					\
			.storagebits = 16,				\
			.endianness = IIO_BE,				\
		},							\
	}

static const struct iio_chan_spec ad7298_channels[] = {
	{
		.type = IIO_TEMP,
		.indexed = 1,
		.channel = 0,
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			BIT(IIO_CHAN_INFO_SCALE) |
			BIT(IIO_CHAN_INFO_OFFSET),
		.address = AD7298_CH_TEMP,
		.scan_index = -1,
		.scan_type = {
			.sign = 's',
			.realbits = 32,
			.storagebits = 32,
		},
	},
	AD7298_V_CHAN(0),
	AD7298_V_CHAN(1),
	AD7298_V_CHAN(2),
	AD7298_V_CHAN(3),
	AD7298_V_CHAN(4),
	AD7298_V_CHAN(5),
	AD7298_V_CHAN(6),
	AD7298_V_CHAN(7),
	IIO_CHAN_SOFT_TIMESTAMP(8),
};

/**
 * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
 **/
static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	const unsigned long *active_scan_mask)
{
	struct ad7298_state *st = iio_priv(indio_dev);
	int i, m;
	unsigned short command;
	int scan_count;

	/* Now compute overall size */
	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);

	command = AD7298_WRITE | st->ext_ref;

	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
		if (test_bit(i, active_scan_mask))
			command |= m;

	st->tx_buf[0] = cpu_to_be16(command);

	/* build spi ring message */
	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	st->ring_xfer[0].len = 2;
	st->ring_xfer[0].cs_change = 1;
	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	st->ring_xfer[1].len = 2;
	st->ring_xfer[1].cs_change = 1;

	spi_message_init(&st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);

	for (i = 0; i < scan_count; i++) {
		st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
		st->ring_xfer[i + 2].len = 2;
		st->ring_xfer[i + 2].cs_change = 1;
		spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	}
	/* make sure last transfer cs_change is not set */
	st->ring_xfer[i + 1].cs_change = 0;

	return 0;
}

/**
 * ad7298_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 **/
static irqreturn_t ad7298_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7298_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, &st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
		iio_get_time_ns(indio_dev));

done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
{
	int ret;
	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
				   (AD7298_CH(0) >> ch));

	ret = spi_sync(st->spi, &st->scan_single_msg);
	if (ret)
		return ret;

	return be16_to_cpu(st->rx_buf[0]);
}

static int ad7298_scan_temp(struct ad7298_state *st, int *val)
{
	int ret;
	__be16 buf;

	buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
			  AD7298_TAVG | st->ext_ref);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	buf = cpu_to_be16(0);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	usleep_range(101, 1000); /* sleep > 100us */

	ret = spi_read(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	*val = sign_extend32(be16_to_cpu(buf), 11);

	return 0;
}

static int ad7298_get_ref_voltage(struct ad7298_state *st)
{
	int vref;

	if (st->ext_ref) {
		vref = regulator_get_voltage(st->reg);
		if (vref < 0)
			return vref;

		return vref / 1000;
	} else {
		return AD7298_INTREF_mV;
	}
}

static int ad7298_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7298_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;

		if (chan->address == AD7298_CH_TEMP)
			ret = ad7298_scan_temp(st, val);
		else
			ret = ad7298_scan_direct(st, chan->address);

		iio_device_release_direct_mode(indio_dev);

		if (ret < 0)
			return ret;

		if (chan->address != AD7298_CH_TEMP)
			*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);

		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		switch (chan->type) {
		case IIO_VOLTAGE:
			*val = ad7298_get_ref_voltage(st);
			*val2 = chan->scan_type.realbits;
			return IIO_VAL_FRACTIONAL_LOG2;
		case IIO_TEMP:
			*val = ad7298_get_ref_voltage(st);
			*val2 = 10;
			return IIO_VAL_FRACTIONAL;
		default:
			return -EINVAL;
		}
	case IIO_CHAN_INFO_OFFSET:
		*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
		return IIO_VAL_INT;
	}
	return -EINVAL;
}

static const struct iio_info ad7298_info = {
	.read_raw = &ad7298_read_raw,
	.update_scan_mode = ad7298_update_scan_mode,
	.driver_module = THIS_MODULE,
};

static int ad7298_probe(struct spi_device *spi)
{
	struct ad7298_platform_data *pdata = spi->dev.platform_data;
	struct ad7298_state *st;
	struct iio_dev *indio_dev;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (pdata && pdata->ext_ref)
		st->ext_ref = AD7298_EXTREF;

	if (st->ext_ref) {
		st->reg = devm_regulator_get(&spi->dev, "vref");
		if (IS_ERR(st->reg))
			return PTR_ERR(st->reg);

		ret = regulator_enable(st->reg);
		if (ret)
			return ret;
	}

	spi_set_drvdata(spi, indio_dev);

	st->spi = spi;

	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->dev.parent = &spi->dev;
	indio_dev->dev.of_node = spi->dev.of_node;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = ad7298_channels;
	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
	indio_dev->info = &ad7298_info;

	/* Setup default message */

	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	st->scan_single_xfer[0].len = 2;
	st->scan_single_xfer[0].cs_change = 1;
	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	st->scan_single_xfer[1].len = 2;
	st->scan_single_xfer[1].cs_change = 1;
	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	st->scan_single_xfer[2].len = 2;

	spi_message_init(&st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
			&ad7298_trigger_handler, NULL);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_cleanup_ring;

	return 0;

error_cleanup_ring:
	iio_triggered_buffer_cleanup(indio_dev);
error_disable_reg:
	if (st->ext_ref)
		regulator_disable(st->reg);

	return ret;
}

static int ad7298_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7298_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	if (st->ext_ref)
		regulator_disable(st->reg);

	return 0;
}

static const struct spi_device_id ad7298_id[] = {
	{"ad7298", 0},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7298_id);

static struct spi_driver ad7298_driver = {
	.driver = {
		.name	= "ad7298",
	},
	.probe		= ad7298_probe,
	.remove		= ad7298_remove,
	.id_table	= ad7298_id,
};
module_spi_driver(ad7298_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7c31b984 MH	1	/*
	2	* AD7298 SPI ADC driver
	3	*
	4	* Copyright 2011 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2.
	7	*/
	8
7c31b984 MH	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/sysfs.h>
	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
	16	#include <linux/delay.h>
99c97852	17	#include <linux/module.h>
dc4871ad	18	#include <linux/interrupt.h>
48898053	19	#include <linux/bitops.h>
7c31b984	20
06458e27 JC	21	#include <linux/iio/iio.h>
	22	#include <linux/iio/sysfs.h>
	23	#include <linux/iio/buffer.h>
dc4871ad LPC	24	#include <linux/iio/trigger_consumer.h>
dc4871ad LPC	25	#include <linux/iio/triggered_buffer.h>
7c31b984	26
709ab36e	27	#include <linux/platform_data/ad7298.h>
7c31b984	28
48898053 PM	29	#define AD7298_WRITE BIT(15) /* write to the control register */
	30	#define AD7298_REPEAT BIT(14) /* repeated conversion enable */
	31	#define AD7298_CH(x) BIT(13 - (x)) /* channel select */
	32	#define AD7298_TSENSE BIT(5) /* temperature conversion enable */
	33	#define AD7298_EXTREF BIT(2) /* external reference enable */
	34	#define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
	35	#define AD7298_PDD BIT(0) /* partial power down enable */
dc4871ad LPC	36
dc4871ad LPC	37	#define AD7298_MAX_CHAN 8
dc4871ad LPC	38	#define AD7298_INTREF_mV 2500
	39
	40	#define AD7298_CH_TEMP 9
	41
dc4871ad LPC	42	struct ad7298_state {
	43	struct spi_device *spi;
	44	struct regulator *reg;
	45	unsigned ext_ref;
	46	struct spi_transfer ring_xfer[10];
	47	struct spi_transfer scan_single_xfer[3];
	48	struct spi_message ring_msg;
	49	struct spi_message scan_single_msg;
	50	/*
	51	* DMA (thus cache coherency maintenance) requires the
	52	* transfer buffers to live in their own cache lines.
	53	*/
be7fd3b8 JC	54	__be16 rx_buf[12] ____cacheline_aligned;
be7fd3b8 JC	55	__be16 tx_buf[2];
dc4871ad LPC	56	};
dc4871ad LPC	57
95e48f77 JC	58	#define AD7298_V_CHAN(index) \
	59	{ \
	60	.type = IIO_VOLTAGE, \
	61	.indexed = 1, \
	62	.channel = index, \
40dd676d JC	63	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
40dd676d JC	64	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
95e48f77 JC	65	.address = index, \
	66	.scan_index = index, \
	67	.scan_type = { \
	68	.sign = 'u', \
	69	.realbits = 12, \
	70	.storagebits = 16, \
ca654638	71	.endianness = IIO_BE, \
95e48f77 JC	72	}, \
	73	}
	74
f4e4b955	75	static const struct iio_chan_spec ad7298_channels[] = {
95e48f77 JC	76	{
	77	.type = IIO_TEMP,
	78	.indexed = 1,
	79	.channel = 0,
40dd676d JC	80	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \|
	81	BIT(IIO_CHAN_INFO_SCALE) \|
	82	BIT(IIO_CHAN_INFO_OFFSET),
d045b9d2 LPC	83	.address = AD7298_CH_TEMP,
d045b9d2 LPC	84	.scan_index = -1,
95e48f77 JC	85	.scan_type = {
	86	.sign = 's',
	87	.realbits = 32,
	88	.storagebits = 32,
	89	},
	90	},
	91	AD7298_V_CHAN(0),
	92	AD7298_V_CHAN(1),
	93	AD7298_V_CHAN(2),
	94	AD7298_V_CHAN(3),
	95	AD7298_V_CHAN(4),
	96	AD7298_V_CHAN(5),
	97	AD7298_V_CHAN(6),
	98	AD7298_V_CHAN(7),
01a99e18 MH	99	IIO_CHAN_SOFT_TIMESTAMP(8),
	100	};
	101
dc4871ad LPC	102	/**
	103	* ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
	104	**/
	105	static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	106	const unsigned long *active_scan_mask)
	107	{
	108	struct ad7298_state *st = iio_priv(indio_dev);
	109	int i, m;
	110	unsigned short command;
	111	int scan_count;
	112
	113	/* Now compute overall size */
	114	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
	115
	116	command = AD7298_WRITE \| st->ext_ref;
	117
	118	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
	119	if (test_bit(i, active_scan_mask))
	120	command \|= m;
	121
	122	st->tx_buf[0] = cpu_to_be16(command);
	123
	124	/* build spi ring message */
	125	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	126	st->ring_xfer[0].len = 2;
	127	st->ring_xfer[0].cs_change = 1;
	128	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	129	st->ring_xfer[1].len = 2;
	130	st->ring_xfer[1].cs_change = 1;
	131
	132	spi_message_init(&st->ring_msg);
	133	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	134	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
	135
	136	for (i = 0; i < scan_count; i++) {
	137	st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
	138	st->ring_xfer[i + 2].len = 2;
	139	st->ring_xfer[i + 2].cs_change = 1;
	140	spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	141	}
	142	/* make sure last transfer cs_change is not set */
	143	st->ring_xfer[i + 1].cs_change = 0;
	144
	145	return 0;
	146	}
	147
	148	/**
	149	* ad7298_trigger_handler() bh of trigger launched polling to ring buffer
	150	*
	151	* Currently there is no option in this driver to disable the saving of
	152	* timestamps within the ring.
	153	**/
	154	static irqreturn_t ad7298_trigger_handler(int irq, void *p)
	155	{
	156	struct iio_poll_func *pf = p;
	157	struct iio_dev *indio_dev = pf->indio_dev;
	158	struct ad7298_state *st = iio_priv(indio_dev);
dc4871ad LPC	159	int b_sent;
	160
	161	b_sent = spi_sync(st->spi, &st->ring_msg);
	162	if (b_sent)
	163	goto done;
	164
85ec2372	165	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
bc2b7dab	166	iio_get_time_ns(indio_dev));
dc4871ad LPC	167
	168	done:
	169	iio_trigger_notify_done(indio_dev->trig);
	170
	171	return IRQ_HANDLED;
	172	}
	173
7c31b984 MH	174	static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
	175	{
	176	int ret;
	177	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE \| st->ext_ref \|
	178	(AD7298_CH(0) >> ch));
	179
	180	ret = spi_sync(st->spi, &st->scan_single_msg);
	181	if (ret)
	182	return ret;
	183
	184	return be16_to_cpu(st->rx_buf[0]);
	185	}
	186
01a99e18	187	static int ad7298_scan_temp(struct ad7298_state st, int val)
7c31b984	188	{
01a10e04	189	int ret;
c1a75288	190	__be16 buf;
7c31b984	191
c1a75288	192	buf = cpu_to_be16(AD7298_WRITE \| AD7298_TSENSE \|
01a99e18	193	AD7298_TAVG \| st->ext_ref);
7c31b984	194
c1a75288	195	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18	196	if (ret)
7c31b984 MH	197	return ret;
7c31b984 MH	198
c1a75288	199	buf = cpu_to_be16(0);
7c31b984	200
c1a75288	201	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18 MH	202	if (ret)
01a99e18 MH	203	return ret;
7c31b984	204
7c31b984	205	usleep_range(101, 1000); /* sleep > 100us */
01a99e18	206
c1a75288	207	ret = spi_read(st->spi, (u8 *)&buf, 2);
01a99e18 MH	208	if (ret)
01a99e18 MH	209	return ret;
7c31b984	210
01a10e04	211	*val = sign_extend32(be16_to_cpu(buf), 11);
7c31b984	212
01a10e04 LPC	213	return 0;
	214	}
	215
	216	static int ad7298_get_ref_voltage(struct ad7298_state *st)
	217	{
	218	int vref;
7c31b984	219
01a10e04 LPC	220	if (st->ext_ref) {
	221	vref = regulator_get_voltage(st->reg);
	222	if (vref < 0)
	223	return vref;
7c31b984	224
01a10e04	225	return vref / 1000;
7c31b984	226	} else {
01a10e04	227	return AD7298_INTREF_mV;
7c31b984	228	}
01a99e18	229	}
7c31b984	230
84f79ecb	231	static int ad7298_read_raw(struct iio_dev *indio_dev,
01a99e18 MH	232	struct iio_chan_spec const *chan,
	233	int *val,
	234	int *val2,
	235	long m)
7c31b984	236	{
01a99e18	237	int ret;
84f79ecb	238	struct ad7298_state *st = iio_priv(indio_dev);
01a99e18 MH	239
01a99e18 MH	240	switch (m) {
b11f98ff	241	case IIO_CHAN_INFO_RAW:
d02ec00d AS	242	ret = iio_device_claim_direct_mode(indio_dev);
	243	if (ret)
	244	return ret;
	245
	246	if (chan->address == AD7298_CH_TEMP)
	247	ret = ad7298_scan_temp(st, val);
	248	else
	249	ret = ad7298_scan_direct(st, chan->address);
	250
	251	iio_device_release_direct_mode(indio_dev);
01a99e18 MH	252
	253	if (ret < 0)
	254	return ret;
	255
	256	if (chan->address != AD7298_CH_TEMP)
48898053	257	*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
01a99e18 MH	258
01a99e18 MH	259	return IIO_VAL_INT;
c8a9f805 JC	260	case IIO_CHAN_INFO_SCALE:
	261	switch (chan->type) {
	262	case IIO_VOLTAGE:
01a10e04	263	*val = ad7298_get_ref_voltage(st);
2e334600 LPC	264	*val2 = chan->scan_type.realbits;
2e334600 LPC	265	return IIO_VAL_FRACTIONAL_LOG2;
c8a9f805	266	case IIO_TEMP:
01a10e04 LPC	267	*val = ad7298_get_ref_voltage(st);
	268	*val2 = 10;
	269	return IIO_VAL_FRACTIONAL;
c8a9f805 JC	270	default:
	271	return -EINVAL;
	272	}
01a10e04 LPC	273	case IIO_CHAN_INFO_OFFSET:
	274	*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
	275	return IIO_VAL_INT;
01a99e18 MH	276	}
01a99e18 MH	277	return -EINVAL;
7c31b984	278	}
7c31b984	279
6fe8135f JC	280	static const struct iio_info ad7298_info = {
6fe8135f JC	281	.read_raw = &ad7298_read_raw,
d045b9d2	282	.update_scan_mode = ad7298_update_scan_mode,
6fe8135f JC	283	.driver_module = THIS_MODULE,
	284	};
	285
fc52692c	286	static int ad7298_probe(struct spi_device *spi)
7c31b984 MH	287	{
	288	struct ad7298_platform_data *pdata = spi->dev.platform_data;
	289	struct ad7298_state *st;
7abe9007	290	struct iio_dev *indio_dev;
2e334600	291	int ret;
7c31b984	292
7abe9007	293	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
cc4a48e4 MH	294	if (indio_dev == NULL)
	295	return -ENOMEM;
	296
	297	st = iio_priv(indio_dev);
7c31b984	298
2e334600 LPC	299	if (pdata && pdata->ext_ref)
	300	st->ext_ref = AD7298_EXTREF;
	301
	302	if (st->ext_ref) {
7abe9007 SK	303	st->reg = devm_regulator_get(&spi->dev, "vref");
	304	if (IS_ERR(st->reg))
	305	return PTR_ERR(st->reg);
	306
7c31b984 MH	307	ret = regulator_enable(st->reg);
7c31b984 MH	308	if (ret)
7abe9007	309	return ret;
7c31b984 MH	310	}
7c31b984 MH	311
cc4a48e4	312	spi_set_drvdata(spi, indio_dev);
7c31b984	313
7c31b984 MH	314	st->spi = spi;
7c31b984 MH	315
cc4a48e4 MH	316	indio_dev->name = spi_get_device_id(spi)->name;
cc4a48e4 MH	317	indio_dev->dev.parent = &spi->dev;
b541eaff	318	indio_dev->dev.of_node = spi->dev.of_node;
cc4a48e4 MH	319	indio_dev->modes = INDIO_DIRECT_MODE;
	320	indio_dev->channels = ad7298_channels;
	321	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
6fe8135f	322	indio_dev->info = &ad7298_info;
7c31b984 MH	323
	324	/* Setup default message */
	325
	326	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	327	st->scan_single_xfer[0].len = 2;
	328	st->scan_single_xfer[0].cs_change = 1;
	329	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	330	st->scan_single_xfer[1].len = 2;
	331	st->scan_single_xfer[1].cs_change = 1;
	332	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	333	st->scan_single_xfer[2].len = 2;
	334
	335	spi_message_init(&st->scan_single_msg);
	336	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	337	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	338	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
	339
dc4871ad LPC	340	ret = iio_triggered_buffer_setup(indio_dev, NULL,
dc4871ad LPC	341	&ad7298_trigger_handler, NULL);
7c31b984	342	if (ret)
cc4a48e4	343	goto error_disable_reg;
7c31b984	344
26d25ae3 JC	345	ret = iio_device_register(indio_dev);
26d25ae3 JC	346	if (ret)
d045b9d2	347	goto error_cleanup_ring;
cc4a48e4	348
7c31b984 MH	349	return 0;
	350
	351	error_cleanup_ring:
dc4871ad	352	iio_triggered_buffer_cleanup(indio_dev);
7c31b984	353	error_disable_reg:
2e334600	354	if (st->ext_ref)
7c31b984	355	regulator_disable(st->reg);
cc4a48e4	356
7c31b984 MH	357	return ret;
	358	}
	359
fc52692c	360	static int ad7298_remove(struct spi_device *spi)
7c31b984	361	{
cc4a48e4 MH	362	struct iio_dev *indio_dev = spi_get_drvdata(spi);
cc4a48e4 MH	363	struct ad7298_state *st = iio_priv(indio_dev);
7c31b984	364
d2fffd6c	365	iio_device_unregister(indio_dev);
dc4871ad	366	iio_triggered_buffer_cleanup(indio_dev);
7abe9007	367	if (st->ext_ref)
7c31b984	368	regulator_disable(st->reg);
cc4a48e4	369
7c31b984 MH	370	return 0;
	371	}
	372
	373	static const struct spi_device_id ad7298_id[] = {
	374	{"ad7298", 0},
	375	{}
	376	};
55e4390c	377	MODULE_DEVICE_TABLE(spi, ad7298_id);
7c31b984 MH	378
	379	static struct spi_driver ad7298_driver = {
	380	.driver = {
	381	.name = "ad7298",
7c31b984 MH	382	},
7c31b984 MH	383	.probe = ad7298_probe,
fc52692c	384	.remove = ad7298_remove,
7c31b984 MH	385	.id_table = ad7298_id,
7c31b984 MH	386	};
ae6ae6fe	387	module_spi_driver(ad7298_driver);
7c31b984 MH	388
	389	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
	390	MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
	391	MODULE_LICENSE("GPL v2");