[deliverable/linux.git] / drivers / iio / adc / ad7887.c

/*
 * AD7887 SPI ADC driver
 *
 * Copyright 2010-2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>

#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include <linux/platform_data/ad7887.h>

#define AD7887_REF_DIS		(1 << 5) /* on-chip reference disable */
#define AD7887_DUAL		(1 << 4) /* dual-channel mode */
#define AD7887_CH_AIN1		(1 << 3) /* convert on channel 1, DUAL=1 */
#define AD7887_CH_AIN0		(0 << 3) /* convert on channel 0, DUAL=0,1 */
#define AD7887_PM_MODE1		(0)	 /* CS based shutdown */
#define AD7887_PM_MODE2		(1)	 /* full on */
#define AD7887_PM_MODE3		(2)	 /* auto shutdown after conversion */
#define AD7887_PM_MODE4		(3)	 /* standby mode */

enum ad7887_channels {
	AD7887_CH0,
	AD7887_CH0_CH1,
	AD7887_CH1,
};

#define RES_MASK(bits)	((1 << (bits)) - 1)

/**
 * struct ad7887_chip_info - chip specifc information
 * @int_vref_mv:	the internal reference voltage
 * @channel:		channel specification
 */
struct ad7887_chip_info {
	u16				int_vref_mv;
	struct iio_chan_spec		channel[3];
};

struct ad7887_state {
	struct spi_device		*spi;
	const struct ad7887_chip_info	*chip_info;
	struct regulator		*reg;
	struct spi_transfer		xfer[4];
	struct spi_message		msg[3];
	struct spi_message		*ring_msg;
	unsigned char			tx_cmd_buf[4];

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 * Buffer needs to be large enough to hold two 16 bit samples and a
	 * 64 bit aligned 64 bit timestamp.
	 */
	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
		____cacheline_aligned;
};

enum ad7887_supported_device_ids {
	ID_AD7887
};

static int ad7887_ring_preenable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* We know this is a single long so can 'cheat' */
	switch (*indio_dev->active_scan_mask) {
	case (1 << 0):
		st->ring_msg = &st->msg[AD7887_CH0];
		break;
	case (1 << 1):
		st->ring_msg = &st->msg[AD7887_CH1];
		/* Dummy read: push CH1 setting down to hardware */
		spi_sync(st->spi, st->ring_msg);
		break;
	case ((1 << 1) | (1 << 0)):
		st->ring_msg = &st->msg[AD7887_CH0_CH1];
		break;
	}

	return 0;
}

static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* dummy read: restore default CH0 settin */
	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
}

/**
 * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 **/
static irqreturn_t ad7887_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7887_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
		iio_get_time_ns());
done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	.preenable = &ad7887_ring_preenable,
	.postenable = &iio_triggered_buffer_postenable,
	.predisable = &iio_triggered_buffer_predisable,
	.postdisable = &ad7887_ring_postdisable,
};

static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
{
	int ret = spi_sync(st->spi, &st->msg[ch]);
	if (ret)
		return ret;

	return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
}

static int ad7887_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7887_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		if (iio_buffer_enabled(indio_dev))
			ret = -EBUSY;
		else
			ret = ad7887_scan_direct(st, chan->address);
		mutex_unlock(&indio_dev->mlock);

		if (ret < 0)
			return ret;
		*val = ret >> chan->scan_type.shift;
		*val &= RES_MASK(chan->scan_type.realbits);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		if (st->reg) {
			*val = regulator_get_voltage(st->reg);
			if (*val < 0)
				return *val;
			*val /= 1000;
		} else {
			*val = st->chip_info->int_vref_mv;
		}

		*val2 = chan->scan_type.realbits;

		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}


static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	/*
	 * More devices added in future
	 */
	[ID_AD7887] = {
		.channel[0] = {
			.type = IIO_VOLTAGE,
			.indexed = 1,
			.channel = 1,
			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
			.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
			.address = 1,
			.scan_index = 1,
			.scan_type = IIO_ST('u', 12, 16, 0),
		},
		.channel[1] = {
			.type = IIO_VOLTAGE,
			.indexed = 1,
			.channel = 0,
			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
			.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
			.address = 0,
			.scan_index = 0,
			.scan_type = IIO_ST('u', 12, 16, 0),
		},
		.channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
		.int_vref_mv = 2500,
	},
};

static const struct iio_info ad7887_info = {
	.read_raw = &ad7887_read_raw,
	.driver_module = THIS_MODULE,
};

static int ad7887_probe(struct spi_device *spi)
{
	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	struct ad7887_state *st;
	struct iio_dev *indio_dev;
	uint8_t mode;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (!pdata || !pdata->use_onchip_ref) {
		st->reg = devm_regulator_get(&spi->dev, "vref");
		if (IS_ERR(st->reg))
			return PTR_ERR(st->reg);

		ret = regulator_enable(st->reg);
		if (ret)
			return ret;
	}

	st->chip_info =
		&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	spi_set_drvdata(spi, indio_dev);
	st->spi = spi;

	/* Estabilish that the iio_dev is a child of the spi device */
	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad7887_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	/* Setup default message */

	mode = AD7887_PM_MODE4;
	if (!pdata || !pdata->use_onchip_ref)
		mode |= AD7887_REF_DIS;
	if (pdata && pdata->en_dual)
		mode |= AD7887_DUAL;

	st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;

	st->xfer[0].rx_buf = &st->data[0];
	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	st->xfer[0].len = 2;

	spi_message_init(&st->msg[AD7887_CH0]);
	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);

	if (pdata && pdata->en_dual) {
		st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;

		st->xfer[1].rx_buf = &st->data[0];
		st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[1].len = 2;

		st->xfer[2].rx_buf = &st->data[2];
		st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
		st->xfer[2].len = 2;

		spi_message_init(&st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);

		st->xfer[3].rx_buf = &st->data[2];
		st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[3].len = 2;

		spi_message_init(&st->msg[AD7887_CH1]);
		spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);

		indio_dev->channels = st->chip_info->channel;
		indio_dev->num_channels = 3;
	} else {
		indio_dev->channels = &st->chip_info->channel[1];
		indio_dev->num_channels = 2;
	}

	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
			&ad7887_trigger_handler, &ad7887_ring_setup_ops);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_unregister_ring;

	return 0;
error_unregister_ring:
	iio_triggered_buffer_cleanup(indio_dev);
error_disable_reg:
	if (st->reg)
		regulator_disable(st->reg);

	return ret;
}

static int ad7887_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7887_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	if (st->reg)
		regulator_disable(st->reg);

	return 0;
}

static const struct spi_device_id ad7887_id[] = {
	{"ad7887", ID_AD7887},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7887_id);

static struct spi_driver ad7887_driver = {
	.driver = {
		.name	= "ad7887",
		.owner	= THIS_MODULE,
	},
	.probe		= ad7887_probe,
	.remove		= ad7887_remove,
	.id_table	= ad7887_id,
};
module_spi_driver(ad7887_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2b4756aa MH	1	/*
	2	* AD7887 SPI ADC driver
	3	*
596d0609	4	* Copyright 2010-2011 Analog Devices Inc.
2b4756aa	5	*
596d0609	6	* Licensed under the GPL-2.
2b4756aa MH	7	*/
2b4756aa MH	8
2b4756aa MH	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/sysfs.h>
2b4756aa MH	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
99c97852	16	#include <linux/module.h>
65dd3d3d	17	#include <linux/interrupt.h>
2b4756aa	18
06458e27 JC	19	#include <linux/iio/iio.h>
	20	#include <linux/iio/sysfs.h>
	21	#include <linux/iio/buffer.h>
cdf38709	22
65dd3d3d LPC	23	#include <linux/iio/trigger_consumer.h>
65dd3d3d LPC	24	#include <linux/iio/triggered_buffer.h>
2b4756aa	25
4eb3ccf1	26	#include <linux/platform_data/ad7887.h>
2b4756aa	27
65dd3d3d LPC	28	#define AD7887_REF_DIS (1 << 5) /* on-chip reference disable */
	29	#define AD7887_DUAL (1 << 4) /* dual-channel mode */
	30	#define AD7887_CH_AIN1 (1 << 3) /* convert on channel 1, DUAL=1 */
	31	#define AD7887_CH_AIN0 (0 << 3) /* convert on channel 0, DUAL=0,1 */
	32	#define AD7887_PM_MODE1 (0) /* CS based shutdown */
	33	#define AD7887_PM_MODE2 (1) /* full on */
	34	#define AD7887_PM_MODE3 (2) /* auto shutdown after conversion */
	35	#define AD7887_PM_MODE4 (3) /* standby mode */
	36
	37	enum ad7887_channels {
	38	AD7887_CH0,
	39	AD7887_CH0_CH1,
	40	AD7887_CH1,
	41	};
	42
	43	#define RES_MASK(bits) ((1 << (bits)) - 1)
	44
	45	/**
	46	* struct ad7887_chip_info - chip specifc information
	47	* @int_vref_mv: the internal reference voltage
	48	* @channel: channel specification
	49	*/
	50	struct ad7887_chip_info {
	51	u16 int_vref_mv;
	52	struct iio_chan_spec channel[3];
	53	};
	54
	55	struct ad7887_state {
	56	struct spi_device *spi;
	57	const struct ad7887_chip_info *chip_info;
	58	struct regulator *reg;
	59	struct spi_transfer xfer[4];
	60	struct spi_message msg[3];
	61	struct spi_message *ring_msg;
fce7c3ea	62	unsigned char tx_cmd_buf[4];
65dd3d3d LPC	63
	64	/*
	65	* DMA (thus cache coherency maintenance) requires the
	66	* transfer buffers to live in their own cache lines.
	67	* Buffer needs to be large enough to hold two 16 bit samples and a
	68	* 64 bit aligned 64 bit timestamp.
	69	*/
	70	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
	71	____cacheline_aligned;
	72	};
	73
	74	enum ad7887_supported_device_ids {
	75	ID_AD7887
	76	};
	77
	78	static int ad7887_ring_preenable(struct iio_dev *indio_dev)
	79	{
	80	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	81
	82	/* We know this is a single long so can 'cheat' */
	83	switch (*indio_dev->active_scan_mask) {
	84	case (1 << 0):
	85	st->ring_msg = &st->msg[AD7887_CH0];
	86	break;
	87	case (1 << 1):
	88	st->ring_msg = &st->msg[AD7887_CH1];
	89	/* Dummy read: push CH1 setting down to hardware */
	90	spi_sync(st->spi, st->ring_msg);
	91	break;
	92	case ((1 << 1) \| (1 << 0)):
	93	st->ring_msg = &st->msg[AD7887_CH0_CH1];
	94	break;
	95	}
	96
	97	return 0;
	98	}
	99
	100	static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
	101	{
	102	struct ad7887_state *st = iio_priv(indio_dev);
	103
	104	/* dummy read: restore default CH0 settin */
	105	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
	106	}
	107
	108	/**
	109	* ad7887_trigger_handler() bh of trigger launched polling to ring buffer
	110	*
	111	* Currently there is no option in this driver to disable the saving of
	112	* timestamps within the ring.
	113	**/
	114	static irqreturn_t ad7887_trigger_handler(int irq, void *p)
	115	{
	116	struct iio_poll_func *pf = p;
	117	struct iio_dev *indio_dev = pf->indio_dev;
	118	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	119	int b_sent;
	120
	121	b_sent = spi_sync(st->spi, st->ring_msg);
	122	if (b_sent)
	123	goto done;
	124
5afd602b LPC	125	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
5afd602b LPC	126	iio_get_time_ns());
65dd3d3d LPC	127	done:
	128	iio_trigger_notify_done(indio_dev->trig);
	129
	130	return IRQ_HANDLED;
	131	}
	132
	133	static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	134	.preenable = &ad7887_ring_preenable,
	135	.postenable = &iio_triggered_buffer_postenable,
	136	.predisable = &iio_triggered_buffer_predisable,
	137	.postdisable = &ad7887_ring_postdisable,
	138	};
	139
2b4756aa MH	140	static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
	141	{
	142	int ret = spi_sync(st->spi, &st->msg[ch]);
	143	if (ret)
	144	return ret;
	145
	146	return (st->data[(ch * 2)] << 8) \| st->data[(ch * 2) + 1];
	147	}
	148
84f79ecb	149	static int ad7887_read_raw(struct iio_dev *indio_dev,
596d0609 MH	150	struct iio_chan_spec const *chan,
	151	int *val,
	152	int *val2,
	153	long m)
2b4756aa	154	{
2b4756aa	155	int ret;
84f79ecb	156	struct ad7887_state *st = iio_priv(indio_dev);
2b4756aa	157
596d0609	158	switch (m) {
b11f98ff	159	case IIO_CHAN_INFO_RAW:
84f79ecb JC	160	mutex_lock(&indio_dev->mlock);
84f79ecb JC	161	if (iio_buffer_enabled(indio_dev))
790d8759	162	ret = -EBUSY;
596d0609 MH	163	else
596d0609 MH	164	ret = ad7887_scan_direct(st, chan->address);
84f79ecb	165	mutex_unlock(&indio_dev->mlock);
596d0609 MH	166
	167	if (ret < 0)
	168	return ret;
98efb70a LPC	169	*val = ret >> chan->scan_type.shift;
98efb70a LPC	170	*val &= RES_MASK(chan->scan_type.realbits);
596d0609	171	return IIO_VAL_INT;
c8a9f805	172	case IIO_CHAN_INFO_SCALE:
bf5d2613 LPC	173	if (st->reg) {
	174	*val = regulator_get_voltage(st->reg);
	175	if (*val < 0)
	176	return *val;
	177	*val /= 1000;
	178	} else {
	179	*val = st->chip_info->int_vref_mv;
	180	}
	181
98efb70a	182	*val2 = chan->scan_type.realbits;
bf5d2613 LPC	183
bf5d2613 LPC	184	return IIO_VAL_FRACTIONAL_LOG2;
596d0609 MH	185	}
596d0609 MH	186	return -EINVAL;
2b4756aa MH	187	}
2b4756aa MH	188
2b4756aa MH	189
	190	static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	191	/*
	192	* More devices added in future
	193	*/
	194	[ID_AD7887] = {
31bf47d5 JC	195	.channel[0] = {
	196	.type = IIO_VOLTAGE,
	197	.indexed = 1,
	198	.channel = 1,
16d186b1 JC	199	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
16d186b1 JC	200	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
31bf47d5 JC	201	.address = 1,
	202	.scan_index = 1,
	203	.scan_type = IIO_ST('u', 12, 16, 0),
	204	},
	205	.channel[1] = {
	206	.type = IIO_VOLTAGE,
	207	.indexed = 1,
	208	.channel = 0,
16d186b1 JC	209	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
16d186b1 JC	210	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
31bf47d5 JC	211	.address = 0,
	212	.scan_index = 0,
	213	.scan_type = IIO_ST('u', 12, 16, 0),
	214	},
596d0609	215	.channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
2b4756aa MH	216	.int_vref_mv = 2500,
	217	},
	218	};
	219
6fe8135f JC	220	static const struct iio_info ad7887_info = {
	221	.read_raw = &ad7887_read_raw,
	222	.driver_module = THIS_MODULE,
	223	};
	224
fc52692c	225	static int ad7887_probe(struct spi_device *spi)
2b4756aa MH	226	{
	227	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	228	struct ad7887_state *st;
82429e0d	229	struct iio_dev *indio_dev;
fce7c3ea	230	uint8_t mode;
bf5d2613	231	int ret;
2b4756aa	232
82429e0d	233	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
f39e086a MH	234	if (indio_dev == NULL)
	235	return -ENOMEM;
	236
	237	st = iio_priv(indio_dev);
2b4756aa	238
bf5d2613	239	if (!pdata \|\| !pdata->use_onchip_ref) {
82429e0d SK	240	st->reg = devm_regulator_get(&spi->dev, "vref");
	241	if (IS_ERR(st->reg))
	242	return PTR_ERR(st->reg);
bf5d2613	243
2b4756aa MH	244	ret = regulator_enable(st->reg);
2b4756aa MH	245	if (ret)
82429e0d	246	return ret;
2b4756aa MH	247	}
	248
	249	st->chip_info =
	250	&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	251
f39e086a	252	spi_set_drvdata(spi, indio_dev);
2b4756aa MH	253	st->spi = spi;
2b4756aa MH	254
2b4756aa	255	/* Estabilish that the iio_dev is a child of the spi device */
f39e086a MH	256	indio_dev->dev.parent = &spi->dev;
f39e086a MH	257	indio_dev->name = spi_get_device_id(spi)->name;
6fe8135f	258	indio_dev->info = &ad7887_info;
f39e086a	259	indio_dev->modes = INDIO_DIRECT_MODE;
2b4756aa MH	260
	261	/* Setup default message */
	262
fce7c3ea LPC	263	mode = AD7887_PM_MODE4;
	264	if (!pdata \|\| !pdata->use_onchip_ref)
	265	mode \|= AD7887_REF_DIS;
	266	if (pdata && pdata->en_dual)
	267	mode \|= AD7887_DUAL;
	268
	269	st->tx_cmd_buf[0] = AD7887_CH_AIN0 \| mode;
2b4756aa MH	270
	271	st->xfer[0].rx_buf = &st->data[0];
	272	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	273	st->xfer[0].len = 2;
	274
	275	spi_message_init(&st->msg[AD7887_CH0]);
	276	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
	277
	278	if (pdata && pdata->en_dual) {
fce7c3ea	279	st->tx_cmd_buf[2] = AD7887_CH_AIN1 \| mode;
2b4756aa MH	280
	281	st->xfer[1].rx_buf = &st->data[0];
	282	st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
	283	st->xfer[1].len = 2;
	284
	285	st->xfer[2].rx_buf = &st->data[2];
fce7c3ea	286	st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
2b4756aa MH	287	st->xfer[2].len = 2;
	288
	289	spi_message_init(&st->msg[AD7887_CH0_CH1]);
	290	spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
	291	spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
	292
fce7c3ea LPC	293	st->xfer[3].rx_buf = &st->data[2];
fce7c3ea LPC	294	st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
2b4756aa MH	295	st->xfer[3].len = 2;
	296
	297	spi_message_init(&st->msg[AD7887_CH1]);
	298	spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
	299
f39e086a MH	300	indio_dev->channels = st->chip_info->channel;
f39e086a MH	301	indio_dev->num_channels = 3;
2b4756aa	302	} else {
f39e086a MH	303	indio_dev->channels = &st->chip_info->channel[1];
f39e086a MH	304	indio_dev->num_channels = 2;
596d0609	305	}
2b4756aa	306
65dd3d3d LPC	307	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
65dd3d3d LPC	308	&ad7887_trigger_handler, &ad7887_ring_setup_ops);
2b4756aa	309	if (ret)
f39e086a	310	goto error_disable_reg;
2b4756aa	311
26d25ae3 JC	312	ret = iio_device_register(indio_dev);
	313	if (ret)
	314	goto error_unregister_ring;
	315
	316	return 0;
	317	error_unregister_ring:
65dd3d3d	318	iio_triggered_buffer_cleanup(indio_dev);
2b4756aa	319	error_disable_reg:
bf5d2613	320	if (st->reg)
2b4756aa	321	regulator_disable(st->reg);
f39e086a	322
2b4756aa MH	323	return ret;
	324	}
	325
fc52692c	326	static int ad7887_remove(struct spi_device *spi)
2b4756aa	327	{
f39e086a MH	328	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	329	struct ad7887_state *st = iio_priv(indio_dev);
	330
d2fffd6c	331	iio_device_unregister(indio_dev);
65dd3d3d	332	iio_triggered_buffer_cleanup(indio_dev);
82429e0d	333	if (st->reg)
2b4756aa	334	regulator_disable(st->reg);
f39e086a	335
2b4756aa MH	336	return 0;
	337	}
	338
	339	static const struct spi_device_id ad7887_id[] = {
	340	{"ad7887", ID_AD7887},
	341	{}
	342	};
55e4390c	343	MODULE_DEVICE_TABLE(spi, ad7887_id);
2b4756aa MH	344
	345	static struct spi_driver ad7887_driver = {
	346	.driver = {
	347	.name = "ad7887",
2b4756aa MH	348	.owner = THIS_MODULE,
	349	},
	350	.probe = ad7887_probe,
fc52692c	351	.remove = ad7887_remove,
2b4756aa MH	352	.id_table = ad7887_id,
2b4756aa MH	353	};
ae6ae6fe	354	module_spi_driver(ad7887_driver);
2b4756aa MH	355
	356	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
	357	MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
	358	MODULE_LICENSE("GPL v2");