Commit | Line | Data |
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0eac259d | 1 | /* |
f2f7a449 | 2 | * AD7904/AD7914/AD7923/AD7924 SPI ADC driver |
0eac259d CL |
3 | * |
4 | * Copyright 2011 Analog Devices Inc (from AD7923 Driver) | |
5 | * Copyright 2012 CS Systemes d'Information | |
6 | * | |
7 | * Licensed under the GPL-2. | |
8 | */ | |
9 | ||
10 | #include <linux/device.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sysfs.h> | |
14 | #include <linux/spi/spi.h> | |
ecf6ca25 | 15 | #include <linux/regulator/consumer.h> |
0eac259d CL |
16 | #include <linux/err.h> |
17 | #include <linux/delay.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/interrupt.h> | |
20 | ||
21 | #include <linux/iio/iio.h> | |
22 | #include <linux/iio/sysfs.h> | |
23 | #include <linux/iio/buffer.h> | |
24 | #include <linux/iio/trigger_consumer.h> | |
25 | #include <linux/iio/triggered_buffer.h> | |
26 | ||
27 | #define AD7923_WRITE_CR (1 << 11) /* write control register */ | |
28 | #define AD7923_RANGE (1 << 1) /* range to REFin */ | |
29 | #define AD7923_CODING (1 << 0) /* coding is straight binary */ | |
30 | #define AD7923_PM_MODE_AS (1) /* auto shutdown */ | |
31 | #define AD7923_PM_MODE_FS (2) /* full shutdown */ | |
32 | #define AD7923_PM_MODE_OPS (3) /* normal operation */ | |
33 | #define AD7923_CHANNEL_0 (0) /* analog input 0 */ | |
34 | #define AD7923_CHANNEL_1 (1) /* analog input 1 */ | |
35 | #define AD7923_CHANNEL_2 (2) /* analog input 2 */ | |
36 | #define AD7923_CHANNEL_3 (3) /* analog input 3 */ | |
37 | #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */ | |
38 | #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */ | |
39 | #define AD7923_SEQUENCE_ON (3) /* continuous sequence */ | |
40 | ||
41 | #define AD7923_MAX_CHAN 4 | |
42 | ||
43 | #define AD7923_PM_MODE_WRITE(mode) (mode << 4) /* write mode */ | |
44 | #define AD7923_CHANNEL_WRITE(channel) (channel << 6) /* write channel */ | |
45 | #define AD7923_SEQUENCE_WRITE(sequence) (((sequence & 1) << 3) \ | |
46 | + ((sequence & 2) << 9)) | |
47 | /* write sequence fonction */ | |
48 | /* left shift for CR : bit 11 transmit in first */ | |
49 | #define AD7923_SHIFT_REGISTER 4 | |
50 | ||
51 | /* val = value, dec = left shift, bits = number of bits of the mask */ | |
52 | #define EXTRACT(val, dec, bits) ((val >> dec) & ((1 << bits) - 1)) | |
53 | ||
54 | struct ad7923_state { | |
55 | struct spi_device *spi; | |
56 | struct spi_transfer ring_xfer[5]; | |
57 | struct spi_transfer scan_single_xfer[2]; | |
58 | struct spi_message ring_msg; | |
59 | struct spi_message scan_single_msg; | |
ecf6ca25 LPC |
60 | |
61 | struct regulator *reg; | |
62 | ||
63 | unsigned int settings; | |
64 | ||
0eac259d CL |
65 | /* |
66 | * DMA (thus cache coherency maintenance) requires the | |
67 | * transfer buffers to live in their own cache lines. | |
68 | */ | |
69 | __be16 rx_buf[4] ____cacheline_aligned; | |
70 | __be16 tx_buf[4]; | |
71 | }; | |
72 | ||
f2f7a449 LPC |
73 | struct ad7923_chip_info { |
74 | const struct iio_chan_spec *channels; | |
75 | unsigned int num_channels; | |
76 | }; | |
77 | ||
78 | enum ad7923_id { | |
79 | AD7904, | |
80 | AD7914, | |
81 | AD7924, | |
82 | }; | |
83 | ||
84 | #define AD7923_V_CHAN(index, bits) \ | |
0eac259d CL |
85 | { \ |
86 | .type = IIO_VOLTAGE, \ | |
87 | .indexed = 1, \ | |
88 | .channel = index, \ | |
7657719f JC |
89 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
90 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | |
0eac259d CL |
91 | .address = index, \ |
92 | .scan_index = index, \ | |
93 | .scan_type = { \ | |
94 | .sign = 'u', \ | |
f2f7a449 | 95 | .realbits = (bits), \ |
0eac259d CL |
96 | .storagebits = 16, \ |
97 | .endianness = IIO_BE, \ | |
98 | }, \ | |
99 | } | |
100 | ||
f2f7a449 LPC |
101 | #define DECLARE_AD7923_CHANNELS(name, bits) \ |
102 | const struct iio_chan_spec name ## _channels[] = { \ | |
103 | AD7923_V_CHAN(0, bits), \ | |
104 | AD7923_V_CHAN(1, bits), \ | |
105 | AD7923_V_CHAN(2, bits), \ | |
106 | AD7923_V_CHAN(3, bits), \ | |
107 | IIO_CHAN_SOFT_TIMESTAMP(4), \ | |
108 | } | |
109 | ||
110 | static DECLARE_AD7923_CHANNELS(ad7904, 8); | |
111 | static DECLARE_AD7923_CHANNELS(ad7914, 10); | |
112 | static DECLARE_AD7923_CHANNELS(ad7924, 12); | |
113 | ||
114 | static const struct ad7923_chip_info ad7923_chip_info[] = { | |
115 | [AD7904] = { | |
116 | .channels = ad7904_channels, | |
117 | .num_channels = ARRAY_SIZE(ad7904_channels), | |
118 | }, | |
119 | [AD7914] = { | |
120 | .channels = ad7914_channels, | |
121 | .num_channels = ARRAY_SIZE(ad7914_channels), | |
122 | }, | |
123 | [AD7924] = { | |
124 | .channels = ad7924_channels, | |
125 | .num_channels = ARRAY_SIZE(ad7924_channels), | |
126 | }, | |
0eac259d CL |
127 | }; |
128 | ||
129 | /** | |
130 | * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask | |
131 | **/ | |
132 | static int ad7923_update_scan_mode(struct iio_dev *indio_dev, | |
133 | const unsigned long *active_scan_mask) | |
134 | { | |
135 | struct ad7923_state *st = iio_priv(indio_dev); | |
136 | int i, cmd, len; | |
137 | ||
138 | len = 0; | |
139 | for_each_set_bit(i, active_scan_mask, AD7923_MAX_CHAN) { | |
ecf6ca25 | 140 | cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) | |
0eac259d | 141 | AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) | |
ecf6ca25 | 142 | st->settings; |
0eac259d CL |
143 | cmd <<= AD7923_SHIFT_REGISTER; |
144 | st->tx_buf[len++] = cpu_to_be16(cmd); | |
145 | } | |
146 | /* build spi ring message */ | |
147 | st->ring_xfer[0].tx_buf = &st->tx_buf[0]; | |
148 | st->ring_xfer[0].len = len; | |
149 | st->ring_xfer[0].cs_change = 1; | |
150 | ||
151 | spi_message_init(&st->ring_msg); | |
152 | spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg); | |
153 | ||
154 | for (i = 0; i < len; i++) { | |
155 | st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i]; | |
156 | st->ring_xfer[i + 1].len = 2; | |
157 | st->ring_xfer[i + 1].cs_change = 1; | |
158 | spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg); | |
159 | } | |
160 | /* make sure last transfer cs_change is not set */ | |
161 | st->ring_xfer[i + 1].cs_change = 0; | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | /** | |
167 | * ad7923_trigger_handler() bh of trigger launched polling to ring buffer | |
168 | * | |
169 | * Currently there is no option in this driver to disable the saving of | |
170 | * timestamps within the ring. | |
171 | **/ | |
172 | static irqreturn_t ad7923_trigger_handler(int irq, void *p) | |
173 | { | |
174 | struct iio_poll_func *pf = p; | |
175 | struct iio_dev *indio_dev = pf->indio_dev; | |
176 | struct ad7923_state *st = iio_priv(indio_dev); | |
177 | s64 time_ns = 0; | |
178 | int b_sent; | |
179 | ||
180 | b_sent = spi_sync(st->spi, &st->ring_msg); | |
181 | if (b_sent) | |
182 | goto done; | |
183 | ||
184 | if (indio_dev->scan_timestamp) { | |
185 | time_ns = iio_get_time_ns(); | |
186 | memcpy((u8 *)st->rx_buf + indio_dev->scan_bytes - sizeof(s64), | |
187 | &time_ns, sizeof(time_ns)); | |
188 | } | |
189 | ||
190 | iio_push_to_buffers(indio_dev, (u8 *)st->rx_buf); | |
191 | ||
192 | done: | |
193 | iio_trigger_notify_done(indio_dev->trig); | |
194 | ||
195 | return IRQ_HANDLED; | |
196 | } | |
197 | ||
198 | static int ad7923_scan_direct(struct ad7923_state *st, unsigned ch) | |
199 | { | |
200 | int ret, cmd; | |
201 | ||
ecf6ca25 LPC |
202 | cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) | |
203 | AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) | | |
204 | st->settings; | |
0eac259d CL |
205 | cmd <<= AD7923_SHIFT_REGISTER; |
206 | st->tx_buf[0] = cpu_to_be16(cmd); | |
207 | ||
208 | ret = spi_sync(st->spi, &st->scan_single_msg); | |
209 | if (ret) | |
210 | return ret; | |
211 | ||
212 | return be16_to_cpu(st->rx_buf[0]); | |
213 | } | |
214 | ||
ecf6ca25 LPC |
215 | static int ad7923_get_range(struct ad7923_state *st) |
216 | { | |
217 | int vref; | |
218 | ||
219 | vref = regulator_get_voltage(st->reg); | |
220 | if (vref < 0) | |
221 | return vref; | |
222 | ||
223 | vref /= 1000; | |
224 | ||
225 | if (!(st->settings & AD7923_RANGE)) | |
226 | vref *= 2; | |
227 | ||
228 | return vref; | |
229 | } | |
230 | ||
0eac259d CL |
231 | static int ad7923_read_raw(struct iio_dev *indio_dev, |
232 | struct iio_chan_spec const *chan, | |
233 | int *val, | |
234 | int *val2, | |
235 | long m) | |
236 | { | |
237 | int ret; | |
238 | struct ad7923_state *st = iio_priv(indio_dev); | |
239 | ||
240 | switch (m) { | |
241 | case IIO_CHAN_INFO_RAW: | |
242 | mutex_lock(&indio_dev->mlock); | |
243 | if (iio_buffer_enabled(indio_dev)) | |
244 | ret = -EBUSY; | |
245 | else | |
246 | ret = ad7923_scan_direct(st, chan->address); | |
247 | mutex_unlock(&indio_dev->mlock); | |
248 | ||
249 | if (ret < 0) | |
250 | return ret; | |
251 | ||
252 | if (chan->address == EXTRACT(ret, 12, 4)) | |
253 | *val = EXTRACT(ret, 0, 12); | |
135f0646 LPC |
254 | else |
255 | return -EIO; | |
0eac259d CL |
256 | |
257 | return IIO_VAL_INT; | |
ecf6ca25 LPC |
258 | case IIO_CHAN_INFO_SCALE: |
259 | ret = ad7923_get_range(st); | |
260 | if (ret < 0) | |
261 | return ret; | |
262 | *val = ret; | |
263 | *val2 = chan->scan_type.realbits; | |
264 | return IIO_VAL_FRACTIONAL_LOG2; | |
0eac259d CL |
265 | } |
266 | return -EINVAL; | |
267 | } | |
268 | ||
269 | static const struct iio_info ad7923_info = { | |
270 | .read_raw = &ad7923_read_raw, | |
271 | .update_scan_mode = ad7923_update_scan_mode, | |
272 | .driver_module = THIS_MODULE, | |
273 | }; | |
274 | ||
275 | static int ad7923_probe(struct spi_device *spi) | |
276 | { | |
277 | struct ad7923_state *st; | |
278 | struct iio_dev *indio_dev = iio_device_alloc(sizeof(*st)); | |
f2f7a449 | 279 | const struct ad7923_chip_info *info; |
0eac259d CL |
280 | int ret; |
281 | ||
282 | if (indio_dev == NULL) | |
283 | return -ENOMEM; | |
284 | ||
285 | st = iio_priv(indio_dev); | |
286 | ||
287 | spi_set_drvdata(spi, indio_dev); | |
288 | ||
289 | st->spi = spi; | |
ecf6ca25 LPC |
290 | st->settings = AD7923_CODING | AD7923_RANGE | |
291 | AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS); | |
0eac259d | 292 | |
f2f7a449 LPC |
293 | info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data]; |
294 | ||
0eac259d CL |
295 | indio_dev->name = spi_get_device_id(spi)->name; |
296 | indio_dev->dev.parent = &spi->dev; | |
297 | indio_dev->modes = INDIO_DIRECT_MODE; | |
f2f7a449 LPC |
298 | indio_dev->channels = info->channels; |
299 | indio_dev->num_channels = info->num_channels; | |
0eac259d CL |
300 | indio_dev->info = &ad7923_info; |
301 | ||
302 | /* Setup default message */ | |
303 | ||
304 | st->scan_single_xfer[0].tx_buf = &st->tx_buf[0]; | |
305 | st->scan_single_xfer[0].len = 2; | |
306 | st->scan_single_xfer[0].cs_change = 1; | |
307 | st->scan_single_xfer[1].rx_buf = &st->rx_buf[0]; | |
308 | st->scan_single_xfer[1].len = 2; | |
309 | ||
310 | spi_message_init(&st->scan_single_msg); | |
311 | spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg); | |
312 | spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg); | |
313 | ||
ecf6ca25 LPC |
314 | st->reg = regulator_get(&spi->dev, "refin"); |
315 | if (IS_ERR(st->reg)) { | |
316 | ret = PTR_ERR(st->reg); | |
317 | goto error_free; | |
318 | } | |
319 | ret = regulator_enable(st->reg); | |
320 | if (ret) | |
321 | goto error_put_reg; | |
322 | ||
0eac259d CL |
323 | ret = iio_triggered_buffer_setup(indio_dev, NULL, |
324 | &ad7923_trigger_handler, NULL); | |
325 | if (ret) | |
ecf6ca25 | 326 | goto error_disable_reg; |
0eac259d CL |
327 | |
328 | ret = iio_device_register(indio_dev); | |
329 | if (ret) | |
330 | goto error_cleanup_ring; | |
331 | ||
332 | return 0; | |
333 | ||
334 | error_cleanup_ring: | |
335 | iio_triggered_buffer_cleanup(indio_dev); | |
ecf6ca25 LPC |
336 | error_disable_reg: |
337 | regulator_disable(st->reg); | |
338 | error_put_reg: | |
339 | regulator_put(st->reg); | |
0eac259d CL |
340 | error_free: |
341 | iio_device_free(indio_dev); | |
342 | ||
343 | return ret; | |
344 | } | |
345 | ||
346 | static int ad7923_remove(struct spi_device *spi) | |
347 | { | |
348 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
ecf6ca25 | 349 | struct ad7923_state *st = iio_priv(indio_dev); |
0eac259d CL |
350 | |
351 | iio_device_unregister(indio_dev); | |
352 | iio_triggered_buffer_cleanup(indio_dev); | |
ecf6ca25 LPC |
353 | regulator_disable(st->reg); |
354 | regulator_put(st->reg); | |
0eac259d CL |
355 | iio_device_free(indio_dev); |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static const struct spi_device_id ad7923_id[] = { | |
f2f7a449 LPC |
361 | {"ad7904", AD7904}, |
362 | {"ad7914", AD7914}, | |
363 | {"ad7923", AD7924}, | |
364 | {"ad7924", AD7924}, | |
0eac259d CL |
365 | {} |
366 | }; | |
367 | MODULE_DEVICE_TABLE(spi, ad7923_id); | |
368 | ||
369 | static struct spi_driver ad7923_driver = { | |
370 | .driver = { | |
371 | .name = "ad7923", | |
372 | .owner = THIS_MODULE, | |
373 | }, | |
374 | .probe = ad7923_probe, | |
375 | .remove = ad7923_remove, | |
376 | .id_table = ad7923_id, | |
377 | }; | |
378 | module_spi_driver(ad7923_driver); | |
379 | ||
380 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
381 | MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>"); | |
f2f7a449 | 382 | MODULE_DESCRIPTION("Analog Devices AD7904/AD7914/AD7923/AD7924 ADC"); |
0eac259d | 383 | MODULE_LICENSE("GPL v2"); |